From a4e969f4965059196ca948db781e52f7cfebf19e Mon Sep 17 00:00:00 2001 From: Lorry Tar Creator Date: Tue, 24 May 2016 08:28:08 +0000 Subject: webkitgtk-2.12.3 --- .../disassembler/ARM64/A64DOpcode.cpp | 70 + .../JavaScriptCore/disassembler/ARM64/A64DOpcode.h | 20 +- .../disassembler/ARM64Disassembler.cpp | 5 +- .../disassembler/ARMv7/ARMv7DOpcode.cpp | 1733 ++++ .../disassembler/ARMv7/ARMv7DOpcode.h | 1237 +++ .../disassembler/ARMv7Disassembler.cpp | 55 + .../JavaScriptCore/disassembler/Disassembler.cpp | 117 +- Source/JavaScriptCore/disassembler/Disassembler.h | 22 +- .../disassembler/LLVMDisassembler.cpp | 131 - .../JavaScriptCore/disassembler/LLVMDisassembler.h | 46 - .../disassembler/UDis86Disassembler.cpp | 63 + .../disassembler/UDis86Disassembler.h | 46 + .../disassembler/X86Disassembler.cpp | 38 +- .../disassembler/udis86/differences.txt | 24 + Source/JavaScriptCore/disassembler/udis86/itab.py | 360 + .../JavaScriptCore/disassembler/udis86/optable.xml | 8959 ++++++++++++++++++++ .../disassembler/udis86/ud_opcode.py | 235 + .../disassembler/udis86/ud_optable.py | 103 + Source/JavaScriptCore/disassembler/udis86/udis86.c | 182 + Source/JavaScriptCore/disassembler/udis86/udis86.h | 33 + .../disassembler/udis86/udis86_decode.c | 1142 +++ .../disassembler/udis86/udis86_decode.h | 258 + .../disassembler/udis86/udis86_extern.h | 88 + .../disassembler/udis86/udis86_input.c | 262 + .../disassembler/udis86/udis86_input.h | 67 + .../disassembler/udis86/udis86_itab_holder.c | 33 + .../disassembler/udis86/udis86_syn-att.c | 265 + .../disassembler/udis86/udis86_syn-intel.c | 278 + .../disassembler/udis86/udis86_syn.c | 86 + .../disassembler/udis86/udis86_syn.h | 47 + .../disassembler/udis86/udis86_types.h | 242 + 31 files changed, 16020 insertions(+), 227 deletions(-) create mode 100644 Source/JavaScriptCore/disassembler/ARMv7/ARMv7DOpcode.cpp create mode 100644 Source/JavaScriptCore/disassembler/ARMv7/ARMv7DOpcode.h create mode 100644 Source/JavaScriptCore/disassembler/ARMv7Disassembler.cpp delete mode 100644 Source/JavaScriptCore/disassembler/LLVMDisassembler.cpp delete mode 100644 Source/JavaScriptCore/disassembler/LLVMDisassembler.h create mode 100644 Source/JavaScriptCore/disassembler/UDis86Disassembler.cpp create mode 100644 Source/JavaScriptCore/disassembler/UDis86Disassembler.h create mode 100644 Source/JavaScriptCore/disassembler/udis86/differences.txt create mode 100644 Source/JavaScriptCore/disassembler/udis86/itab.py create mode 100644 Source/JavaScriptCore/disassembler/udis86/optable.xml create mode 100644 Source/JavaScriptCore/disassembler/udis86/ud_opcode.py create mode 100644 Source/JavaScriptCore/disassembler/udis86/ud_optable.py create mode 100644 Source/JavaScriptCore/disassembler/udis86/udis86.c create mode 100644 Source/JavaScriptCore/disassembler/udis86/udis86.h create mode 100644 Source/JavaScriptCore/disassembler/udis86/udis86_decode.c create mode 100644 Source/JavaScriptCore/disassembler/udis86/udis86_decode.h create mode 100644 Source/JavaScriptCore/disassembler/udis86/udis86_extern.h create mode 100644 Source/JavaScriptCore/disassembler/udis86/udis86_input.c create mode 100644 Source/JavaScriptCore/disassembler/udis86/udis86_input.h create mode 100644 Source/JavaScriptCore/disassembler/udis86/udis86_itab_holder.c create mode 100644 Source/JavaScriptCore/disassembler/udis86/udis86_syn-att.c create mode 100644 Source/JavaScriptCore/disassembler/udis86/udis86_syn-intel.c create mode 100644 Source/JavaScriptCore/disassembler/udis86/udis86_syn.c create mode 100644 Source/JavaScriptCore/disassembler/udis86/udis86_syn.h create mode 100644 Source/JavaScriptCore/disassembler/udis86/udis86_types.h (limited to 'Source/JavaScriptCore/disassembler') diff --git a/Source/JavaScriptCore/disassembler/ARM64/A64DOpcode.cpp b/Source/JavaScriptCore/disassembler/ARM64/A64DOpcode.cpp index 0ea817a46..52a92c669 100644 --- a/Source/JavaScriptCore/disassembler/ARM64/A64DOpcode.cpp +++ b/Source/JavaScriptCore/disassembler/ARM64/A64DOpcode.cpp @@ -23,7 +23,11 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +#define __STDC_FORMAT_MACROS #include "config.h" + +#if USE(ARM64_DISASSEMBLER) + #include "A64DOpcode.h" #include @@ -62,6 +66,8 @@ struct OpcodeGroupInitializer { { groupIndex, groupClass::mask, groupClass::pattern, groupClass::format } static OpcodeGroupInitializer opcodeGroupList[] = { + OPCODE_GROUP_ENTRY(0x08, A64DOpcodeLoadStoreRegisterPair), + OPCODE_GROUP_ENTRY(0x09, A64DOpcodeLoadStoreRegisterPair), OPCODE_GROUP_ENTRY(0x0a, A64DOpcodeLogicalShiftedRegister), OPCODE_GROUP_ENTRY(0x0b, A64DOpcodeAddSubtractExtendedRegister), OPCODE_GROUP_ENTRY(0x0b, A64DOpcodeAddSubtractShiftedRegister), @@ -172,6 +178,11 @@ const char* A64DOpcode::format() void A64DOpcode::appendRegisterName(unsigned registerNumber, bool is64Bit) { + if (registerNumber == 29) { + bufferPrintf(is64Bit ? "fp" : "wfp"); + return; + } + if (registerNumber == 30) { bufferPrintf(is64Bit ? "lr" : "wlr"); return; @@ -939,6 +950,63 @@ const char* A64DOpcodeLoadStoreRegisterOffset::format() return m_formatBuffer; } +const char* A64DOpcodeLoadStoreRegisterPair::opName() +{ + if (!vBit() && lBit() && size() == 0x1) + return "ldpsw"; + if (lBit()) + return "ldp"; + return "stp"; +} + +const char* A64DOpcodeLoadStoreRegisterPair::format() +{ + const char* thisOpName = opName(); + + if (size() == 0x3) + return A64DOpcode::format(); + + if ((offsetMode() < 0x1) || (offsetMode() > 0x3)) + return A64DOpcode::format(); + + if ((offsetMode() == 0x1) && !vBit() && !lBit()) + return A64DOpcode::format(); + + appendInstructionName(thisOpName); + unsigned offsetShift; + if (vBit()) { + appendFPRegisterName(rt(), size()); + appendSeparator(); + appendFPRegisterName(rt2(), size()); + offsetShift = size() + 2; + } else { + appendRegisterName(rt(), is64Bit()); + appendSeparator(); + appendRegisterName(rt2(), is64Bit()); + offsetShift = (size() >> 1) + 2; + } + + appendSeparator(); + appendCharacter('['); + appendSPOrRegisterName(rn()); + + int offset = immediate7() << offsetShift; + + if (offsetMode() == 1) { + appendCharacter(']'); + appendSeparator(); + appendSignedImmediate(offset); + } else { + appendSeparator(); + appendSignedImmediate(offset); + appendCharacter(']'); + if (offsetMode() == 0x3) + appendCharacter('!'); + } + + return m_formatBuffer; +} + const char* A64DOpcodeLoadStoreUnsignedImmediate::format() { const char* thisOpName = opName(); @@ -1130,3 +1198,5 @@ const char* A64DOpcodeUnconditionalBranchRegister::format() } } } // namespace JSC::ARM64Disassembler + +#endif // USE(ARM64_DISASSEMBLER) diff --git a/Source/JavaScriptCore/disassembler/ARM64/A64DOpcode.h b/Source/JavaScriptCore/disassembler/ARM64/A64DOpcode.h index ed18d30df..5bb7db9f1 100644 --- a/Source/JavaScriptCore/disassembler/ARM64/A64DOpcode.h +++ b/Source/JavaScriptCore/disassembler/ARM64/A64DOpcode.h @@ -172,12 +172,12 @@ protected: void appendUnsignedImmediate64(uint64_t immediate) { - bufferPrintf("#0x%llx", immediate); + bufferPrintf("#0x%" PRIx64, immediate); } void appendPCRelativeOffset(uint32_t* pc, int32_t immediate) { - bufferPrintf("0x%llx", reinterpret_cast(pc + immediate)); + bufferPrintf("0x%" PRIx64, reinterpret_cast(pc + immediate)); } void appendShiftAmount(unsigned amount) @@ -565,6 +565,22 @@ public: int sBit() { return (m_opcode >> 12) & 0x1; } }; +class A64DOpcodeLoadStoreRegisterPair : public A64DOpcodeLoadStore { +public: + static const uint32_t mask = 0x3a000000; + static const uint32_t pattern = 0x28000000; + + DEFINE_STATIC_FORMAT(A64DOpcodeLoadStoreRegisterPair, thisObj); + + const char* format(); + const char* opName(); + + unsigned rt2() { return (m_opcode >> 10) & 0x1f; } + int immediate7() { return (static_cast((m_opcode >> 15) & 0x7f) << 25) >> 25; } + unsigned offsetMode() { return (m_opcode >> 23) & 0x7; } + int lBit() { return (m_opcode >> 22) & 0x1; } +}; + class A64DOpcodeLoadStoreUnsignedImmediate : public A64DOpcodeLoadStore { public: static const uint32_t mask = 0x3b000000; diff --git a/Source/JavaScriptCore/disassembler/ARM64Disassembler.cpp b/Source/JavaScriptCore/disassembler/ARM64Disassembler.cpp index 713c1a74c..bb8fde4e4 100644 --- a/Source/JavaScriptCore/disassembler/ARM64Disassembler.cpp +++ b/Source/JavaScriptCore/disassembler/ARM64Disassembler.cpp @@ -1,5 +1,5 @@ /* - * Copyright (C) 2012 Apple Inc. All rights reserved. + * Copyright (C) 2012, 2014 Apple Inc. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -23,6 +23,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +#define __STDC_FORMAT_MACROS #include "config.h" #include "Disassembler.h" @@ -33,7 +34,7 @@ namespace JSC { -bool tryToDisassemble(const MacroAssemblerCodePtr& codePtr, size_t size, const char* prefix, PrintStream& out, InstructionSubsetHint) +bool tryToDisassemble(const MacroAssemblerCodePtr& codePtr, size_t size, const char* prefix, PrintStream& out) { A64DOpcode arm64Opcode; diff --git a/Source/JavaScriptCore/disassembler/ARMv7/ARMv7DOpcode.cpp b/Source/JavaScriptCore/disassembler/ARMv7/ARMv7DOpcode.cpp new file mode 100644 index 000000000..3175cccbd --- /dev/null +++ b/Source/JavaScriptCore/disassembler/ARMv7/ARMv7DOpcode.cpp @@ -0,0 +1,1733 @@ +/* + * Copyright (C) 2013 Apple Inc. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY APPLE INC. ``AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL APPLE INC. OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY + * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "config.h" + +#if USE(ARMV7_DISASSEMBLER) + +#include "ARMv7DOpcode.h" + +#include +#include +#include +#include + +namespace JSC { namespace ARMv7Disassembler { + +ARMv7D16BitOpcode::OpcodeGroup* ARMv7D16BitOpcode::opcodeTable[32]; +ARMv7D32BitOpcode::OpcodeGroup* ARMv7D32BitOpcode::opcodeTable[16]; + +const char* const ARMv7DOpcode::s_conditionNames[16] = { + "eq", "ne", "hs", "lo", "mi", "pl", "vs", "vc", + "hi", "ls", "ge", "lt", "gt", "le", "al", "al" +}; + +const char* const ARMv7DOpcode::s_optionName[8] = { + "uxtb", "uxth", "uxtw", "uxtx", "sxtb", "sxth", "sxtw", "sxtx" +}; + +const char* const ARMv7DOpcode::s_shiftNames[4] = { + "lsl", "lsr", "asr", "ror" +}; + +const char* const ARMv7DOpcode::s_specialRegisterNames[3] = { "sp", "lr", "pc" }; + +template +struct OpcodeGroupInitializer { + unsigned m_opcodeGroupNumber; + InstructionType m_mask; + InstructionType m_pattern; + const char* (*m_format)(OpcodeType*); +}; + +#define OPCODE_GROUP_ENTRY(groupIndex, groupClass) \ +{ groupIndex, groupClass::s_mask, groupClass::s_pattern, groupClass::format } + +typedef OpcodeGroupInitializer Opcode16GroupInitializer; +typedef OpcodeGroupInitializer Opcode32GroupInitializer; + +static Opcode16GroupInitializer opcode16BitGroupList[] = { + OPCODE_GROUP_ENTRY(0x0, ARMv7DOpcodeLogicalImmediateT1), + OPCODE_GROUP_ENTRY(0x1, ARMv7DOpcodeLogicalImmediateT1), + OPCODE_GROUP_ENTRY(0x2, ARMv7DOpcodeLogicalImmediateT1), + OPCODE_GROUP_ENTRY(0x3, ARMv7DOpcodeAddSubtractT1), + OPCODE_GROUP_ENTRY(0x3, ARMv7DOpcodeAddSubtractImmediate3), + OPCODE_GROUP_ENTRY(0x4, ARMv7DOpcodeMoveImmediateT1), + OPCODE_GROUP_ENTRY(0x5, ARMv7DOpcodeCompareImmediateT1), + OPCODE_GROUP_ENTRY(0x6, ARMv7DOpcodeAddSubtractImmediate8), + OPCODE_GROUP_ENTRY(0x7, ARMv7DOpcodeAddSubtractImmediate8), + OPCODE_GROUP_ENTRY(0x8, ARMv7DOpcodeDataProcessingRegisterT1), + OPCODE_GROUP_ENTRY(0x8, ARMv7DOpcodeAddRegisterT2), + OPCODE_GROUP_ENTRY(0x8, ARMv7DOpcodeCompareRegisterT2), + OPCODE_GROUP_ENTRY(0x8, ARMv7DOpcodeCompareRegisterT1), + OPCODE_GROUP_ENTRY(0x8, ARMv7DOpcodeMoveRegisterT1), + OPCODE_GROUP_ENTRY(0x8, ARMv7DOpcodeBranchExchangeT1), + OPCODE_GROUP_ENTRY(0x9, ARMv7DOpcodeLoadFromLiteralPool), + OPCODE_GROUP_ENTRY(0xa, ARMv7DOpcodeLoadStoreRegisterOffsetT1), + OPCODE_GROUP_ENTRY(0xb, ARMv7DOpcodeLoadStoreRegisterOffsetT1), + OPCODE_GROUP_ENTRY(0xc, ARMv7DOpcodeLoadStoreRegisterImmediateWordAndByte), + OPCODE_GROUP_ENTRY(0xd, ARMv7DOpcodeLoadStoreRegisterImmediateWordAndByte), + OPCODE_GROUP_ENTRY(0xe, ARMv7DOpcodeLoadStoreRegisterImmediateWordAndByte), + OPCODE_GROUP_ENTRY(0xf, ARMv7DOpcodeLoadStoreRegisterImmediateWordAndByte), + OPCODE_GROUP_ENTRY(0x10, ARMv7DOpcodeStoreRegisterImmediateHalfWord), + OPCODE_GROUP_ENTRY(0x11, ARMv7DOpcodeLoadRegisterImmediateHalfWord), + OPCODE_GROUP_ENTRY(0x12, ARMv7DOpcodeLoadStoreRegisterSPRelative), + OPCODE_GROUP_ENTRY(0x13, ARMv7DOpcodeLoadStoreRegisterSPRelative), + OPCODE_GROUP_ENTRY(0x14, ARMv7DOpcodeGeneratePCRelativeAddress), + OPCODE_GROUP_ENTRY(0x15, ARMv7DOpcodeAddSPPlusImmediate), + OPCODE_GROUP_ENTRY(0x16, ARMv7DOpcodeMiscCompareAndBranch), + OPCODE_GROUP_ENTRY(0x16, ARMv7DOpcodeMiscByteHalfwordOps), + OPCODE_GROUP_ENTRY(0x16, ARMv7DOpcodeMiscPushPop), + OPCODE_GROUP_ENTRY(0x16, ARMv7DOpcodeMiscAddSubSP), + OPCODE_GROUP_ENTRY(0x17, ARMv7DOpcodeMiscHint16), // Needs to be before IfThenT1 + OPCODE_GROUP_ENTRY(0x17, ARMv7DOpcodeMiscIfThenT1), + OPCODE_GROUP_ENTRY(0x17, ARMv7DOpcodeMiscByteHalfwordOps), + OPCODE_GROUP_ENTRY(0x17, ARMv7DOpcodeMiscCompareAndBranch), + OPCODE_GROUP_ENTRY(0x17, ARMv7DOpcodeMiscPushPop), + OPCODE_GROUP_ENTRY(0x17, ARMv7DOpcodeMiscBreakpointT1), + OPCODE_GROUP_ENTRY(0x1a, ARMv7DOpcodeBranchConditionalT1), + OPCODE_GROUP_ENTRY(0x1b, ARMv7DOpcodeBranchConditionalT1), + OPCODE_GROUP_ENTRY(0x1c, ARMv7DOpcodeBranchT2) +}; + +static Opcode32GroupInitializer opcode32BitGroupList[] = { + OPCODE_GROUP_ENTRY(0x4, ARMv7DOpcodeDataPopMultiple), + OPCODE_GROUP_ENTRY(0x4, ARMv7DOpcodeDataPushMultiple), + OPCODE_GROUP_ENTRY(0x5, ARMv7DOpcodeDataProcessingShiftedReg), + OPCODE_GROUP_ENTRY(0x6, ARMv7DOpcodeVLDR), + OPCODE_GROUP_ENTRY(0x6, ARMv7DOpcodeVMOVSinglePrecision), + OPCODE_GROUP_ENTRY(0x6, ARMv7DOpcodeVMOVDoublePrecision), + OPCODE_GROUP_ENTRY(0x7, ARMv7DOpcodeFPTransfer), + OPCODE_GROUP_ENTRY(0x7, ARMv7DOpcodeVMSR), + OPCODE_GROUP_ENTRY(0x7, ARMv7DOpcodeVCMP), + OPCODE_GROUP_ENTRY(0x7, ARMv7DOpcodeVCVTBetweenFPAndInt), + OPCODE_GROUP_ENTRY(0x8, ARMv7DOpcodeDataProcessingModifiedImmediate), + OPCODE_GROUP_ENTRY(0x8, ARMv7DOpcodeConditionalBranchT3), + OPCODE_GROUP_ENTRY(0x8, ARMv7DOpcodeBranchOrBranchLink), + OPCODE_GROUP_ENTRY(0x9, ARMv7DOpcodeUnmodifiedImmediate), + OPCODE_GROUP_ENTRY(0x9, ARMv7DOpcodeHint32), + OPCODE_GROUP_ENTRY(0x9, ARMv7DOpcodeConditionalBranchT3), + OPCODE_GROUP_ENTRY(0x9, ARMv7DOpcodeBranchOrBranchLink), + OPCODE_GROUP_ENTRY(0xa, ARMv7DOpcodeDataProcessingModifiedImmediate), + OPCODE_GROUP_ENTRY(0xa, ARMv7DOpcodeConditionalBranchT3), + OPCODE_GROUP_ENTRY(0xa, ARMv7DOpcodeBranchOrBranchLink), + OPCODE_GROUP_ENTRY(0xb, ARMv7DOpcodeUnmodifiedImmediate), + OPCODE_GROUP_ENTRY(0xb, ARMv7DOpcodeConditionalBranchT3), + OPCODE_GROUP_ENTRY(0xb, ARMv7DOpcodeBranchOrBranchLink), + OPCODE_GROUP_ENTRY(0xc, ARMv7DOpcodeLoadRegister), + OPCODE_GROUP_ENTRY(0xc, ARMv7DOpcodeDataPushPopSingle), // Should be before StoreSingle* + OPCODE_GROUP_ENTRY(0xc, ARMv7DOpcodeDataPopMultiple), + OPCODE_GROUP_ENTRY(0xc, ARMv7DOpcodeDataPushMultiple), + OPCODE_GROUP_ENTRY(0xc, ARMv7DOpcodeStoreSingleRegister), + OPCODE_GROUP_ENTRY(0xc, ARMv7DOpcodeStoreSingleImmediate12), + OPCODE_GROUP_ENTRY(0xc, ARMv7DOpcodeStoreSingleImmediate8), + OPCODE_GROUP_ENTRY(0xc, ARMv7DOpcodeLoadSignedImmediate), + OPCODE_GROUP_ENTRY(0xc, ARMv7DOpcodeLoadUnsignedImmediate), + OPCODE_GROUP_ENTRY(0xd, ARMv7DOpcodeLongMultipleDivide), + OPCODE_GROUP_ENTRY(0xd, ARMv7DOpcodeDataProcessingRegShift), + OPCODE_GROUP_ENTRY(0xd, ARMv7DOpcodeDataProcessingRegExtend), + OPCODE_GROUP_ENTRY(0xd, ARMv7DOpcodeDataProcessingRegParallel), + OPCODE_GROUP_ENTRY(0xd, ARMv7DOpcodeDataProcessingRegMisc), + OPCODE_GROUP_ENTRY(0xe, ARMv7DOpcodeVLDR), + OPCODE_GROUP_ENTRY(0xf, ARMv7DOpcodeVCMP), + OPCODE_GROUP_ENTRY(0xf, ARMv7DOpcodeVCVTBetweenFPAndInt), +}; + +bool ARMv7DOpcode::s_initialized = false; + +void ARMv7DOpcode::init() +{ + if (s_initialized) + return; + + ARMv7D16BitOpcode::init(); + ARMv7D32BitOpcode::init(); + + s_initialized = true; +} + +void ARMv7DOpcode::startITBlock(unsigned blocksize, unsigned firstCondition) +{ + ASSERT(blocksize > 0 && blocksize <= MaxITBlockSize); + m_ITBlocksize = blocksize; + m_ITConditionIndex = m_ITBlocksize + 1; + m_currentITCondition = 0; + m_ifThenConditions[0] = firstCondition; +} + +void ARMv7DOpcode::saveITConditionAt(unsigned blockPosition, unsigned condition) +{ + if (blockPosition < m_ITBlocksize) + m_ifThenConditions[blockPosition] = static_cast(condition); +} + +void ARMv7DOpcode::fetchOpcode(uint16_t*& newPC) +{ + m_bufferOffset = 0; + m_formatBuffer[0] = '\0'; + m_currentPC = newPC; + + m_opcode = *newPC++; + + if (is32BitInstruction()) { + m_opcode <<= 16; + m_opcode |= *newPC++; + } + + if (m_ITConditionIndex < m_ITBlocksize) + m_currentITCondition = m_ifThenConditions[m_ITConditionIndex]; + else + m_currentITCondition = CondNone; +} + +const char* ARMv7DOpcode::disassemble(uint16_t*& currentPC) +{ + const char* result; + fetchOpcode(currentPC); + + if (is32BitInstruction()) + result = reinterpret_cast(this)->doDisassemble(); + else + result = reinterpret_cast(this)->doDisassemble(); + + if (startingITBlock()) + m_ITConditionIndex = 0; + else if (inITBlock() && (++m_ITConditionIndex >= m_ITBlocksize)) + endITBlock(); + + return result; +} + +void ARMv7DOpcode::bufferPrintf(const char* format, ...) +{ + if (m_bufferOffset >= bufferSize) + return; + + va_list argList; + va_start(argList, format); + + m_bufferOffset += vsnprintf(m_formatBuffer + m_bufferOffset, bufferSize - m_bufferOffset, format, argList); + + va_end(argList); +} + +void ARMv7DOpcode::appendInstructionName(const char* instructionName, bool addS) +{ + if (!inITBlock() && !addS) { + appendInstructionNameNoITBlock(instructionName); + + return; + } + + const char sevenSpaces[8] = " "; + + unsigned length = strlen(instructionName); + + bufferPrintf(" %s", instructionName); + if (inITBlock()) { + const char* condition = conditionName(m_currentITCondition); + length += strlen(condition); + appendString(condition); + } else if (addS) { + length++; + appendCharacter('s'); + } + + if (length >= 7) + length = 6; + + appendString(sevenSpaces + length); +} + +void ARMv7DOpcode::appendRegisterName(unsigned registerNumber) +{ + registerNumber &= 0xf; + + if (registerNumber > 12) { + appendString(s_specialRegisterNames[registerNumber - 13]); + return; + } + + bufferPrintf("r%u", registerNumber); +} + +void ARMv7DOpcode::appendRegisterList(unsigned registers) +{ + unsigned numberPrinted = 0; + + appendCharacter('{'); + + for (unsigned i = 0; i < 16; i++) { + if (registers & (1 << i)) { + if (numberPrinted++) + appendSeparator(); + appendRegisterName(i); + } + } + + appendCharacter('}'); +} + +void ARMv7DOpcode::appendFPRegisterName(char registerPrefix, unsigned registerNumber) +{ + bufferPrintf("%c%u", registerPrefix, registerNumber); +} + +// 16 Bit Instructions + +void ARMv7D16BitOpcode::init() +{ + OpcodeGroup* lastGroups[OpcodeGroup::opcodeTableSize]; + + for (unsigned i = 0; i < OpcodeGroup::opcodeTableSize; i++) { + opcodeTable[i] = 0; + lastGroups[i] = 0; + } + + for (unsigned i = 0; i < sizeof(opcode16BitGroupList) / sizeof(Opcode16GroupInitializer); i++) { + OpcodeGroup* newOpcodeGroup = new OpcodeGroup(opcode16BitGroupList[i].m_mask, opcode16BitGroupList[i].m_pattern, opcode16BitGroupList[i].m_format); + uint16_t opcodeGroupNumber = opcode16BitGroupList[i].m_opcodeGroupNumber; + + if (!opcodeTable[opcodeGroupNumber]) + opcodeTable[opcodeGroupNumber] = newOpcodeGroup; + else + lastGroups[opcodeGroupNumber]->setNext(newOpcodeGroup); + lastGroups[opcodeGroupNumber] = newOpcodeGroup; + } +} + +const char* ARMv7D16BitOpcode::doDisassemble() +{ + OpcodeGroup* opGroup = opcodeTable[opcodeGroupNumber(m_opcode)]; + + while (opGroup) { + if (opGroup->matches(static_cast(m_opcode))) + return opGroup->format(this); + opGroup = opGroup->next(); + } + + return defaultFormat(); +} + +const char* ARMv7D16BitOpcode::defaultFormat() +{ + bufferPrintf(" .word %04x", m_opcode); + return m_formatBuffer; +} + +const char* ARMv7DOpcodeAddRegisterT2::format() +{ + appendInstructionName("add"); + appendRegisterName(rdn()); + appendSeparator(); + appendRegisterName(rm()); + + return m_formatBuffer; +} + +const char* ARMv7DOpcodeAddSPPlusImmediate::format() +{ + appendInstructionName("add"); + appendRegisterName(rd()); + appendSeparator(); + appendRegisterName(RegSP); + appendSeparator(); + appendUnsignedImmediate(immediate8()); + + return m_formatBuffer; +} + +const char* const ARMv7DOpcodeAddSubtract::s_opNames[2] = { "add", "sub" }; + +const char* ARMv7DOpcodeAddSubtractT1::format() +{ + appendInstructionName(opName(), !inITBlock()); + appendRegisterName(rd()); + appendSeparator(); + appendRegisterName(rn()); + appendSeparator(); + appendRegisterName(rm()); + + return m_formatBuffer; +} + +const char* ARMv7DOpcodeAddSubtractImmediate3::format() +{ + appendInstructionName(opName(), !inITBlock()); + appendRegisterName(rd()); + appendSeparator(); + appendRegisterName(rn()); + appendSeparator(); + appendUnsignedImmediate(immediate3()); + + return m_formatBuffer; +} + +const char* ARMv7DOpcodeAddSubtractImmediate8::format() +{ + appendInstructionName(opName(), !inITBlock()); + appendRegisterName(rdn()); + appendSeparator(); + appendUnsignedImmediate(immediate8()); + + return m_formatBuffer; +} + +const char* ARMv7DOpcodeBranchConditionalT1::format() +{ + if (condition() == 0xe) + return defaultFormat(); + + if (condition() == 0xf) { + appendInstructionName("svc"); + appendUnsignedImmediate(offset()); + + return m_formatBuffer; + } + + bufferPrintf(" b%-6.6s", conditionName(condition())); + appendPCRelativeOffset(static_cast(offset()) + 2); + + return m_formatBuffer; +} + +const char* ARMv7DOpcodeBranchExchangeT1::format() +{ + appendInstructionName(opName()); + appendRegisterName(rm()); + + return m_formatBuffer; +} + +const char* ARMv7DOpcodeBranchT2::format() +{ + appendInstructionName("b"); + appendPCRelativeOffset(static_cast(immediate11()) + 2); + + return m_formatBuffer; +} + +const char* ARMv7DOpcodeCompareImmediateT1::format() +{ + appendInstructionName("cmp"); + appendRegisterName(rn()); + appendSeparator(); + appendUnsignedImmediate(immediate8()); + + return m_formatBuffer; +} + +const char* ARMv7DOpcodeCompareRegisterT1::format() +{ + appendInstructionName("cmp"); + appendRegisterName(rn()); + appendSeparator(); + appendRegisterName(rm()); + + return m_formatBuffer; +} + +const char* ARMv7DOpcodeCompareRegisterT2::format() +{ + appendInstructionName("compare"); + appendRegisterName(rn()); + appendSeparator(); + appendRegisterName(rm()); + + return m_formatBuffer; +} + +const char* const ARMv7DOpcodeDataProcessingRegisterT1::s_opNames[16] = { + "and", "eor", "lsl", "lsr", "asr", "adc", "sbc", "ror", "tst", "rsb", "cmp", "cmn", "orr", "mul", "bic", "mvn" +}; + +const char* ARMv7DOpcodeDataProcessingRegisterT1::format() +{ + appendInstructionName(opName(), inITBlock() && (!(op() == 0x8) || (op() == 0xa) || (op() == 0xb))); + appendRegisterName(rdn()); + appendSeparator(); + appendRegisterName(rm()); + if (op() == 0x9) // rsb T1 + appendString(", #0"); + else if (op() == 0xd) { // mul T1 + appendSeparator(); + appendRegisterName(rdn()); + } + + return m_formatBuffer; +} + +const char* ARMv7DOpcodeGeneratePCRelativeAddress::format() +{ + appendInstructionName("adr"); + appendRegisterName(rd()); + appendSeparator(); + appendPCRelativeOffset(static_cast(immediate8())); + + return m_formatBuffer; +} + +const char* ARMv7DOpcodeLoadFromLiteralPool::format() +{ + appendInstructionName("ldr"); + appendRegisterName(rt()); + appendSeparator(); + appendPCRelativeOffset(static_cast(immediate8())); + + return m_formatBuffer; +} + +const char* const ARMv7DOpcodeLoadStoreRegisterImmediate::s_opNames[6] = { + "str", "ldr", "strb", "ldrb", "strh", "ldrh" +}; + +const char* ARMv7DOpcodeLoadStoreRegisterImmediate::format() +{ + const char* instructionName = opName(); + + if (!instructionName) + return defaultFormat(); + + appendInstructionName(opName()); + appendRegisterName(rt()); + appendSeparator(); + appendCharacter('['); + appendRegisterName(rn()); + if (immediate5()) { + appendSeparator(); + appendUnsignedImmediate(immediate5() << scale()); + } + appendCharacter(']'); + + return m_formatBuffer; +} + +unsigned ARMv7DOpcodeLoadStoreRegisterImmediate::scale() +{ + switch (op()) { + case 0: + case 1: + return 2; + case 2: + case 3: + return 0; + case 4: + case 5: + return 1; + default: + break; + } + ASSERT_NOT_REACHED(); + return 0; +} + +const char* const ARMv7DOpcodeLoadStoreRegisterOffsetT1::s_opNames[8] = { + "str", "strh", "strb", "ldrsb", "ldr", "ldrh", "ldrb", "ldrsh" +}; + +const char* ARMv7DOpcodeLoadStoreRegisterOffsetT1::format() +{ + appendInstructionName(opName()); + appendRegisterName(rt()); + appendSeparator(); + appendCharacter('['); + appendRegisterName(rn()); + appendSeparator(); + appendRegisterName(rm()); + appendCharacter(']'); + + return m_formatBuffer; +} + +const char* ARMv7DOpcodeLoadStoreRegisterSPRelative::format() +{ + appendInstructionName(opName()); + appendRegisterName(rt()); + appendSeparator(); + appendCharacter('['); + appendRegisterName(RegSP); + if (immediate8()) { + appendSeparator(); + appendUnsignedImmediate(immediate8() << 2); + } + appendCharacter(']'); + + return m_formatBuffer; +} + +const char* ARMv7DOpcodeLogicalImmediateT1::format() +{ + if (!op() && !immediate5()) { + // mov T2 + appendInstructionName("movs"); + appendRegisterName(rd()); + appendSeparator(); + appendRegisterName(rm()); + + return m_formatBuffer; + } + + appendInstructionName(opName(), !inITBlock()); + appendRegisterName(rd()); + appendSeparator(); + appendRegisterName(rm()); + appendSeparator(); + appendUnsignedImmediate((op() && !immediate5()) ? 32 : immediate5()); + + return m_formatBuffer; +} + +const char* ARMv7DOpcodeMiscAddSubSP::format() +{ + appendInstructionName(opName()); + appendRegisterName(RegSP); + appendSeparator(); + appendRegisterName(RegSP); + appendSeparator(); + appendUnsignedImmediate(immediate7()); + + return m_formatBuffer; +} + +const char* ARMv7DOpcodeMiscBreakpointT1::format() +{ + appendInstructionNameNoITBlock("bkpt"); + appendUnsignedImmediate(immediate8()); + + return m_formatBuffer; +} + +const char* const ARMv7DOpcodeMiscByteHalfwordOps::s_opNames[8] = { + "sxth", "sxb", "uxth", "uxtb", "rev", "rev16", "revsh" +}; + +const char* ARMv7DOpcodeMiscByteHalfwordOps::format() +{ + const char* instructionName = opName(); + + if (!instructionName) + return defaultFormat(); + + appendInstructionName(instructionName); + appendRegisterName(rd()); + appendSeparator(); + appendRegisterName(rm()); + + return m_formatBuffer; +} + +const char* ARMv7DOpcodeMiscCompareAndBranch::format() +{ + appendInstructionName(opName()); + appendPCRelativeOffset(immediate6() + 2); + + return m_formatBuffer; +} + +const char* const ARMv7DOpcodeMiscHint16::s_opNames[16] = { + "nop", "yield", "wfe", "wfi", "sev" +}; + +const char* ARMv7DOpcodeMiscHint16::format() +{ + if (opA() > 4) + return defaultFormat(); + + appendInstructionName(opName()); + + return m_formatBuffer; +} + +const char* ARMv7DOpcodeMiscIfThenT1::format() +{ + char opName[6]; + opName[0] = 'i'; + opName[1] = 't'; + + unsigned condition = firstCondition(); + unsigned maskBits = mask(); + unsigned blockLength = 0; + + for (unsigned i = 0; i < 4; ++i) { + if (maskBits & (1 << i)) { + blockLength = 4 - i; + break; + } + } + + startITBlock(blockLength, condition); + + for (unsigned i = 1; i < blockLength; ++i) { + unsigned currMaskBit = (maskBits >> (4-i)) & 0x1; + opName[i + 1] = (currMaskBit ^ (condition & 1)) ? 'e' : 't'; + saveITConditionAt(i, (condition & ~1) | currMaskBit); + } + opName[blockLength + 1] = '\0'; + + appendInstructionNameNoITBlock(opName); + appendString(conditionName(condition)); + + return m_formatBuffer; +} + +const char* ARMv7DOpcodeMiscPushPop::format() +{ + appendInstructionName(opName()); + appendRegisterList(registerMask()); + + return m_formatBuffer; +} + +const char* ARMv7DOpcodeMoveImmediateT1::format() +{ + appendInstructionName("mov", !inITBlock()); + appendRegisterName(rd()); + appendSeparator(); + appendUnsignedImmediate(immediate8()); + + return m_formatBuffer; +} + +const char* ARMv7DOpcodeMoveRegisterT1::format() +{ + appendInstructionName("mov"); + appendRegisterName(rd()); + appendSeparator(); + appendRegisterName(rm()); + + return m_formatBuffer; +} + +// 32 bit Intructions + +void ARMv7D32BitOpcode::init() +{ + OpcodeGroup* lastGroups[OpcodeGroup::opcodeTableSize]; + + for (unsigned i = 0; i < OpcodeGroup::opcodeTableSize; i++) { + opcodeTable[i] = 0; + lastGroups[i] = 0; + } + + for (unsigned i = 0; i < sizeof(opcode32BitGroupList) / sizeof(Opcode32GroupInitializer); i++) { + OpcodeGroup* newOpcodeGroup = new OpcodeGroup(opcode32BitGroupList[i].m_mask, opcode32BitGroupList[i].m_pattern, opcode32BitGroupList[i].m_format); + uint16_t opcodeGroupNumber = opcode32BitGroupList[i].m_opcodeGroupNumber; + + if (!opcodeTable[opcodeGroupNumber]) + opcodeTable[opcodeGroupNumber] = newOpcodeGroup; + else + lastGroups[opcodeGroupNumber]->setNext(newOpcodeGroup); + lastGroups[opcodeGroupNumber] = newOpcodeGroup; + } +} + +const char* ARMv7D32BitOpcode::doDisassemble() +{ + OpcodeGroup* opGroup = opcodeTable[opcodeGroupNumber(m_opcode)]; + + while (opGroup) { + if (opGroup->matches(m_opcode)) + return opGroup->format(this); + opGroup = opGroup->next(); + } + + return defaultFormat(); +} + +const char* ARMv7D32BitOpcode::defaultFormat() +{ + bufferPrintf(" .long %08x", m_opcode); + return m_formatBuffer; +} + +const char* ARMv7DOpcodeConditionalBranchT3::format() +{ + if (condition() < 0xe) + bufferPrintf(" b%-6.6s", conditionName(condition())); + else + appendInstructionName("b"); + appendPCRelativeOffset(offset() + 2); + + return m_formatBuffer; +} + +const char* ARMv7DOpcodeBranchOrBranchLink::format() +{ + appendInstructionName(isBL() ? "bl" : "b"); + appendPCRelativeOffset(offset() + 2); + + return m_formatBuffer; +} + +const char* const ARMv7DOpcodeDataProcessingLogicalAndRithmetic::s_opNames[16] = { + "and", "bic", "orr", "orn", "eor", 0, "pkh", 0, "add", 0, "adc", "sbc", 0, "sub", "rsb", 0 +}; + +void ARMv7DOpcodeDataProcessingModifiedImmediate::appendModifiedImmediate(unsigned immediate12) +{ + if (!(immediate12 & 0xc00)) { + unsigned immediate = 0; + unsigned lower8Bits = immediate12 & 0xff; + + switch ((immediate12 >> 8) & 3) { + case 0: + immediate = lower8Bits; + break; + case 1: + immediate = (lower8Bits << 16) | lower8Bits; + break; + case 2: + immediate = (lower8Bits << 24) | (lower8Bits << 8); + break; + case 3: + immediate = (lower8Bits << 24) | (lower8Bits << 16) | (lower8Bits << 8) | lower8Bits; + break; + } + appendUnsignedImmediate(immediate); + return; + } + + unsigned immediate8 = 0x80 | (immediate12 & 0x7f); + unsigned shiftAmount = 32 - ((immediate12 >> 7) & 0x1f); + + appendUnsignedImmediate(immediate8 << shiftAmount); +} + +const char* ARMv7DOpcodeDataProcessingModifiedImmediate::format() +{ + if ((op() == 0x5) || (op() == 0x6) || (op() == 0x7) || (op() == 0x9) || (op() == 0xc) || (op() == 0xf)) + return defaultFormat(); + + const char* instructionName = opName(); + + if (rn() == 15) { + if (op() == 2) { + // MOV T2 + instructionName = sBit() ? "movs" : "mov"; + appendInstructionName(instructionName); + appendRegisterName(rd()); + appendSeparator(); + appendModifiedImmediate(immediate12()); + + return m_formatBuffer; + } + + if (op() == 3) { + // MVN T1 + instructionName = sBit() ? "mvns" : "mvn"; + appendInstructionName(instructionName); + appendRegisterName(rd()); + appendSeparator(); + appendModifiedImmediate(immediate12()); + + return m_formatBuffer; + } + } + + if (rd() == 15) { + if (sBit()) { + bool testOrCmpInstruction = false; + + switch (op()) { + case 0x0: + instructionName = "tst"; + testOrCmpInstruction = true; + break; + case 0x4: + instructionName = "teq"; + testOrCmpInstruction = true; + break; + case 0x8: + instructionName = "cmn"; + testOrCmpInstruction = true; + break; + case 0xd: + instructionName = "cmp"; + testOrCmpInstruction = true; + break; + } + + if (testOrCmpInstruction) { + appendInstructionName(instructionName); + appendRegisterName(rn()); + appendSeparator(); + appendModifiedImmediate(immediate12()); + + return m_formatBuffer; + } + } + } + + appendInstructionName(instructionName); + appendRegisterName(rd()); + appendSeparator(); + appendRegisterName(rn()); + appendSeparator(); + appendModifiedImmediate(immediate12()); + + return m_formatBuffer; +} + +void ARMv7DOpcodeDataProcessingShiftedReg::appendImmShift(unsigned type, unsigned immediate) +{ + if (type || immediate) { + appendSeparator(); + + if (!immediate) { + switch (type) { + case 1: + case 2: + immediate = 32; + break; + case 3: + appendString("rrx"); + return; + } + } + + appendShiftType(type); + appendUnsignedImmediate(immediate); + } +} + +const char* ARMv7DOpcodeDataProcessingShiftedReg::format() +{ + if ((op() == 0x5) || (op() == 0x7) || (op() == 0x9) || (op() == 0xc) || (op() == 0xf)) + return defaultFormat(); + + if (op() == 6) { + // pkhbt or pkhtb + if (sBit() || tBit()) + return defaultFormat(); + + if (tbBit()) + appendInstructionName("pkhtb"); + else + appendInstructionName("pkhbt"); + appendRegisterName(rd()); + appendSeparator(); + appendRegisterName(rn()); + appendSeparator(); + appendRegisterName(rm()); + appendImmShift(tbBit() << 1, immediate5()); + + return m_formatBuffer; + } + + const char* instructionName = opName(); + + if (rn() == 15) { + if (op() == 2) { + if (!type() && !immediate5()) { + // MOV T3 + instructionName = sBit() ? "movs" : "mov"; + appendInstructionName(instructionName); + appendRegisterName(rd()); + appendSeparator(); + appendRegisterName(rm()); + + return m_formatBuffer; + } + + if (type() == 3 && !immediate5()) { + // RRX T1 + instructionName = sBit() ? "rrx" : "rrx"; + appendInstructionName(instructionName); + appendRegisterName(rd()); + appendSeparator(); + appendRegisterName(rm()); + + return m_formatBuffer; + } + + // Logical + if (sBit()) + bufferPrintf("%ss ", shiftName(type())); + else + appendInstructionName(shiftName(type())); + appendRegisterName(rd()); + appendSeparator(); + appendRegisterName(rm()); + appendSeparator(); + appendUnsignedImmediate(immediate5()); + + return m_formatBuffer; + } + + if (op() == 3) { + // MVN T2 + instructionName = sBit() ? "mvns" : "mvn"; + appendInstructionName(instructionName); + appendRegisterName(rd()); + appendSeparator(); + appendRegisterName(rm()); + appendImmShift(type(), immediate5()); + + return m_formatBuffer; + } + } + + if (rd() == 15) { + if (sBit()) { + bool testOrCmpInstruction = false; + + switch (op()) { + case 0x0: + instructionName = "tst"; + testOrCmpInstruction = true; + break; + case 0x4: + instructionName = "teq"; + testOrCmpInstruction = true; + break; + case 0x8: + instructionName = "cmn"; + testOrCmpInstruction = true; + break; + case 0xd: + instructionName = "cmp"; + testOrCmpInstruction = true; + break; + } + + if (testOrCmpInstruction) { + appendInstructionName(instructionName); + appendRegisterName(rn()); + appendSeparator(); + appendRegisterName(rm()); + appendImmShift(type(), immediate5()); + + return m_formatBuffer; + } + } + } + + appendInstructionName(instructionName); + appendRegisterName(rd()); + appendSeparator(); + appendRegisterName(rn()); + appendSeparator(); + appendRegisterName(rm()); + appendImmShift(type(), immediate5()); + + return m_formatBuffer; +} + +const char* ARMv7DOpcodeFPTransfer::format() +{ + appendInstructionName("vmov"); + + if (opL()) { + appendFPRegister(); + appendSeparator(); + } + + appendRegisterName(rt()); + + if (!opL()) { + appendSeparator(); + appendFPRegister(); + } + + return m_formatBuffer; +} + +void ARMv7DOpcodeFPTransfer::appendFPRegister() +{ + if (opC()) { + appendFPRegisterName('d', vd()); + bufferPrintf("[%u]", opH()); + } else + appendFPRegisterName('s', vn()); +} + +const char* ARMv7DOpcodeDataProcessingRegShift::format() +{ + appendInstructionName(opName()); + appendRegisterName(rd()); + appendSeparator(); + appendRegisterName(rn()); + appendSeparator(); + appendRegisterName(rm()); + + return m_formatBuffer; +} + +const char* const ARMv7DOpcodeDataProcessingRegExtend::s_opExtendNames[8] = { + "sxth", "uxth", "sxtb16", "uxtb16", "sxtb", "uxtb" +}; + +const char* const ARMv7DOpcodeDataProcessingRegExtend::s_opExtendAndAddNames[8] = { + "sxtah", "uxtah", "sxtab16", "uxtab16", "sxtab", "uxtab" +}; + +const char* ARMv7DOpcodeDataProcessingRegExtend::format() +{ + const char* instructionName; + + if (rn() == 0xf) + instructionName = opExtendName(); + else + instructionName = opExtendAndAddName(); + + if (!instructionName) + return defaultFormat(); + + appendInstructionName(instructionName); + appendRegisterName(rd()); + appendSeparator(); + appendRegisterName(rn()); + appendSeparator(); + appendRegisterName(rm()); + + if (rotate()) { + appendSeparator(); + appendString("ror "); + appendUnsignedImmediate(rotate() * 8); + } + + return m_formatBuffer; +} + +const char* const ARMv7DOpcodeDataProcessingRegParallel::s_opNames[16] = { + "sadd8", "sadd16", "sasx", 0, "ssub8", "ssub16", "ssax", 0, + "qadd8", "qadd16", "qasx", 0, "qsub8", "qsub16", "qsax", 0 +}; + +const char* ARMv7DOpcodeDataProcessingRegParallel::format() +{ + const char* instructionName; + + instructionName = opName(); + + if (!instructionName) + return defaultFormat(); + + appendInstructionName(instructionName); + appendRegisterName(rd()); + appendSeparator(); + appendRegisterName(rn()); + appendSeparator(); + appendRegisterName(rm()); + + return m_formatBuffer; +} + +const char* const ARMv7DOpcodeDataProcessingRegMisc::s_opNames[16] = { + "qadd", "qdadd", "qsub", "qdsub", "rev", "rev16", "rbit", "revsh", + "sel", 0, 0, 0, "clz" +}; + +const char* ARMv7DOpcodeDataProcessingRegMisc::format() +{ + const char* instructionName; + + instructionName = opName(); + + if (!instructionName) + return defaultFormat(); + + if ((op1() & 0x1) && (rn() != rm())) + return defaultFormat(); + + appendInstructionName(instructionName); + appendRegisterName(rd()); + appendSeparator(); + + if (op1() == 0x2) { // sel + appendRegisterName(rn()); + appendSeparator(); + appendRegisterName(rm()); + + return m_formatBuffer; + } + + appendRegisterName(rm()); + + if (!(op1() & 0x1)) { + appendSeparator(); + appendRegisterName(rn()); + } + + return m_formatBuffer; +} + +const char* const ARMv7DOpcodeHint32::s_opNames[8] = { + "nop", "yield", "wfe", "wfi", "sev" +}; + +const char* ARMv7DOpcodeHint32::format() +{ + if (isDebugHint()) { + appendInstructionName("debug"); + appendUnsignedImmediate(debugOption()); + + return m_formatBuffer; + } + + if (op() > 0x4) + return defaultFormat(); + + appendInstructionName(opName()); + + return m_formatBuffer; +} + +const char* const ARMv7DOpcodeDataLoad::s_opNames[8] = { + "ldrb", "ldrh", "ldr", 0, "ldrsb", "ldrsh" +}; + +const char* ARMv7DOpcodeLoadRegister::format() +{ + appendInstructionName(opName()); + appendRegisterName(rt()); + appendSeparator(); + appendCharacter('['); + appendRegisterName(rn()); + appendSeparator(); + appendRegisterName(rm()); + if (immediate2()) { + appendSeparator(); + appendUnsignedImmediate(immediate2()); + } + appendCharacter(']'); + + return m_formatBuffer; +} + +const char* ARMv7DOpcodeLoadSignedImmediate::format() +{ + appendInstructionName(opName()); + appendRegisterName(rt()); + appendSeparator(); + appendCharacter('['); + appendRegisterName(rn()); + if (pBit()) { + if (wBit() || immediate8()) { + appendSeparator(); + if (uBit()) + appendUnsignedImmediate(immediate8()); + else + appendSignedImmediate(0 - static_cast(immediate8())); + } + appendCharacter(']'); + if (wBit()) + appendCharacter('!'); + } else { + appendCharacter(']'); + appendSeparator(); + if (uBit()) + appendUnsignedImmediate(immediate8()); + else + appendSignedImmediate(0 - static_cast(immediate8())); + } + + return m_formatBuffer; +} + +const char* ARMv7DOpcodeLoadUnsignedImmediate::format() +{ + appendInstructionName(opName()); + appendRegisterName(rt()); + appendSeparator(); + appendCharacter('['); + appendRegisterName(rn()); + if (immediate12()) { + appendSeparator(); + appendUnsignedImmediate(immediate12()); + } + appendCharacter(']'); + + return m_formatBuffer; +} + +const char* const ARMv7DOpcodeLongMultipleDivide::s_opNames[8] = { + "smull", "sdiv", "umull", "udiv", "smlal", "smlsld", "umlal", 0 +}; + +const char* const ARMv7DOpcodeLongMultipleDivide::s_smlalOpNames[4] = { + "smlalbb", "smlalbt", "smlaltb", "smlaltt" +}; + +const char* const ARMv7DOpcodeLongMultipleDivide::s_smlaldOpNames[2] = { + "smlald", "smlaldx" +}; + +const char* const ARMv7DOpcodeLongMultipleDivide::s_smlsldOpNames[2] = { + "smlsld", "smlsldx" +}; + +const char* ARMv7DOpcodeLongMultipleDivide::format() +{ + const char* instructionName = opName(); + + switch (op1()) { + case 0x0: + case 0x2: + if (op2()) + return defaultFormat(); + break; + case 0x1: + case 0x3: + if (op2() != 0xf) + return defaultFormat(); + break; + case 0x4: + if ((op2() & 0xc) == 0x8) + instructionName = smlalOpName(); + else if ((op2() & 0xe) == 0xc) + instructionName = smlaldOpName(); + else if (op2()) + return defaultFormat(); + break; + case 0x5: + if ((op2() & 0xe) == 0xc) + instructionName = smlaldOpName(); + else + return defaultFormat(); + break; + case 0x6: + if (op2() == 0x5) + instructionName = "umaal"; + else if (op2()) + return defaultFormat(); + break; + case 0x7: + return defaultFormat(); + break; + } + + appendInstructionName(instructionName); + if ((op1() & 0x5) == 0x1) { // sdiv and udiv + if (rt() != 0xf) + return defaultFormat(); + } else { + appendRegisterName(rdLo()); + appendSeparator(); + } + appendRegisterName(rdHi()); + appendSeparator(); + appendRegisterName(rn()); + appendSeparator(); + appendRegisterName(rm()); + + return m_formatBuffer; +} + +const char* const ARMv7DOpcodeUnmodifiedImmediate::s_opNames[16] = { + "addw", 0, "movw", 0, 0, "subw", "movt", 0, + "ssat", "ssat16", "sbfx", "bfi", "usat" , "usat16", "ubfx", 0 +}; + +const char* ARMv7DOpcodeUnmodifiedImmediate::format() +{ + const char* instructionName = opName(); + + switch (op() >> 1) { + case 0x0: + case 0x5: + if (rn() == 0xf) + instructionName = "adr"; + break; + case 0x9: + if (immediate5()) + instructionName = "ssat"; + break; + case 0xb: + if (rn() == 0xf) + instructionName = "bfc"; + break; + case 0xd: + if (immediate5()) + instructionName = "usat"; + break; + } + + if (!instructionName) + return defaultFormat(); + + appendInstructionName(instructionName); + appendRegisterName(rd()); + appendSeparator(); + + if ((op() & 0x17) == 0x4) { // movw or movt + appendUnsignedImmediate(immediate16()); + + return m_formatBuffer; + } + + if (!op() || (op() == 0xa)) { // addw, subw and adr + if (rn() == 0xf) { + int32_t offset; + + if ((op() == 0xa) && (rn() == 0xf)) + offset = 0 - static_cast(immediate12()); + else + offset = static_cast(immediate12()); + + appendPCRelativeOffset(offset); + + return m_formatBuffer; + } + + appendRegisterName(rn()); + appendSeparator(); + appendUnsignedImmediate(immediate12()); + + return m_formatBuffer; + } + + if (((op() & 0x15) == 0x10) || (((op() & 0x17) == 0x12) && immediate5())) { // ssat, usat, ssat16 & usat16 + appendSeparator(); + appendUnsignedImmediate(bitNumOrSatImmediate() + 1); + appendSeparator(); + appendRegisterName(rn()); + if (shBit() || immediate5()) { + appendSeparator(); + appendShiftType(shBit() << 1); + appendUnsignedImmediate(immediate5()); + } + + return m_formatBuffer; + } + + if (op() == 0x16) { // bfi or bfc + int width = static_cast(bitNumOrSatImmediate()) - static_cast(immediate5()) + 1; + + if (width < 0) + return defaultFormat(); + + if (rn() != 0xf) { + appendSeparator(); + appendRegisterName(rn()); + } + appendSeparator(); + appendUnsignedImmediate(immediate5()); + appendSeparator(); + appendSignedImmediate(width); + + return m_formatBuffer; + } + + // Must be sbfx or ubfx + appendSeparator(); + appendRegisterName(rn()); + appendSeparator(); + appendUnsignedImmediate(immediate5()); + appendSeparator(); + appendUnsignedImmediate(bitNumOrSatImmediate() + 1); + + return m_formatBuffer; +} + +const char* const ARMv7DOpcodeDataStoreSingle::s_opNames[4] = { + "strb", "strh", "str", 0 +}; + +const char* ARMv7DOpcodeDataPushPopSingle::format() +{ + appendInstructionName(opName()); + appendRegisterName(rt()); + + return m_formatBuffer; +} + +void ARMv7DOpcodeDataPushPopMultiple::appendRegisterList() +{ + unsigned registers = registerList(); + + appendCharacter('{'); + bool needSeparator = false; + + for (unsigned i = 0; i < 16; i++) { + if (registers & (1 << i)) { + if (needSeparator) + appendSeparator(); + appendRegisterName(i); + needSeparator = true; + } + } + appendCharacter('}'); +} + +const char* ARMv7DOpcodeDataPopMultiple::format() +{ + if (condition() != 0xe) + bufferPrintf(" pop%-4.4s", conditionName(condition())); + else + appendInstructionName("pop"); + appendRegisterList(); + + return m_formatBuffer; +} + +const char* ARMv7DOpcodeDataPushMultiple::format() +{ + if (condition() != 0xe) + bufferPrintf(" push%-3.3s", conditionName(condition())); + else + appendInstructionName("push"); + appendRegisterList(); + + return m_formatBuffer; +} + +const char* ARMv7DOpcodeStoreSingleImmediate12::format() +{ + appendInstructionName(opName()); + appendRegisterName(rt()); + appendSeparator(); + appendCharacter('['); + appendRegisterName(rn()); + if (immediate12()) { + appendSeparator(); + appendUnsignedImmediate(immediate12()); + } + appendCharacter(']'); + + return m_formatBuffer; +} + +const char* ARMv7DOpcodeStoreSingleImmediate8::format() +{ + if (pBit() && uBit() && !wBit()) // Really undecoded strt + return defaultFormat(); + + if ((rn() == 0xf) || (!pBit() && !wBit())) + return defaultFormat(); + + appendInstructionName(opName()); + appendRegisterName(rt()); + appendSeparator(); + appendCharacter('['); + appendRegisterName(rn()); + + if (!pBit()) { + appendCharacter(']'); + appendSeparator(); + appendSignedImmediate(uBit() ? static_cast(immediate8()) : (0 - static_cast(immediate8()))); + + return m_formatBuffer; + } + + if (immediate8()) { + appendSeparator(); + appendSignedImmediate(uBit() ? static_cast(immediate8()) : (0 - static_cast(immediate8()))); + } + appendCharacter(']'); + + if (wBit()) + appendCharacter('!'); + + return m_formatBuffer; +} + +const char* ARMv7DOpcodeStoreSingleRegister::format() +{ + appendInstructionName(opName()); + appendRegisterName(rt()); + appendSeparator(); + appendCharacter('['); + appendRegisterName(rn()); + appendSeparator(); + appendRegisterName(rm()); + if (immediate2()) { + appendSeparator(); + appendString("lsl "); + appendUnsignedImmediate(immediate2()); + } + appendCharacter(']'); + + return m_formatBuffer; +} + +const char* ARMv7DOpcodeVCMP::format() +{ + bufferPrintf(" vcmp"); + + if (eBit()) + appendCharacter('e'); // Raise exception on qNaN + + if (condition() != 0xe) + appendString(conditionName(condition())); + + appendCharacter('.'); + appendString(szBit() ? "f64" : "f32"); + appendCharacter(' '); + if (szBit()) { + appendFPRegisterName('d', (dBit() << 4) | vd()); + appendSeparator(); + appendFPRegisterName('d', (mBit() << 4) | vm()); + } else { + appendFPRegisterName('s', (vd() << 1) | dBit()); + appendSeparator(); + appendFPRegisterName('s', (vm() << 1) | mBit()); + } + + return m_formatBuffer; +} + +const char* ARMv7DOpcodeVCVTBetweenFPAndInt::format() +{ + bufferPrintf(" vcvt"); + bool convertToInteger = op2() & 0x4; + + if (convertToInteger) { + if (!op()) + appendCharacter('r'); // Round using mode in FPSCR + if (condition() != 0xe) + appendString(conditionName(condition())); + appendCharacter('.'); + appendCharacter((op2() & 1) ? 's' : 'u'); + appendString("32.f"); + appendString(szBit() ? "64" : "32"); + appendCharacter(' '); + appendFPRegisterName('s', (vd() << 1) | dBit()); + appendSeparator(); + if (szBit()) + appendFPRegisterName('d', (mBit() << 4) | vm()); + else + appendFPRegisterName('s', (vm() << 1) | mBit()); + } else { + if (condition() != 0xe) + appendString(conditionName(condition())); + appendCharacter('.'); + appendString(szBit() ? "f64." : "f32."); + appendString(op() ? "s32" : "u32"); + appendCharacter(' '); + if (szBit()) + appendFPRegisterName('d', (dBit() << 4) | vd()); + else + appendFPRegisterName('s', (vd() << 1) | dBit()); + appendSeparator(); + appendFPRegisterName('s', (vm() << 1) | mBit()); + } + + return m_formatBuffer; +} + +const char* ARMv7DOpcodeVLDR::format() +{ + if (condition() != 0xe) + bufferPrintf(" vldr%-3.3s", conditionName(condition())); + else + appendInstructionName("vldr"); + + appendFPRegisterName(doubleReg() ? 'd' : 's', vd()); + appendSeparator(); + + int immediate = immediate8() * 4; + + if (!uBit()) + immediate = -immediate; + + appendCharacter('['); + + if (rn() == RegPC) + appendPCRelativeOffset(immediate); + else { + appendRegisterName(rn()); + + if (immediate) { + appendSeparator(); + appendSignedImmediate(immediate); + } + } + + appendCharacter(']'); + + return m_formatBuffer; +} + +const char* ARMv7DOpcodeVMOVDoublePrecision::format() +{ + appendInstructionName("vmov"); + if (op()) { + appendRegisterName(rt()); + appendSeparator(); + appendRegisterName(rt2()); + appendSeparator(); + } + + appendFPRegisterName('d', vm()); + + if (!op()) { + appendSeparator(); + appendRegisterName(rt()); + appendSeparator(); + appendRegisterName(rt2()); + } + + return m_formatBuffer; +} + +const char* ARMv7DOpcodeVMOVSinglePrecision::format() +{ + appendInstructionName("vmov"); + if (op()) { + appendRegisterName(rt()); + appendSeparator(); + appendRegisterName(rt2()); + appendSeparator(); + } + + appendFPRegisterName('s', vm()); + appendSeparator(); + appendFPRegisterName('s', (vm() + 1) % 32); + + if (!op()) { + appendSeparator(); + appendRegisterName(rt()); + appendSeparator(); + appendRegisterName(rt2()); + } + + return m_formatBuffer; +} + +const char* ARMv7DOpcodeVMSR::format() +{ + appendInstructionName("vmrs"); + if (opL()) { + if (rt() == 0xf) + appendString("apsr_nzcv"); + else + appendRegisterName(rt()); + appendSeparator(); + } + + appendString("fpscr"); + + if (!opL()) { + appendSeparator(); + appendRegisterName(rt()); + } + + return m_formatBuffer; +} + +} } // namespace JSC::ARMv7Disassembler + +#endif // #if USE(ARMV7_DISASSEMBLER) diff --git a/Source/JavaScriptCore/disassembler/ARMv7/ARMv7DOpcode.h b/Source/JavaScriptCore/disassembler/ARMv7/ARMv7DOpcode.h new file mode 100644 index 000000000..13e209db7 --- /dev/null +++ b/Source/JavaScriptCore/disassembler/ARMv7/ARMv7DOpcode.h @@ -0,0 +1,1237 @@ +/* + * Copyright (C) 2013 Apple Inc. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY APPLE INC. ``AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL APPLE INC. OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY + * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef ARMv7DOpcode_h +#define ARMv7DOpcode_h + +#if USE(ARMV7_DISASSEMBLER) + +#include +#include + +namespace JSC { namespace ARMv7Disassembler { + +class ARMv7DOpcode { +public: + static void init(); + + ARMv7DOpcode() + : m_opcode(0) + , m_bufferOffset(0) + { + init(); + + for (unsigned i = 0; i < 4; i++) + m_ifThenConditions[i] = CondNone; + + endITBlock(); + + m_formatBuffer[0] = '\0'; + } + + const char* disassemble(uint16_t*& currentPC); + +protected: + const unsigned RegSP = 0xd; + const unsigned RegLR = 0xe; + const unsigned RegPC = 0xf; + + void fetchOpcode(uint16_t*&); + bool is32BitInstruction() { return (m_opcode & 0xfffff800) > 0xe000; } + bool isFPInstruction() { return (m_opcode & 0xfc000e00) == 0xec000a00; } + + static const char* const s_conditionNames[16]; + static const char* const s_shiftNames[4]; + static const char* const s_optionName[8]; + static const char* const s_specialRegisterNames[3]; + + static const char* conditionName(unsigned condition) { return s_conditionNames[condition & 0xf]; } + static const char* shiftName(unsigned shiftValue) { return s_shiftNames[shiftValue & 0x3]; } + + bool inITBlock() { return m_ITConditionIndex < m_ITBlocksize; } + bool startingITBlock() { return m_ITConditionIndex == m_ITBlocksize + 1; } + + void startITBlock(unsigned, unsigned); + void saveITConditionAt(unsigned, unsigned); + void endITBlock() + { + m_currentITCondition = CondNone; + m_ITConditionIndex = 0; + m_ITBlocksize = 0; + } + + void bufferPrintf(const char* format, ...) WTF_ATTRIBUTE_PRINTF(2, 3); + void appendInstructionName(const char*, bool addS = false); + + void appendInstructionNameNoITBlock(const char* instructionName) + { + bufferPrintf(" %-7.7s", instructionName); + } + + void appendRegisterName(unsigned); + void appendRegisterList(unsigned); + void appendFPRegisterName(char, unsigned); + + void appendSeparator() + { + bufferPrintf(", "); + } + + void appendCharacter(const char c) + { + bufferPrintf("%c", c); + } + + void appendString(const char* string) + { + bufferPrintf("%s", string); + } + + void appendShiftType(unsigned shiftValue) + { + bufferPrintf("%s ", shiftName(shiftValue)); + } + + void appendSignedImmediate(int immediate) + { + bufferPrintf("#%d", immediate); + } + + void appendUnsignedImmediate(unsigned immediate) + { + bufferPrintf("#%u", immediate); + } + + void appendPCRelativeOffset(int32_t immediate) + { + bufferPrintf("0x%x", reinterpret_cast(m_currentPC + immediate)); + } + + void appendShiftAmount(unsigned amount) + { + bufferPrintf("lsl #%u", 16 * amount); + } + + static const int bufferSize = 81; + static const unsigned char CondNone = 0xe; + static const unsigned MaxITBlockSize = 4; + + char m_formatBuffer[bufferSize]; + unsigned char m_ifThenConditions[MaxITBlockSize]; + uint16_t* m_currentPC; + uint32_t m_opcode; + int m_bufferOffset; + int m_currentITCondition; + unsigned m_ITConditionIndex; + unsigned m_ITBlocksize; + +private: + static bool s_initialized; +}; + +#define DEFINE_STATIC_FORMAT16(klass, thisObj) \ + static const char* format(ARMv7D16BitOpcode* thisObj) { return reinterpret_cast< klass *>(thisObj)->format(); } + +class ARMv7D16BitOpcode : public ARMv7DOpcode { +private: + class OpcodeGroup { + public: + OpcodeGroup(uint16_t opcodeMask, uint16_t opcodePattern, const char* (*format)(ARMv7D16BitOpcode*)) + : m_opcodeMask(opcodeMask) + , m_opcodePattern(opcodePattern) + , m_format(format) + , m_next(0) + { + } + + void setNext(OpcodeGroup* next) + { + m_next = next; + } + + OpcodeGroup* next() + { + return m_next; + } + + bool matches(uint16_t opcode) + { + return (opcode & m_opcodeMask) == m_opcodePattern; + } + + const char* format(ARMv7D16BitOpcode* thisObj) + { + return m_format(thisObj); + } + + public: + static const unsigned opcodeTableSize = 32; + static const unsigned opcodeTableMask = opcodeTableSize-1; + + // private: + uint16_t m_opcodeMask; + uint16_t m_opcodePattern; + const char* (*m_format)(ARMv7D16BitOpcode*); + OpcodeGroup* m_next; + }; + +public: + static void init(); + + const char* defaultFormat(); + const char* doDisassemble(); + +protected: + unsigned rm() { return (m_opcode >> 3) & 0x7; } + unsigned rd() { return m_opcode & 0x7; } + unsigned opcodeGroupNumber(unsigned opcode) { return (opcode >> 11) & OpcodeGroup::opcodeTableMask; } + +private: + static OpcodeGroup* opcodeTable[OpcodeGroup::opcodeTableSize]; +}; + +class ARMv7DOpcodeAddRegisterT2 : public ARMv7D16BitOpcode { +public: + static const uint16_t s_mask = 0xff00; + static const uint16_t s_pattern = 0x4400; + + DEFINE_STATIC_FORMAT16(ARMv7DOpcodeAddRegisterT2, thisObj); + +protected: + const char* format(); + + unsigned rdn() { return ((m_opcode >> 4) & 0x8) | (m_opcode & 0x7); } + unsigned rm() { return ((m_opcode >> 3) & 0xf); } +}; + +class ARMv7DOpcodeAddSPPlusImmediate : public ARMv7D16BitOpcode { +public: + static const uint16_t s_mask = 0xf800; + static const uint16_t s_pattern = 0xc800; + + DEFINE_STATIC_FORMAT16(ARMv7DOpcodeAddSPPlusImmediate, thisObj); + +protected: + const char* format(); + + unsigned rd() { return (m_opcode >> 8) & 0x7; } + unsigned immediate8() { return m_opcode & 0x0ff; } +}; + +class ARMv7DOpcodeAddSubtract : public ARMv7D16BitOpcode { +protected: + static const char* const s_opNames[2]; +}; + +class ARMv7DOpcodeAddSubtractT1 : public ARMv7DOpcodeAddSubtract { +public: + static const uint16_t s_mask = 0xfc00; + static const uint16_t s_pattern = 0x1800; + + DEFINE_STATIC_FORMAT16(ARMv7DOpcodeAddSubtractT1, thisObj); + +protected: + const char* format(); + + const char* opName() { return s_opNames[op()]; } + + unsigned op() { return (m_opcode >> 9) & 0x1; } + unsigned rm() { return (m_opcode >> 6) & 0x7; } + unsigned rn() { return (m_opcode >> 3) & 0x7; } +}; + +class ARMv7DOpcodeAddSubtractImmediate3 : public ARMv7DOpcodeAddSubtract { +public: + static const uint16_t s_mask = 0xfc00; + static const uint16_t s_pattern = 0x1c00; + + DEFINE_STATIC_FORMAT16(ARMv7DOpcodeAddSubtractImmediate3, thisObj); + +protected: + const char* format(); + + const char* opName() { return s_opNames[op()]; } + + unsigned op() { return (m_opcode >> 9) & 0x1; } + unsigned immediate3() { return (m_opcode >> 6) & 0x7; } + unsigned rn() { return (m_opcode >> 3) & 0x7; } +}; + +class ARMv7DOpcodeAddSubtractImmediate8 : public ARMv7DOpcodeAddSubtract { +public: + static const uint16_t s_mask = 0xf000; + static const uint16_t s_pattern = 0x3000; + + DEFINE_STATIC_FORMAT16(ARMv7DOpcodeAddSubtractImmediate8, thisObj); + +protected: + const char* format(); + + const char* opName() { return s_opNames[op()]; } + + unsigned op() { return (m_opcode >> 11) & 0x1; } + unsigned rdn() { return (m_opcode >> 8) & 0x7; } + unsigned immediate8() { return m_opcode & 0xff; } +}; + +class ARMv7DOpcodeBranchConditionalT1 : public ARMv7D16BitOpcode { +public: + static const uint16_t s_mask = 0xf000; + static const uint16_t s_pattern = 0xd000; + + DEFINE_STATIC_FORMAT16(ARMv7DOpcodeBranchConditionalT1, thisObj); + +protected: + const char* format(); + + unsigned condition() { return (m_opcode >> 8) & 0xf; } + int offset() { return static_cast(m_opcode & 0xff); } +}; + +class ARMv7DOpcodeBranchExchangeT1 : public ARMv7D16BitOpcode { +public: + static const uint16_t s_mask = 0xff00; + static const uint16_t s_pattern = 0x4700; + + DEFINE_STATIC_FORMAT16(ARMv7DOpcodeBranchExchangeT1, thisObj); + +protected: + const char* format(); + + const char* opName() { return (m_opcode & 0x80) ? "blx" : "bx"; } + unsigned rm() { return ((m_opcode >> 3) & 0xf); } +}; + +class ARMv7DOpcodeBranchT2 : public ARMv7D16BitOpcode { +public: + static const uint16_t s_mask = 0xf800; + static const uint16_t s_pattern = 0xe000; + + DEFINE_STATIC_FORMAT16(ARMv7DOpcodeBranchT2, thisObj); + +protected: + const char* format(); + + int immediate11() { return static_cast(m_opcode & 0x7ff); } +}; + +class ARMv7DOpcodeCompareImmediateT1 : public ARMv7D16BitOpcode { +public: + static const uint16_t s_mask = 0xf800; + static const uint16_t s_pattern = 0x2800; + + DEFINE_STATIC_FORMAT16(ARMv7DOpcodeCompareImmediateT1, thisObj); + +protected: + const char* format(); + + unsigned rn() { return (m_opcode >> 8) & 0x3; } + unsigned immediate8() { return m_opcode & 0xff; } +}; + +class ARMv7DOpcodeCompareRegisterT1 : public ARMv7D16BitOpcode { +public: + static const uint16_t s_mask = 0xffc0; + static const uint16_t s_pattern = 0x4280; + + DEFINE_STATIC_FORMAT16(ARMv7DOpcodeCompareRegisterT1, thisObj); + +protected: + const char* format(); + + unsigned rn() { return m_opcode & 0x7; } +}; + +class ARMv7DOpcodeCompareRegisterT2 : public ARMv7D16BitOpcode { +public: + static const uint16_t s_mask = 0xff00; + static const uint16_t s_pattern = 0x4500; + + DEFINE_STATIC_FORMAT16(ARMv7DOpcodeCompareRegisterT2, thisObj); + +protected: + const char* format(); + + unsigned rn() { return ((m_opcode >> 4) & 0x8) | (m_opcode & 0x7); } + unsigned rm() { return ((m_opcode >> 3) & 0xf); } +}; + +class ARMv7DOpcodeDataProcessingRegisterT1 : public ARMv7D16BitOpcode { +private: + static const char* const s_opNames[16]; + +public: + static const uint16_t s_mask = 0xfc00; + static const uint16_t s_pattern = 0x4000; + + DEFINE_STATIC_FORMAT16(ARMv7DOpcodeDataProcessingRegisterT1, thisObj); + +protected: + const char* format(); + + const char* opName() { return s_opNames[op()]; } + + unsigned op() { return (m_opcode >> 6) & 0xf; } + + unsigned rm() { return (m_opcode >> 3) & 0x7; } + unsigned rdn() { return m_opcode & 0x7; } +}; + +class ARMv7DOpcodeGeneratePCRelativeAddress : public ARMv7D16BitOpcode { +public: + static const uint16_t s_mask = 0xf800; + static const uint16_t s_pattern = 0xa000; + + DEFINE_STATIC_FORMAT16(ARMv7DOpcodeGeneratePCRelativeAddress, thisObj); + +protected: + const char* format(); + + unsigned rd() { return (m_opcode >> 8) & 0x7; } + unsigned immediate8() { return m_opcode & 0x0ff; } +}; + +class ARMv7DOpcodeLoadFromLiteralPool : public ARMv7D16BitOpcode { +public: + static const uint16_t s_mask = 0xf800; + static const uint16_t s_pattern = 0x4800; + + DEFINE_STATIC_FORMAT16(ARMv7DOpcodeLoadFromLiteralPool, thisObj); + +protected: + const char* format(); + + unsigned rt() { return (m_opcode >> 8) & 0x7; } + unsigned immediate8() { return m_opcode & 0x0ff; } +}; + +class ARMv7DOpcodeLoadStoreRegisterImmediate : public ARMv7D16BitOpcode { +private: + static const char* const s_opNames[6]; + +public: + const char* format(); + +protected: + const char* opName() { return s_opNames[op()]; } + + unsigned op() { return ((m_opcode >> 11) & 0x1f) - 0xc; } + unsigned immediate5() { return (m_opcode >> 6) & 0x01f; } + unsigned rn() { return (m_opcode >> 3) & 0x7; } + unsigned rt() { return m_opcode & 0x7; } + unsigned scale(); +}; + +class ARMv7DOpcodeLoadStoreRegisterImmediateWordAndByte : public ARMv7DOpcodeLoadStoreRegisterImmediate { +public: + static const uint16_t s_mask = 0xe000; + static const uint16_t s_pattern = 0x6000; + + DEFINE_STATIC_FORMAT16(ARMv7DOpcodeLoadStoreRegisterImmediate, thisObj); +}; + +class ARMv7DOpcodeStoreRegisterImmediateHalfWord : public ARMv7DOpcodeLoadStoreRegisterImmediate { +public: + static const uint16_t s_mask = 0xf800; + static const uint16_t s_pattern = 0x8000; + + DEFINE_STATIC_FORMAT16(ARMv7DOpcodeLoadStoreRegisterImmediate, thisObj); +}; + +class ARMv7DOpcodeLoadRegisterImmediateHalfWord : public ARMv7DOpcodeLoadStoreRegisterImmediate { +public: + static const uint16_t s_mask = 0xf800; + static const uint16_t s_pattern = 0x8800; + + DEFINE_STATIC_FORMAT16(ARMv7DOpcodeLoadStoreRegisterImmediate, thisObj); +}; + +class ARMv7DOpcodeLoadStoreRegisterOffsetT1 : public ARMv7D16BitOpcode { +private: + static const char* const s_opNames[8]; + +public: + static const uint16_t s_mask = 0xf000; + static const uint16_t s_pattern = 0x5000; + + DEFINE_STATIC_FORMAT16(ARMv7DOpcodeLoadStoreRegisterOffsetT1, thisObj); + +protected: + const char* format(); + + const char* opName() { return s_opNames[opB()]; } + + unsigned opB() { return (m_opcode >> 9) & 0x7; } + unsigned rm() { return (m_opcode >> 6) & 0x7; } + unsigned rn() { return (m_opcode >> 3) & 0x7; } + unsigned rt() { return m_opcode & 0x7; } +}; + +class ARMv7DOpcodeLoadStoreRegisterSPRelative : public ARMv7D16BitOpcode { +private: + static const char* const s_opNames[8]; + +public: + static const uint16_t s_mask = 0xf000; + static const uint16_t s_pattern = 0x9000; + + DEFINE_STATIC_FORMAT16(ARMv7DOpcodeLoadStoreRegisterSPRelative, thisObj); + +protected: + const char* format(); + + const char* opName() { return op() ? "ldr" : "str"; } + + unsigned op() { return (m_opcode >> 11) & 0x1; } + unsigned rt() { return (m_opcode >> 8) & 0x7; } + unsigned immediate8() { return m_opcode & 0xff; } +}; + +class ARMv7DOpcodeLogicalImmediateT1 : public ARMv7D16BitOpcode { +public: + static const uint16_t s_mask = 0xe000; + static const uint16_t s_pattern = 0x0000; + + DEFINE_STATIC_FORMAT16(ARMv7DOpcodeLogicalImmediateT1, thisObj); + +protected: + const char* format(); + + const char* opName() { return shiftName(op()); } + + unsigned op() { return (m_opcode >> 12) & 0x3; } + unsigned immediate5() { return (m_opcode >> 6) & 0x1f; } +}; + +class ARMv7DOpcodeMiscAddSubSP : public ARMv7D16BitOpcode { +public: + static const uint16_t s_mask = 0xff00; + static const uint16_t s_pattern = 0xb000; + + DEFINE_STATIC_FORMAT16(ARMv7DOpcodeMiscAddSubSP, thisObj); + +protected: + const char* format(); + + const char* opName() { return op() ? "sub" : "add"; } + unsigned op() { return (m_opcode >> 7) & 0x1; } + unsigned immediate7() { return m_opcode & 0x7f; } +}; + +class ARMv7DOpcodeMiscByteHalfwordOps : public ARMv7D16BitOpcode { +private: + static const char* const s_opNames[8]; + +public: + static const uint16_t s_mask = 0xf700; + static const uint16_t s_pattern = 0xb200; + + DEFINE_STATIC_FORMAT16(ARMv7DOpcodeMiscByteHalfwordOps, thisObj); + +protected: + const char* format(); + + const char* opName() { return s_opNames[op()]; } + unsigned op() { return ((m_opcode >> 9) & 0x4) || ((m_opcode >> 6) & 0x3); } +}; + +class ARMv7DOpcodeMiscBreakpointT1 : public ARMv7D16BitOpcode { +public: + static const uint16_t s_mask = 0xff00; + static const uint16_t s_pattern = 0xbe00; + + DEFINE_STATIC_FORMAT16(ARMv7DOpcodeMiscBreakpointT1, thisObj); + +protected: + const char* format(); + + unsigned immediate8() { return m_opcode & 0xff; } +}; + +class ARMv7DOpcodeMiscCompareAndBranch : public ARMv7D16BitOpcode { +public: + static const uint16_t s_mask = 0xf500; + static const uint16_t s_pattern = 0xb100; + + DEFINE_STATIC_FORMAT16(ARMv7DOpcodeMiscCompareAndBranch, thisObj); + +protected: + const char* format(); + + const char* opName() { return op() ? "cbnz" : "cbz"; } + unsigned op() { return (m_opcode >> 11) & 0x1; } + int32_t immediate6() { return ((m_opcode >> 4) & 0x20) | ((m_opcode >> 3) & 0x1f); } + unsigned rn() { return m_opcode & 0x7; } +}; + +class ARMv7DOpcodeMiscHint16 : public ARMv7D16BitOpcode { +private: + static const char* const s_opNames[16]; + +public: + static const uint16_t s_mask = 0xff0f; + static const uint16_t s_pattern = 0xbf00; + + DEFINE_STATIC_FORMAT16(ARMv7DOpcodeMiscHint16, thisObj); + +protected: + const char* format(); + + const char* opName() { return s_opNames[opA()]; } + unsigned opA() { return (m_opcode >> 4) & 0xf; } +}; + +class ARMv7DOpcodeMiscIfThenT1 : public ARMv7D16BitOpcode { +public: + static const uint16_t s_mask = 0xff00; + static const uint16_t s_pattern = 0xbf00; + + DEFINE_STATIC_FORMAT16(ARMv7DOpcodeMiscIfThenT1, thisObj); + +protected: + const char* format(); + + unsigned firstCondition() { return (m_opcode >> 4) & 0xf; } + unsigned mask() { return m_opcode & 0xf; } +}; + +class ARMv7DOpcodeMiscPushPop : public ARMv7D16BitOpcode { +public: + static const uint16_t s_mask = 0xf600; + static const uint16_t s_pattern = 0xb400; + + DEFINE_STATIC_FORMAT16(ARMv7DOpcodeMiscPushPop, thisObj); + +protected: + const char* format(); + + const char* opName() { return op() ? "pop" : "push"; } + unsigned op() { return (m_opcode >> 11) & 0x1; } + unsigned registerMask() { return ((m_opcode << 6) & 0x4000) | (m_opcode & 0xff); } +}; + +class ARMv7DOpcodeMoveImmediateT1 : public ARMv7D16BitOpcode { +public: + static const uint16_t s_mask = 0xf800; + static const uint16_t s_pattern = 0x2000; + + DEFINE_STATIC_FORMAT16(ARMv7DOpcodeMoveImmediateT1, thisObj); + +protected: + const char* format(); + + unsigned rd() { return (m_opcode >> 8) & 0x3; } + unsigned immediate8() { return m_opcode & 0xff; } +}; + +class ARMv7DOpcodeMoveRegisterT1 : public ARMv7D16BitOpcode { +public: + static const uint16_t s_mask = 0xff00; + static const uint16_t s_pattern = 0x4600; + + DEFINE_STATIC_FORMAT16(ARMv7DOpcodeMoveRegisterT1, thisObj); + +protected: + const char* format(); + + unsigned rd() { return ((m_opcode >> 4) & 0x8) | (m_opcode & 0x7); } + unsigned rm() { return ((m_opcode >> 3) & 0xf); } +}; + +// 32 Bit instructions + +#define DEFINE_STATIC_FORMAT32(klass, thisObj) \ + static const char* format(ARMv7D32BitOpcode* thisObj) { return reinterpret_cast< klass *>(thisObj)->format(); } + +class ARMv7D32BitOpcode : public ARMv7DOpcode { +private: + class OpcodeGroup { + public: + OpcodeGroup(uint32_t opcodeMask, uint32_t opcodePattern, const char* (*format)(ARMv7D32BitOpcode*)) + : m_opcodeMask(opcodeMask) + , m_opcodePattern(opcodePattern) + , m_format(format) + , m_next(0) + { + } + + void setNext(OpcodeGroup* next) + { + m_next = next; + } + + OpcodeGroup* next() + { + return m_next; + } + + bool matches(uint32_t opcode) + { + return (opcode & m_opcodeMask) == m_opcodePattern; + } + + const char* format(ARMv7D32BitOpcode* thisObj) + { + return m_format(thisObj); + } + + public: + static const unsigned opcodeTableSize = 16; + static const unsigned opcodeTableMask = opcodeTableSize-1; + + private: + uint32_t m_opcodeMask; + uint32_t m_opcodePattern; + const char* (*m_format)(ARMv7D32BitOpcode*); + OpcodeGroup* m_next; + }; + +public: + static void init(); + + const char* defaultFormat(); + const char* doDisassemble(); + +protected: + unsigned rd() { return (m_opcode >> 8) & 0xf; } + unsigned rm() { return m_opcode & 0xf; } + unsigned rn() { return (m_opcode >> 16) & 0xf; } + unsigned rt() { return (m_opcode >> 12) & 0xf; } + + unsigned opcodeGroupNumber(unsigned opcode) { return (opcode >> 25) & OpcodeGroup::opcodeTableMask; } + +private: + static OpcodeGroup* opcodeTable[OpcodeGroup::opcodeTableSize]; +}; + +class ARMv7DOpcodeBranchRelative : public ARMv7D32BitOpcode { +protected: + unsigned sBit() { return (m_opcode >> 26) & 0x1; } + unsigned j1() { return (m_opcode >> 13) & 0x1; } + unsigned j2() { return (m_opcode >> 11) & 0x1; } + unsigned immediate11() { return m_opcode & 0x7ff; } +}; + +class ARMv7DOpcodeConditionalBranchT3 : public ARMv7DOpcodeBranchRelative { +public: + static const uint32_t s_mask = 0xf800d000; + static const uint32_t s_pattern = 0xf0008000; + + DEFINE_STATIC_FORMAT32(ARMv7DOpcodeConditionalBranchT3, thisObj); + +protected: + const char* format(); + + int32_t offset() { return ((static_cast(sBit() << 31)) >> 12) | static_cast((j1() << 18) | (j2() << 17) | (immediate6() << 11) | immediate11()); } + unsigned condition() { return (m_opcode >> 22) & 0xf; } + unsigned immediate6() { return (m_opcode >> 16) & 0x3f; } +}; + +class ARMv7DOpcodeBranchOrBranchLink : public ARMv7DOpcodeBranchRelative { +public: + static const uint32_t s_mask = 0xf8009000; + static const uint32_t s_pattern = 0xf0009000; + + DEFINE_STATIC_FORMAT32(ARMv7DOpcodeBranchOrBranchLink, thisObj); + +protected: + const char* format(); + + int32_t offset() { return ((static_cast(sBit() << 31)) >> 8) | static_cast((~(j1() ^ sBit()) << 22) | (~(j2() ^ sBit()) << 21) | (immediate10() << 11) | immediate11()); } + unsigned immediate10() { return (m_opcode >> 16) & 0x3ff; } + bool isBL() { return !!((m_opcode >> 14) & 0x1); } +}; + +class ARMv7DOpcodeDataProcessingLogicalAndRithmetic : public ARMv7D32BitOpcode { +protected: + static const char* const s_opNames[16]; +}; + +class ARMv7DOpcodeDataProcessingModifiedImmediate : public ARMv7DOpcodeDataProcessingLogicalAndRithmetic { +private: + void appendImmShift(unsigned, unsigned); + +public: + static const uint32_t s_mask = 0xfa008000; + static const uint32_t s_pattern = 0xf0000000; + + DEFINE_STATIC_FORMAT32(ARMv7DOpcodeDataProcessingModifiedImmediate, thisObj); + +protected: + const char* format(); + void appendModifiedImmediate(unsigned); + + const char* opName() { return s_opNames[op()]; } + + unsigned op() { return (m_opcode >> 21) & 0xf; } + unsigned sBit() { return (m_opcode >> 20) & 0x1; } + unsigned immediate12() { return ((m_opcode >> 15) & 0x0800) | ((m_opcode >> 4) & 0x0700) | (m_opcode & 0x00ff); } +}; + +class ARMv7DOpcodeDataProcessingShiftedReg : public ARMv7DOpcodeDataProcessingLogicalAndRithmetic { +private: + void appendImmShift(unsigned, unsigned); + +public: + static const uint32_t s_mask = 0xfe000000; + static const uint32_t s_pattern = 0xea000000; + + DEFINE_STATIC_FORMAT32(ARMv7DOpcodeDataProcessingShiftedReg, thisObj); + +protected: + const char* format(); + + const char* opName() { return s_opNames[op()]; } + + unsigned sBit() { return (m_opcode >> 20) & 0x1; } + unsigned op() { return (m_opcode >> 21) & 0xf; } + unsigned immediate5() { return ((m_opcode >> 10) & 0x1c) | ((m_opcode >> 6) & 0x3); } + unsigned type() { return (m_opcode >> 4) & 0x3; } + unsigned tbBit() { return (m_opcode >> 5) & 0x1; } + unsigned tBit() { return (m_opcode >> 4) & 0x1; } +}; + +class ARMv7DOpcodeDataProcessingReg : public ARMv7D32BitOpcode { +protected: + unsigned op1() { return (m_opcode >> 20) & 0xf; } + unsigned op2() { return (m_opcode >> 4) & 0xf; } +}; + +class ARMv7DOpcodeDataProcessingRegShift : public ARMv7DOpcodeDataProcessingReg { +public: + static const uint32_t s_mask = 0xffe0f0f0; + static const uint32_t s_pattern = 0xfa00f000; + + DEFINE_STATIC_FORMAT32(ARMv7DOpcodeDataProcessingRegShift, thisObj); + +protected: + const char* format(); + + const char* opName() { return shiftName((op1() >> 1) & 0x3); } +}; + +class ARMv7DOpcodeDataProcessingRegExtend : public ARMv7DOpcodeDataProcessingReg { +private: + static const char* const s_opExtendNames[8]; + static const char* const s_opExtendAndAddNames[8]; + +public: + static const uint32_t s_mask = 0xff80f0c0; + static const uint32_t s_pattern = 0xfa00f080; + + DEFINE_STATIC_FORMAT32(ARMv7DOpcodeDataProcessingRegExtend, thisObj); + +protected: + const char* format(); + + const char* opExtendName() { return s_opExtendNames[op1()]; } + const char* opExtendAndAddName() { return s_opExtendAndAddNames[op1()]; } + unsigned rotate() { return (m_opcode >> 4) & 0x3; } +}; + +class ARMv7DOpcodeDataProcessingRegParallel : public ARMv7DOpcodeDataProcessingReg { +private: + static const char* const s_opNames[16]; + +public: + static const uint32_t s_mask = 0xff80f0e0; + static const uint32_t s_pattern = 0xfa00f000; + + DEFINE_STATIC_FORMAT32(ARMv7DOpcodeDataProcessingRegParallel, thisObj); + +protected: + const char* format(); + + const char* opName() { return s_opNames[((op1() & 0x7) << 1) | (op2() & 0x1)]; } +}; + +class ARMv7DOpcodeDataProcessingRegMisc : public ARMv7DOpcodeDataProcessingReg { +private: + static const char* const s_opNames[16]; + +public: + static const uint32_t s_mask = 0xffc0f0c0; + static const uint32_t s_pattern = 0xfa80f080; + + DEFINE_STATIC_FORMAT32(ARMv7DOpcodeDataProcessingRegMisc, thisObj); + +protected: + const char* format(); + + const char* opName() { return s_opNames[((op1() & 0x3) << 2) | (op2() & 0x3)]; } +}; + +class ARMv7DOpcodeHint32 : public ARMv7D32BitOpcode { +private: + static const char* const s_opNames[8]; + +public: + static const uint32_t s_mask = 0xfff0d000; + static const uint32_t s_pattern = 0xf3a08000; + + DEFINE_STATIC_FORMAT32(ARMv7DOpcodeHint32, thisObj); + +protected: + const char* format(); + + const char* opName() { return s_opNames[op()]; } + + bool isDebugHint() { return (m_opcode & 0xf0) == 0xf0; } + unsigned debugOption() { return m_opcode & 0xf; } + unsigned op() { return m_opcode & 0x7; } +}; + +class ARMv7DOpcodeFPTransfer : public ARMv7D32BitOpcode { +public: + static const uint32_t s_mask = 0xffc00e7f; + static const uint32_t s_pattern = 0xee000a10; + + DEFINE_STATIC_FORMAT32(ARMv7DOpcodeFPTransfer, thisObj); + +protected: + const char* format(); + + void appendFPRegister(); + + unsigned opH() { return (m_opcode >> 21) & 0x1; } + unsigned opL() { return (m_opcode >> 20) & 0x1; } + unsigned rt() { return (m_opcode >> 12) & 0xf; } + unsigned opC() { return (m_opcode >> 8) & 0x1; } + unsigned opB() { return (m_opcode >> 5) & 0x3; } + unsigned vd() { return ((m_opcode >> 3) & 0x10) | ((m_opcode >> 16) & 0xf); } + unsigned vn() { return ((m_opcode >> 7) & 0x1) | ((m_opcode >> 15) & 0x1e); } +}; + +class ARMv7DOpcodeDataLoad : public ARMv7D32BitOpcode { +protected: + static const char* const s_opNames[8]; + +protected: + const char* opName() { return s_opNames[op()]; } + + unsigned op() { return ((m_opcode >> 22) & 0x4) | ((m_opcode >> 21) & 0x3); } +}; + +class ARMv7DOpcodeLoadRegister : public ARMv7DOpcodeDataLoad { +public: + static const uint32_t s_mask = 0xfe900800; + static const uint32_t s_pattern = 0xf8100000; + + DEFINE_STATIC_FORMAT32(ARMv7DOpcodeLoadRegister, thisObj); + +protected: + const char* format(); + + unsigned immediate2() { return (m_opcode >> 4) & 0x3; } +}; + +class ARMv7DOpcodeLoadSignedImmediate : public ARMv7DOpcodeDataLoad { +public: + static const uint32_t s_mask = 0xfe900800; + static const uint32_t s_pattern = 0xf8100800; + + DEFINE_STATIC_FORMAT32(ARMv7DOpcodeLoadSignedImmediate, thisObj); + +protected: + const char* format(); + + unsigned pBit() { return (m_opcode >> 10) & 0x1; } + unsigned uBit() { return (m_opcode >> 9) & 0x1; } + unsigned wBit() { return (m_opcode >> 8) & 0x1; } + unsigned immediate8() { return m_opcode & 0xff; } +}; + +class ARMv7DOpcodeLoadUnsignedImmediate : public ARMv7DOpcodeDataLoad { +public: + static const uint32_t s_mask = 0xfe900000; + static const uint32_t s_pattern = 0xf8900000; + + DEFINE_STATIC_FORMAT32(ARMv7DOpcodeLoadUnsignedImmediate, thisObj); + +protected: + const char* format(); + + unsigned immediate12() { return m_opcode & 0xfff; } +}; + +class ARMv7DOpcodeLongMultipleDivide : public ARMv7D32BitOpcode { +protected: + static const char* const s_opNames[8]; + static const char* const s_smlalOpNames[4]; + static const char* const s_smlaldOpNames[2]; + static const char* const s_smlsldOpNames[2]; + +public: + static const uint32_t s_mask = 0xff800000; + static const uint32_t s_pattern = 0xfb800000; + + DEFINE_STATIC_FORMAT32(ARMv7DOpcodeLongMultipleDivide, thisObj); + +protected: + const char* format(); + + const char* opName() { return s_opNames[op1()]; } + const char* smlalOpName() { return s_smlalOpNames[(nBit() << 1) | mBit()]; } + const char* smlaldOpName() { return s_smlaldOpNames[mBit()]; } + const char* smlsldOpName() { return s_smlsldOpNames[mBit()]; } + + unsigned rdLo() { return rt(); } + unsigned rdHi() { return rd(); } + unsigned op1() { return (m_opcode >> 20) & 0x7; } + unsigned op2() { return (m_opcode >> 4) & 0xf; } + unsigned nBit() { return (m_opcode >> 5) & 0x1; } + unsigned mBit() { return (m_opcode >> 4) & 0x1; } +}; + +class ARMv7DOpcodeDataPushPopSingle : public ARMv7D32BitOpcode { +public: + static const uint32_t s_mask = 0xffef0fff; + static const uint32_t s_pattern = 0xf84d0d04; + + DEFINE_STATIC_FORMAT32(ARMv7DOpcodeDataPushPopSingle, thisObj); + +protected: + const char* format(); + + const char* opName() { return op() ? "pop" : "push"; } + unsigned op() { return (m_opcode >> 20) & 0x1; } +}; + +class ARMv7DOpcodeDataPushPopMultiple : public ARMv7D32BitOpcode { +protected: + void appendRegisterList(); + + unsigned registerList() { return m_opcode & 0xffff; } + unsigned condition() { return m_opcode >> 28; } +}; + +class ARMv7DOpcodeDataPopMultiple : public ARMv7DOpcodeDataPushPopMultiple { +public: + static const uint32_t s_mask = 0x0fff0000; + static const uint32_t s_pattern = 0x08bd0000; + + DEFINE_STATIC_FORMAT32(ARMv7DOpcodeDataPopMultiple, thisObj); + +protected: + const char* format(); +}; + +class ARMv7DOpcodeDataPushMultiple : public ARMv7DOpcodeDataPushPopMultiple { +public: + static const uint32_t s_mask = 0xfe7f0000; + static const uint32_t s_pattern = 0xe82d0000; + + DEFINE_STATIC_FORMAT32(ARMv7DOpcodeDataPushMultiple, thisObj); + +protected: + const char* format(); +}; + +class ARMv7DOpcodeDataStoreSingle : public ARMv7D32BitOpcode { +protected: + static const char* const s_opNames[4]; + +protected: + const char* opName() { return s_opNames[op()]; } + + unsigned op() { return (m_opcode >> 21) & 0x3; } +}; + +class ARMv7DOpcodeStoreSingleImmediate12 : public ARMv7DOpcodeDataStoreSingle { +public: + static const uint32_t s_mask = 0xfff00000; + static const uint32_t s_pattern = 0xf8c00000; + + DEFINE_STATIC_FORMAT32(ARMv7DOpcodeStoreSingleImmediate12, thisObj); + + const char* format(); + +protected: + unsigned immediate12() { return m_opcode & 0xfff; } +}; + +class ARMv7DOpcodeStoreSingleImmediate8 : public ARMv7DOpcodeDataStoreSingle { +public: + static const uint32_t s_mask = 0xfff00800; + static const uint32_t s_pattern = 0xf8400800; + + DEFINE_STATIC_FORMAT32(ARMv7DOpcodeStoreSingleImmediate8, thisObj); + + const char* format(); + +protected: + unsigned pBit() { return (m_opcode >> 10) & 0x1; } + unsigned uBit() { return (m_opcode >> 9) & 0x1; } + unsigned wBit() { return (m_opcode >> 8) & 0x1; } + unsigned immediate8() { return m_opcode & 0xff; } +}; + +class ARMv7DOpcodeStoreSingleRegister : public ARMv7DOpcodeDataStoreSingle { +public: + static const uint32_t s_mask = 0xfff00fc0; + static const uint32_t s_pattern = 0xf8400000; + + DEFINE_STATIC_FORMAT32(ARMv7DOpcodeStoreSingleRegister, thisObj); + +protected: + const char* format(); + + unsigned immediate2() { return (m_opcode >> 4) & 0x3; } +}; + +class ARMv7DOpcodeUnmodifiedImmediate : public ARMv7D32BitOpcode { +protected: + static const char* const s_opNames[16]; + +public: + static const uint32_t s_mask = 0xfa008000; + static const uint32_t s_pattern = 0xf2000000; + + DEFINE_STATIC_FORMAT32(ARMv7DOpcodeUnmodifiedImmediate, thisObj); + +protected: + const char* format(); + + const char* opName() { return s_opNames[op() >> 1]; } + + unsigned op() { return (m_opcode >> 20) & 0x1f; } + unsigned shBit() { return (m_opcode >> 21) & 0x1; } + unsigned bitNumOrSatImmediate() { return m_opcode & 0x1f; } + unsigned immediate5() { return ((m_opcode >> 9) & 0x1c) | ((m_opcode >> 6) & 0x3); } + unsigned immediate12() { return ((m_opcode >> 15) & 0x0800) | ((m_opcode >> 4) & 0x0700) | (m_opcode & 0x00ff); } + unsigned immediate16() { return ((m_opcode >> 4) & 0xf000) | ((m_opcode >> 15) & 0x0800) | ((m_opcode >> 4) & 0x0700) | (m_opcode & 0x00ff); } +}; + +class ARMv7DOpcodeVCMP : public ARMv7D32BitOpcode { +public: + static const uint32_t s_mask = 0x0fbf0e50; + static const uint32_t s_pattern = 0x0eb40a40; + + DEFINE_STATIC_FORMAT32(ARMv7DOpcodeVCMP, thisObj); + +protected: + const char* format(); + + unsigned condition() { return m_opcode >> 28; } + unsigned dBit() { return (m_opcode >> 22) & 0x1; } + unsigned vd() { return (m_opcode >> 12) & 0xf; } + unsigned szBit() { return (m_opcode >> 8) & 0x1; } + unsigned eBit() { return (m_opcode >> 7) & 0x1; } + unsigned mBit() { return (m_opcode >> 5) & 0x1; } + unsigned vm() { return m_opcode & 0xf; } +}; + +class ARMv7DOpcodeVCVTBetweenFPAndInt : public ARMv7D32BitOpcode { +public: + static const uint32_t s_mask = 0x0fb80e50; + static const uint32_t s_pattern = 0x0eb80a40; + + DEFINE_STATIC_FORMAT32(ARMv7DOpcodeVCVTBetweenFPAndInt, thisObj); + +protected: + const char* format(); + + unsigned condition() { return m_opcode >> 28; } + unsigned dBit() { return (m_opcode >> 22) & 0x1; } + unsigned op2() { return (m_opcode >> 16) & 0x7; } + unsigned vd() { return (m_opcode >> 12) & 0xf; } + unsigned szBit() { return (m_opcode >> 8) & 0x1; } + unsigned op() { return (m_opcode >> 7) & 0x1; } + unsigned mBit() { return (m_opcode >> 5) & 0x1; } + unsigned vm() { return m_opcode & 0xf; } +}; + +class ARMv7DOpcodeVLDR : public ARMv7D32BitOpcode { +public: + static const uint32_t s_mask = 0x0f300e00; + static const uint32_t s_pattern = 0x0d100a00; + + DEFINE_STATIC_FORMAT32(ARMv7DOpcodeVLDR, thisObj); + +protected: + const char* format(); + + unsigned condition() { return m_opcode >> 28; } + unsigned uBit() { return (m_opcode >> 23) & 0x1; } + unsigned rn() { return (m_opcode >> 16) & 0xf; } + unsigned vd() { return ((m_opcode >> 18) & 0x10) | ((m_opcode >> 12) & 0xf); } + bool doubleReg() { return !!(m_opcode & 0x100); } + unsigned immediate8() { return m_opcode & 0xff; } +}; + +class ARMv7DOpcodeVMOVDoublePrecision : public ARMv7D32BitOpcode { +public: + static const uint32_t s_mask = 0xffe00fd0; + static const uint32_t s_pattern = 0xec400b10; + + DEFINE_STATIC_FORMAT32(ARMv7DOpcodeVMOVDoublePrecision, thisObj); + +protected: + const char* format(); + + unsigned op() { return (m_opcode >> 20) & 0x1; } + unsigned rt2() { return (m_opcode >> 16) & 0xf; } + unsigned rt() { return (m_opcode >> 16) & 0xf; } + unsigned vm() { return (m_opcode & 0xf) | ((m_opcode >> 1) & 0x10); } +}; + +class ARMv7DOpcodeVMOVSinglePrecision : public ARMv7D32BitOpcode { +public: + static const uint32_t s_mask = 0xffe00fd0; + static const uint32_t s_pattern = 0xec400a10; + + DEFINE_STATIC_FORMAT32(ARMv7DOpcodeVMOVSinglePrecision, thisObj); + +protected: + const char* format(); + + unsigned op() { return (m_opcode >> 20) & 0x1; } + unsigned rt2() { return (m_opcode >> 16) & 0xf; } + unsigned rt() { return (m_opcode >> 16) & 0xf; } + unsigned vm() { return ((m_opcode << 1) & 0x1e) | ((m_opcode >> 5) & 0x1); } +}; + +class ARMv7DOpcodeVMSR : public ARMv7D32BitOpcode { +public: + static const uint32_t s_mask = 0xffef0fff; + static const uint32_t s_pattern = 0xeee10a10; + + DEFINE_STATIC_FORMAT32(ARMv7DOpcodeVMSR, thisObj); + +protected: + const char* format(); + + unsigned opL() { return (m_opcode >> 20) & 0x1; } + unsigned rt() { return (m_opcode >> 12) & 0xf; } +}; + + +} } // namespace JSC::ARMv7Disassembler + +using JSC::ARMv7Disassembler::ARMv7DOpcode; + +#endif // #if USE(ARMV7_DISASSEMBLER) + +#endif // ARMv7DOpcode_h diff --git a/Source/JavaScriptCore/disassembler/ARMv7Disassembler.cpp b/Source/JavaScriptCore/disassembler/ARMv7Disassembler.cpp new file mode 100644 index 000000000..bfb48953c --- /dev/null +++ b/Source/JavaScriptCore/disassembler/ARMv7Disassembler.cpp @@ -0,0 +1,55 @@ +/* + * Copyright (C) 2013 Apple Inc. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY APPLE INC. ``AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL APPLE INC. OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY + * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "config.h" +#include "Disassembler.h" + +#if USE(ARMV7_DISASSEMBLER) + +#include "ARMv7/ARMv7DOpcode.h" +#include "MacroAssemblerCodeRef.h" + +namespace JSC { + +bool tryToDisassemble(const MacroAssemblerCodePtr& codePtr, size_t size, const char* prefix, PrintStream& out) +{ + ARMv7DOpcode armOpcode; + + uint16_t* currentPC = reinterpret_cast(reinterpret_cast(codePtr.executableAddress())&~1); + uint16_t* endPC = currentPC + (size / sizeof(uint16_t)); + + while (currentPC < endPC) { + char pcString[12]; + snprintf(pcString, sizeof(pcString), "0x%x", reinterpret_cast(currentPC)); + out.printf("%s%10s: %s\n", prefix, pcString, armOpcode.disassemble(currentPC)); + } + + return true; +} + +} // namespace JSC + +#endif // USE(ARMV7_DISASSEMBLER) + diff --git a/Source/JavaScriptCore/disassembler/Disassembler.cpp b/Source/JavaScriptCore/disassembler/Disassembler.cpp index a72e22a9e..788a6c362 100644 --- a/Source/JavaScriptCore/disassembler/Disassembler.cpp +++ b/Source/JavaScriptCore/disassembler/Disassembler.cpp @@ -1,5 +1,5 @@ /* - * Copyright (C) 2012, 2013 Apple Inc. All rights reserved. + * Copyright (C) 2012, 2013, 2015 Apple Inc. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -26,21 +26,126 @@ #include "config.h" #include "Disassembler.h" -#if ENABLE(DISASSEMBLER) - #include "MacroAssemblerCodeRef.h" +#include #include +#include +#include +#include +#include +#include namespace JSC { -void disassemble(const MacroAssemblerCodePtr& codePtr, size_t size, const char* prefix, PrintStream& out, InstructionSubsetHint subsetHint) +void disassemble(const MacroAssemblerCodePtr& codePtr, size_t size, const char* prefix, PrintStream& out) { - if (tryToDisassemble(codePtr, size, prefix, out, subsetHint)) + if (tryToDisassemble(codePtr, size, prefix, out)) return; out.printf("%sdisassembly not available for range %p...%p\n", prefix, codePtr.executableAddress(), static_cast(codePtr.executableAddress()) + size); } +namespace { + +// This is really a struct, except that it should be a class because that's what the WTF_* macros +// expect. +class DisassemblyTask { + WTF_MAKE_NONCOPYABLE(DisassemblyTask); + WTF_MAKE_FAST_ALLOCATED; +public: + DisassemblyTask() + { + } + + ~DisassemblyTask() + { + if (header) + free(header); // free() because it would have been copied by strdup. + } + + char* header { nullptr }; + MacroAssemblerCodeRef codeRef; + size_t size { 0 }; + const char* prefix { nullptr }; +}; + +class AsynchronousDisassembler { +public: + AsynchronousDisassembler() + { + createThread("Asynchronous Disassembler", [&] () { run(); }); + } + + void enqueue(std::unique_ptr task) + { + LockHolder locker(m_lock); + m_queue.append(WTFMove(task)); + m_condition.notifyAll(); + } + + void waitUntilEmpty() + { + LockHolder locker(m_lock); + while (!m_queue.isEmpty() || m_working) + m_condition.wait(m_lock); + } + +private: + NO_RETURN void run() + { + for (;;) { + std::unique_ptr task; + { + LockHolder locker(m_lock); + m_working = false; + m_condition.notifyAll(); + while (m_queue.isEmpty()) + m_condition.wait(m_lock); + task = m_queue.takeFirst(); + m_working = true; + } + + dataLog(task->header); + disassemble(task->codeRef.code(), task->size, task->prefix, WTF::dataFile()); + } + } + + Lock m_lock; + Condition m_condition; + Deque> m_queue; + bool m_working { false }; +}; + +bool hadAnyAsynchronousDisassembly = false; + +AsynchronousDisassembler& asynchronousDisassembler() +{ + static NeverDestroyed disassembler; + hadAnyAsynchronousDisassembly = true; + return disassembler.get(); +} + +} // anonymous namespace + +void disassembleAsynchronously( + const CString& header, const MacroAssemblerCodeRef& codeRef, size_t size, const char* prefix) +{ + std::unique_ptr task = std::make_unique(); + task->header = strdup(header.data()); // Yuck! We need this because CString does racy refcounting. + task->codeRef = codeRef; + task->size = size; + task->prefix = prefix; + + asynchronousDisassembler().enqueue(WTFMove(task)); +} + +void waitForAsynchronousDisassembly() +{ + if (!hadAnyAsynchronousDisassembly) + return; + + asynchronousDisassembler().waitUntilEmpty(); +} + } // namespace JSC -#endif // ENABLE(DISASSEMBLER) diff --git a/Source/JavaScriptCore/disassembler/Disassembler.h b/Source/JavaScriptCore/disassembler/Disassembler.h index 7088fc46a..ed47db89c 100644 --- a/Source/JavaScriptCore/disassembler/Disassembler.h +++ b/Source/JavaScriptCore/disassembler/Disassembler.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2012, 2013 Apple Inc. All rights reserved. + * Copyright (C) 2012, 2013, 2015 Apple Inc. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -26,19 +26,20 @@ #ifndef Disassembler_h #define Disassembler_h -#include +#include "JSExportMacros.h" +#include #include +#include namespace JSC { class MacroAssemblerCodePtr; - -enum InstructionSubsetHint { MacroAssemblerSubset, LLVMSubset }; +class MacroAssemblerCodeRef; #if ENABLE(DISASSEMBLER) -bool tryToDisassemble(const MacroAssemblerCodePtr&, size_t, const char* prefix, PrintStream&, InstructionSubsetHint = MacroAssemblerSubset); +bool tryToDisassemble(const MacroAssemblerCodePtr&, size_t, const char* prefix, PrintStream&); #else -inline bool tryToDisassemble(const MacroAssemblerCodePtr&, size_t, const char*, PrintStream&, InstructionSubsetHint = MacroAssemblerSubset) +inline bool tryToDisassemble(const MacroAssemblerCodePtr&, size_t, const char*, PrintStream&) { return false; } @@ -46,7 +47,14 @@ inline bool tryToDisassemble(const MacroAssemblerCodePtr&, size_t, const char*, // Prints either the disassembly, or a line of text indicating that disassembly failed and // the range of machine code addresses. -void disassemble(const MacroAssemblerCodePtr&, size_t, const char* prefix, PrintStream& out, InstructionSubsetHint = MacroAssemblerSubset); +void disassemble(const MacroAssemblerCodePtr&, size_t, const char* prefix, PrintStream& out); + +// Asynchronous disassembly. This happens on another thread, and calls the provided +// callback when the disassembly is done. +void disassembleAsynchronously( + const CString& header, const MacroAssemblerCodeRef&, size_t, const char* prefix); + +JS_EXPORT_PRIVATE void waitForAsynchronousDisassembly(); } // namespace JSC diff --git a/Source/JavaScriptCore/disassembler/LLVMDisassembler.cpp b/Source/JavaScriptCore/disassembler/LLVMDisassembler.cpp deleted file mode 100644 index a117bfa28..000000000 --- a/Source/JavaScriptCore/disassembler/LLVMDisassembler.cpp +++ /dev/null @@ -1,131 +0,0 @@ -/* - * Copyright (C) 2013 Apple Inc. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY APPLE INC. ``AS IS'' AND ANY - * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL APPLE INC. OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY - * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "config.h" -#include "LLVMDisassembler.h" - -#if USE(LLVM_DISASSEMBLER) - -#include "InitializeLLVM.h" -#include "LLVMAPI.h" -#include "MacroAssemblerCodeRef.h" - -namespace JSC { - -static const unsigned symbolStringSize = 40; - -static const char *symbolLookupCallback( - void* opaque, uint64_t referenceValue, uint64_t* referenceType, uint64_t referencePC, - const char** referenceName) -{ - // Set this if you want to debug an unexpected reference type. Currently we only encounter these - // if we try to disassemble garbage, since our code generator never uses them. These include things - // like PC-relative references. - static const bool crashOnUnexpected = false; - - char* symbolString = static_cast(opaque); - - switch (*referenceType) { - case LLVMDisassembler_ReferenceType_InOut_None: - return 0; - case LLVMDisassembler_ReferenceType_In_Branch: - *referenceName = 0; - *referenceType = LLVMDisassembler_ReferenceType_InOut_None; - snprintf( - symbolString, symbolStringSize, "0x%lx", - static_cast(referenceValue)); - return symbolString; - default: - if (crashOnUnexpected) { - dataLog("referenceValue = ", referenceValue, "\n"); - dataLog("referenceType = ", RawPointer(referenceType), ", *referenceType = ", *referenceType, "\n"); - dataLog("referencePC = ", referencePC, "\n"); - dataLog("referenceName = ", RawPointer(referenceName), "\n"); - - RELEASE_ASSERT_NOT_REACHED(); - } - - *referenceName = "unimplemented reference type!"; - *referenceType = LLVMDisassembler_ReferenceType_InOut_None; - snprintf( - symbolString, symbolStringSize, "unimplemented:0x%lx", - static_cast(referenceValue)); - return symbolString; - } -} - -bool tryToDisassembleWithLLVM( - const MacroAssemblerCodePtr& codePtr, size_t size, const char* prefix, PrintStream& out, - InstructionSubsetHint) -{ - initializeLLVM(); - - const char* triple; -#if CPU(X86_64) - triple = "x86_64-apple-darwin"; -#elif CPU(X86) - triple = "x86-apple-darwin"; -#else -#error "LLVM disassembler currently not supported on this CPU." -#endif - - char symbolString[symbolStringSize]; - - LLVMDisasmContextRef disassemblyContext = - llvm->CreateDisasm(triple, symbolString, 0, 0, symbolLookupCallback); - RELEASE_ASSERT(disassemblyContext); - - char pcString[20]; - char instructionString[1000]; - - uint8_t* pc = static_cast(codePtr.executableAddress()); - uint8_t* end = pc + size; - - while (pc < end) { - snprintf( - pcString, sizeof(pcString), "0x%lx", - static_cast(bitwise_cast(pc))); - - size_t instructionSize = llvm->DisasmInstruction( - disassemblyContext, pc, end - pc, bitwise_cast(pc), - instructionString, sizeof(instructionString)); - - if (!instructionSize) - snprintf(instructionString, sizeof(instructionString), ".byte 0x%02x", *pc++); - else - pc += instructionSize; - - out.printf("%s%16s: %s\n", prefix, pcString, instructionString); - } - - llvm->DisasmDispose(disassemblyContext); - - return true; -} - -} // namespace JSC - -#endif // USE(LLVM_DISASSEMBLER) - diff --git a/Source/JavaScriptCore/disassembler/LLVMDisassembler.h b/Source/JavaScriptCore/disassembler/LLVMDisassembler.h deleted file mode 100644 index 745912f27..000000000 --- a/Source/JavaScriptCore/disassembler/LLVMDisassembler.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Copyright (C) 2013 Apple Inc. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY APPLE INC. ``AS IS'' AND ANY - * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL APPLE INC. OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY - * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef LLVMDisassembler_h -#define LLVMDisassembler_h - -#include "Disassembler.h" - -namespace JSC { - -#if USE(LLVM_DISASSEMBLER) - -bool tryToDisassembleWithLLVM(const MacroAssemblerCodePtr& codePtr, size_t size, const char* prefix, PrintStream& out, InstructionSubsetHint); - -#else // USE(LLVM_DISASSEMBLER) - -inline bool tryToDisassembleWithLLVM(const MacroAssemblerCodePtr&, size_t, const char*, PrintStream&, InstructionSubsetHint) { return false; } - -#endif // USE(LLVM_DISASSEMBLER) - -} // namespace JSC - -#endif // LLVMDisassembler_h - diff --git a/Source/JavaScriptCore/disassembler/UDis86Disassembler.cpp b/Source/JavaScriptCore/disassembler/UDis86Disassembler.cpp new file mode 100644 index 000000000..4093f13e4 --- /dev/null +++ b/Source/JavaScriptCore/disassembler/UDis86Disassembler.cpp @@ -0,0 +1,63 @@ +/* + * Copyright (C) 2012, 2013, 2016 Apple Inc. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY APPLE INC. ``AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL APPLE INC. OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY + * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "config.h" +#include "UDis86Disassembler.h" + +#if USE(UDIS86) + +#include "MacroAssemblerCodeRef.h" +#include "udis86.h" + +namespace JSC { + +bool tryToDisassembleWithUDis86(const MacroAssemblerCodePtr& codePtr, size_t size, const char* prefix, PrintStream& out) +{ + ud_t disassembler; + ud_init(&disassembler); + ud_set_input_buffer(&disassembler, static_cast(codePtr.executableAddress()), size); +#if CPU(X86_64) + ud_set_mode(&disassembler, 64); +#else + ud_set_mode(&disassembler, 32); +#endif + ud_set_pc(&disassembler, bitwise_cast(codePtr.executableAddress())); + ud_set_syntax(&disassembler, UD_SYN_ATT); + + uint64_t currentPC = disassembler.pc; + while (ud_disassemble(&disassembler)) { + char pcString[20]; + snprintf(pcString, sizeof(pcString), "0x%lx", static_cast(currentPC)); + out.printf("%s%16s: %s\n", prefix, pcString, ud_insn_asm(&disassembler)); + currentPC = disassembler.pc; + } + + return true; +} + +} // namespace JSC + +#endif // USE(UDIS86) + diff --git a/Source/JavaScriptCore/disassembler/UDis86Disassembler.h b/Source/JavaScriptCore/disassembler/UDis86Disassembler.h new file mode 100644 index 000000000..2d5b3c44a --- /dev/null +++ b/Source/JavaScriptCore/disassembler/UDis86Disassembler.h @@ -0,0 +1,46 @@ +/* + * Copyright (C) 2013 Apple Inc. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY APPLE INC. ``AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL APPLE INC. OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY + * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef UDis86Disassembler_h +#define UDis86Disassembler_h + +#include "Disassembler.h" + +namespace JSC { + +#if USE(UDIS86) + +bool tryToDisassembleWithUDis86(const MacroAssemblerCodePtr& codePtr, size_t size, const char* prefix, PrintStream& out); + +#else // USE(UDIS86) + +inline bool tryToDisassembleWithUDis86(const MacroAssemblerCodePtr&, size_t, const char*, PrintStream&) { return false; } + +#endif // USE(UDIS86) + +} // namespace JSC + +#endif // UDis86Disassembler_h + diff --git a/Source/JavaScriptCore/disassembler/X86Disassembler.cpp b/Source/JavaScriptCore/disassembler/X86Disassembler.cpp index 5cce4a93f..1f811beca 100644 --- a/Source/JavaScriptCore/disassembler/X86Disassembler.cpp +++ b/Source/JavaScriptCore/disassembler/X86Disassembler.cpp @@ -1,5 +1,5 @@ /* - * Copyright (C) 2013 Apple Inc. All rights reserved. + * Copyright (C) 2013, 2014 Apple Inc. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -27,48 +27,20 @@ #include "Disassembler.h" #if ENABLE(DISASSEMBLER) -#if USE(UDIS86) || USE(LLVM_DISASSEMBLER) +#if USE(UDIS86) #include "MacroAssemblerCodeRef.h" #include "Options.h" #include "UDis86Disassembler.h" -#include "LLVMDisassembler.h" namespace JSC { -// This horrifying monster is needed because neither of our disassemblers supports -// all of x86, and using them together to disassemble the same instruction stream -// would result in a fairly jarring print-out since they print in different -// styles. Maybe we can do better in the future, but for now the caller hints -// whether he's using the subset of the architecture that our MacroAssembler -// supports (in which case we go with UDis86) or if he's using the LLVM subset. - -bool tryToDisassemble(const MacroAssemblerCodePtr& codePtr, size_t size, const char* prefix, PrintStream& out, InstructionSubsetHint subsetHint) +bool tryToDisassemble(const MacroAssemblerCodePtr& codePtr, size_t size, const char* prefix, PrintStream& out) { - if (Options::forceUDis86Disassembler()) - return tryToDisassembleWithUDis86(codePtr, size, prefix, out, subsetHint); - - if (Options::forceLLVMDisassembler()) - return tryToDisassembleWithLLVM(codePtr, size, prefix, out, subsetHint); - - if (subsetHint == MacroAssemblerSubset - && tryToDisassembleWithUDis86(codePtr, size, prefix, out, MacroAssemblerSubset)) - return true; - - if (subsetHint == LLVMSubset - && tryToDisassembleWithLLVM(codePtr, size, prefix, out, LLVMSubset)) - return true; - - if (tryToDisassembleWithUDis86(codePtr, size, prefix, out, subsetHint)) - return true; - if (tryToDisassembleWithLLVM(codePtr, size, prefix, out, subsetHint)) - return true; - - RELEASE_ASSERT_NOT_REACHED(); - return false; + return tryToDisassembleWithUDis86(codePtr, size, prefix, out); } } // namespace JSC -#endif // USE(UDIS86) || USE(LLVM_DISASSEMBLER) +#endif // USE(UDIS86) #endif // ENABLE(DISASSEMBLER) diff --git a/Source/JavaScriptCore/disassembler/udis86/differences.txt b/Source/JavaScriptCore/disassembler/udis86/differences.txt new file mode 100644 index 000000000..dc225b6ff --- /dev/null +++ b/Source/JavaScriptCore/disassembler/udis86/differences.txt @@ -0,0 +1,24 @@ +This documents the differences between the stock version of udis86 and the one found +here: + +- All files not named "udis86" were prefixed with "udis86". + +- assert() has been changed to ASSERT() + +- Mass rename of udis86_input.h inp_ prefixed functions and macros to ud_inp_ to + avoid namespace pollution. + +- Removal of KERNEL checks. + +- Added #include of udis86_extern.h in udis86_decode.c. + +- Removed s_ie__pause and s_ie__nop from udis86_decode.c, since they weren't used. + +- Made udis86_syn.h use WTF_ATTRIBUTE_PRINTF. This required making a bunch of little + fixes to make the compiler's format string warnings go away. + +- Made the code in udis86_syn.h use vsnprintf() instead of vsprintf(). + +- Fixed udis86_syn-att.c's jump destination printing to work correctly in 64-bit mode. + +- Add --outputDir option to itab.py. diff --git a/Source/JavaScriptCore/disassembler/udis86/itab.py b/Source/JavaScriptCore/disassembler/udis86/itab.py new file mode 100644 index 000000000..3d50ad061 --- /dev/null +++ b/Source/JavaScriptCore/disassembler/udis86/itab.py @@ -0,0 +1,360 @@ +# udis86 - scripts/itab.py +# +# Copyright (c) 2009 Vivek Thampi +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without modification, +# are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +# ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +from optparse import OptionParser +import os +import sys + +sys.path.append( '../scripts' ); + +import ud_optable +import ud_opcode + +class UdItabGenerator( ud_opcode.UdOpcodeTables ): + + OperandDict = { + "Ap" : [ "OP_A" , "SZ_P" ], + "E" : [ "OP_E" , "SZ_NA" ], + "Eb" : [ "OP_E" , "SZ_B" ], + "Ew" : [ "OP_E" , "SZ_W" ], + "Ev" : [ "OP_E" , "SZ_V" ], + "Ed" : [ "OP_E" , "SZ_D" ], + "Eq" : [ "OP_E" , "SZ_Q" ], + "Ez" : [ "OP_E" , "SZ_Z" ], + "Ex" : [ "OP_E" , "SZ_MDQ" ], + "Ep" : [ "OP_E" , "SZ_P" ], + "G" : [ "OP_G" , "SZ_NA" ], + "Gb" : [ "OP_G" , "SZ_B" ], + "Gw" : [ "OP_G" , "SZ_W" ], + "Gv" : [ "OP_G" , "SZ_V" ], + "Gy" : [ "OP_G" , "SZ_MDQ" ], + "Gy" : [ "OP_G" , "SZ_MDQ" ], + "Gd" : [ "OP_G" , "SZ_D" ], + "Gq" : [ "OP_G" , "SZ_Q" ], + "Gx" : [ "OP_G" , "SZ_MDQ" ], + "Gz" : [ "OP_G" , "SZ_Z" ], + "M" : [ "OP_M" , "SZ_NA" ], + "Mb" : [ "OP_M" , "SZ_B" ], + "Mw" : [ "OP_M" , "SZ_W" ], + "Ms" : [ "OP_M" , "SZ_W" ], + "Md" : [ "OP_M" , "SZ_D" ], + "Mq" : [ "OP_M" , "SZ_Q" ], + "Mt" : [ "OP_M" , "SZ_T" ], + "Mo" : [ "OP_M" , "SZ_O" ], + "MwRv" : [ "OP_MR" , "SZ_WV" ], + "MdRy" : [ "OP_MR" , "SZ_DY" ], + "MbRv" : [ "OP_MR" , "SZ_BV" ], + "I1" : [ "OP_I1" , "SZ_NA" ], + "I3" : [ "OP_I3" , "SZ_NA" ], + "Ib" : [ "OP_I" , "SZ_B" ], + "Isb" : [ "OP_I" , "SZ_SB" ], + "Iw" : [ "OP_I" , "SZ_W" ], + "Iv" : [ "OP_I" , "SZ_V" ], + "Iz" : [ "OP_I" , "SZ_Z" ], + "Jv" : [ "OP_J" , "SZ_V" ], + "Jz" : [ "OP_J" , "SZ_Z" ], + "Jb" : [ "OP_J" , "SZ_B" ], + "R" : [ "OP_R" , "SZ_RDQ" ], + "C" : [ "OP_C" , "SZ_NA" ], + "D" : [ "OP_D" , "SZ_NA" ], + "S" : [ "OP_S" , "SZ_NA" ], + "Ob" : [ "OP_O" , "SZ_B" ], + "Ow" : [ "OP_O" , "SZ_W" ], + "Ov" : [ "OP_O" , "SZ_V" ], + "V" : [ "OP_V" , "SZ_O" ], + "W" : [ "OP_W" , "SZ_O" ], + "Wsd" : [ "OP_W" , "SZ_O" ], + "Wss" : [ "OP_W" , "SZ_O" ], + "P" : [ "OP_P" , "SZ_Q" ], + "Q" : [ "OP_Q" , "SZ_Q" ], + "VR" : [ "OP_VR" , "SZ_O" ], + "PR" : [ "OP_PR" , "SZ_Q" ], + "AL" : [ "OP_AL" , "SZ_NA" ], + "CL" : [ "OP_CL" , "SZ_NA" ], + "DL" : [ "OP_DL" , "SZ_NA" ], + "BL" : [ "OP_BL" , "SZ_NA" ], + "AH" : [ "OP_AH" , "SZ_NA" ], + "CH" : [ "OP_CH" , "SZ_NA" ], + "DH" : [ "OP_DH" , "SZ_NA" ], + "BH" : [ "OP_BH" , "SZ_NA" ], + "AX" : [ "OP_AX" , "SZ_NA" ], + "CX" : [ "OP_CX" , "SZ_NA" ], + "DX" : [ "OP_DX" , "SZ_NA" ], + "BX" : [ "OP_BX" , "SZ_NA" ], + "SI" : [ "OP_SI" , "SZ_NA" ], + "DI" : [ "OP_DI" , "SZ_NA" ], + "SP" : [ "OP_SP" , "SZ_NA" ], + "BP" : [ "OP_BP" , "SZ_NA" ], + "eAX" : [ "OP_eAX" , "SZ_NA" ], + "eCX" : [ "OP_eCX" , "SZ_NA" ], + "eDX" : [ "OP_eDX" , "SZ_NA" ], + "eBX" : [ "OP_eBX" , "SZ_NA" ], + "eSI" : [ "OP_eSI" , "SZ_NA" ], + "eDI" : [ "OP_eDI" , "SZ_NA" ], + "eSP" : [ "OP_eSP" , "SZ_NA" ], + "eBP" : [ "OP_eBP" , "SZ_NA" ], + "rAX" : [ "OP_rAX" , "SZ_NA" ], + "rCX" : [ "OP_rCX" , "SZ_NA" ], + "rBX" : [ "OP_rBX" , "SZ_NA" ], + "rDX" : [ "OP_rDX" , "SZ_NA" ], + "rSI" : [ "OP_rSI" , "SZ_NA" ], + "rDI" : [ "OP_rDI" , "SZ_NA" ], + "rSP" : [ "OP_rSP" , "SZ_NA" ], + "rBP" : [ "OP_rBP" , "SZ_NA" ], + "ES" : [ "OP_ES" , "SZ_NA" ], + "CS" : [ "OP_CS" , "SZ_NA" ], + "DS" : [ "OP_DS" , "SZ_NA" ], + "SS" : [ "OP_SS" , "SZ_NA" ], + "GS" : [ "OP_GS" , "SZ_NA" ], + "FS" : [ "OP_FS" , "SZ_NA" ], + "ST0" : [ "OP_ST0" , "SZ_NA" ], + "ST1" : [ "OP_ST1" , "SZ_NA" ], + "ST2" : [ "OP_ST2" , "SZ_NA" ], + "ST3" : [ "OP_ST3" , "SZ_NA" ], + "ST4" : [ "OP_ST4" , "SZ_NA" ], + "ST5" : [ "OP_ST5" , "SZ_NA" ], + "ST6" : [ "OP_ST6" , "SZ_NA" ], + "ST7" : [ "OP_ST7" , "SZ_NA" ], + "NONE" : [ "OP_NONE" , "SZ_NA" ], + "ALr8b" : [ "OP_ALr8b" , "SZ_NA" ], + "CLr9b" : [ "OP_CLr9b" , "SZ_NA" ], + "DLr10b" : [ "OP_DLr10b" , "SZ_NA" ], + "BLr11b" : [ "OP_BLr11b" , "SZ_NA" ], + "AHr12b" : [ "OP_AHr12b" , "SZ_NA" ], + "CHr13b" : [ "OP_CHr13b" , "SZ_NA" ], + "DHr14b" : [ "OP_DHr14b" , "SZ_NA" ], + "BHr15b" : [ "OP_BHr15b" , "SZ_NA" ], + "rAXr8" : [ "OP_rAXr8" , "SZ_NA" ], + "rCXr9" : [ "OP_rCXr9" , "SZ_NA" ], + "rDXr10" : [ "OP_rDXr10" , "SZ_NA" ], + "rBXr11" : [ "OP_rBXr11" , "SZ_NA" ], + "rSPr12" : [ "OP_rSPr12" , "SZ_NA" ], + "rBPr13" : [ "OP_rBPr13" , "SZ_NA" ], + "rSIr14" : [ "OP_rSIr14" , "SZ_NA" ], + "rDIr15" : [ "OP_rDIr15" , "SZ_NA" ], + "jWP" : [ "OP_J" , "SZ_WP" ], + "jDP" : [ "OP_J" , "SZ_DP" ], + + } + + # + # opcode prefix dictionary + # + PrefixDict = { + "aso" : "P_aso", + "oso" : "P_oso", + "rexw" : "P_rexw", + "rexb" : "P_rexb", + "rexx" : "P_rexx", + "rexr" : "P_rexr", + "seg" : "P_seg", + "inv64" : "P_inv64", + "def64" : "P_def64", + "depM" : "P_depM", + "cast1" : "P_c1", + "cast2" : "P_c2", + "cast3" : "P_c3", + "cast" : "P_cast", + "sext" : "P_sext" + } + + InvalidEntryIdx = 0 + InvalidEntry = { 'type' : 'invalid', + 'mnemonic' : 'invalid', + 'operands' : '', + 'prefixes' : '', + 'meta' : '' } + + Itab = [] # instruction table + ItabIdx = 1 # instruction table index + GtabIdx = 0 # group table index + GtabMeta = [] + + ItabLookup = {} + + MnemonicAliases = ( "invalid", "3dnow", "none", "db", "pause" ) + + def __init__( self, outputDir ): + # first itab entry (0) is Invalid + self.Itab.append( self.InvalidEntry ) + self.MnemonicsTable.extend( self.MnemonicAliases ) + self.outputDir = outputDir + + def toGroupId( self, id ): + return 0x8000 | id + + def genLookupTable( self, table, scope = '' ): + idxArray = [ ] + ( tabIdx, self.GtabIdx ) = ( self.GtabIdx, self.GtabIdx + 1 ) + self.GtabMeta.append( { 'type' : table[ 'type' ], 'meta' : table[ 'meta' ] } ) + + for _idx in range( self.sizeOfTable( table[ 'type' ] ) ): + idx = "%02x" % _idx + + e = self.InvalidEntry + i = self.InvalidEntryIdx + + if idx in table[ 'entries' ].keys(): + e = table[ 'entries' ][ idx ] + + # leaf node (insn) + if e[ 'type' ] == 'insn': + ( i, self.ItabIdx ) = ( self.ItabIdx, self.ItabIdx + 1 ) + self.Itab.append( e ) + elif e[ 'type' ] != 'invalid': + i = self.genLookupTable( e, 'static' ) + + idxArray.append( i ) + + name = "ud_itab__%s" % tabIdx + self.ItabLookup[ tabIdx ] = name + + self.ItabC.write( "\n" ); + if len( scope ): + self.ItabC.write( scope + ' ' ) + self.ItabC.write( "const uint16_t %s[] = {\n" % name ) + for i in range( len( idxArray ) ): + if i > 0 and i % 4 == 0: + self.ItabC.write( "\n" ) + if ( i%4 == 0 ): + self.ItabC.write( " /* %2x */" % i) + if idxArray[ i ] >= 0x8000: + self.ItabC.write( "%12s," % ("GROUP(%d)" % ( ~0x8000 & idxArray[ i ] ))) + else: + self.ItabC.write( "%12d," % ( idxArray[ i ] )) + self.ItabC.write( "\n" ) + self.ItabC.write( "};\n" ) + + return self.toGroupId( tabIdx ) + + def genLookupTableList( self ): + self.ItabC.write( "\n\n" ); + self.ItabC.write( "struct ud_lookup_table_list_entry ud_lookup_table_list[] = {\n" ) + for i in range( len( self.GtabMeta ) ): + f0 = self.ItabLookup[ i ] + "," + f1 = ( self.nameOfTable( self.GtabMeta[ i ][ 'type' ] ) ) + "," + f2 = "\"%s\"" % self.GtabMeta[ i ][ 'meta' ] + self.ItabC.write( " /* %03d */ { %s %s %s },\n" % ( i, f0, f1, f2 ) ) + self.ItabC.write( "};" ) + + def genInsnTable( self ): + self.ItabC.write( "struct ud_itab_entry ud_itab[] = {\n" ); + idx = 0 + for e in self.Itab: + opr_c = [ "O_NONE", "O_NONE", "O_NONE" ] + pfx_c = [] + opr = e[ 'operands' ] + for i in range(len(opr)): + if not (opr[i] in self.OperandDict.keys()): + print("error: invalid operand declaration: %s\n" % opr[i]) + opr_c[i] = "O_" + opr[i] + opr = "%s %s %s" % (opr_c[0] + ",", opr_c[1] + ",", opr_c[2]) + + for p in e['prefixes']: + if not ( p in self.PrefixDict.keys() ): + print("error: invalid prefix specification: %s \n" % pfx) + pfx_c.append( self.PrefixDict[p] ) + if len(e['prefixes']) == 0: + pfx_c.append( "P_none" ) + pfx = "|".join( pfx_c ) + + self.ItabC.write( " /* %04d */ { UD_I%s %s, %s },\n" \ + % ( idx, e[ 'mnemonic' ] + ',', opr, pfx ) ) + idx += 1 + self.ItabC.write( "};\n" ) + + self.ItabC.write( "\n\n" ); + self.ItabC.write( "const char * ud_mnemonics_str[] = {\n" ) + self.ItabC.write( ",\n ".join( [ "\"%s\"" % m for m in self.MnemonicsTable ] ) ) + self.ItabC.write( "\n};\n" ) + + + def genItabH( self ): + self.ItabH = open( os.path.join(self.outputDir, "udis86_itab.h"), "w" ) + + # Generate Table Type Enumeration + self.ItabH.write( "#ifndef UD_ITAB_H\n" ) + self.ItabH.write( "#define UD_ITAB_H\n\n" ) + + # table type enumeration + self.ItabH.write( "/* ud_table_type -- lookup table types (see lookup.c) */\n" ) + self.ItabH.write( "enum ud_table_type {\n " ) + enum = [ self.TableInfo[ k ][ 'name' ] for k in self.TableInfo.keys() ] + self.ItabH.write( ",\n ".join( enum ) ) + self.ItabH.write( "\n};\n\n" ); + + # mnemonic enumeration + self.ItabH.write( "/* ud_mnemonic -- mnemonic constants */\n" ) + enum = "enum ud_mnemonic_code {\n " + enum += ",\n ".join( [ "UD_I%s" % m for m in self.MnemonicsTable ] ) + enum += "\n} UD_ATTR_PACKED;\n" + self.ItabH.write( enum ) + self.ItabH.write( "\n" ) + + self.ItabH.write("\n/* itab entry operand definitions */\n"); + operands = self.OperandDict.keys() + operands.sort() + for o in operands: + self.ItabH.write("#define O_%-7s { %-12s %-8s }\n" % + (o, self.OperandDict[o][0] + ",", self.OperandDict[o][1])); + self.ItabH.write("\n\n"); + + self.ItabH.write( "extern const char * ud_mnemonics_str[];\n" ) + + self.ItabH.write( "#define GROUP(n) (0x8000 | (n))" ) + + self.ItabH.write( "\n#endif /* UD_ITAB_H */\n" ) + + self.ItabH.close() + + + def genItabC( self ): + self.ItabC = open( os.path.join(self.outputDir, "udis86_itab.c"), "w" ) + self.ItabC.write( "/* itab.c -- generated by itab.py, do no edit" ) + self.ItabC.write( " */\n" ); + self.ItabC.write( "#include \"udis86_decode.h\"\n\n" ); + + self.genLookupTable( self.OpcodeTable0 ) + self.genLookupTableList() + self.genInsnTable() + + self.ItabC.close() + + def genItab( self ): + self.genItabC() + self.genItabH() + +def main(): + parser = OptionParser() + parser.add_option("--outputDir", dest="outputDir", default="") + options, args = parser.parse_args() + generator = UdItabGenerator(os.path.normpath(options.outputDir)) + optableXmlParser = ud_optable.UdOptableXmlParser() + optableXmlParser.parse( args[ 0 ], generator.addInsnDef ) + + generator.genItab() + +if __name__ == '__main__': + main() diff --git a/Source/JavaScriptCore/disassembler/udis86/optable.xml b/Source/JavaScriptCore/disassembler/udis86/optable.xml new file mode 100644 index 000000000..14b4ac593 --- /dev/null +++ b/Source/JavaScriptCore/disassembler/udis86/optable.xml @@ -0,0 +1,8959 @@ + + + + + + aaa + + 37 + inv64 + + + + + aad + + d5 + Ib + inv64 + + + + + aam + + d4 + Ib + inv64 + + + + + aas + + 3f + inv64 + + + + + adc + + aso rexr rexx rexb + 10 + Eb Gb + + + aso oso rexw rexr rexx rexb + 11 + Ev Gv + + + aso rexr rexx rexb + 12 + Gb Eb + + + aso oso rexw rexr rexx rexb + 13 + Gv Ev + + + 14 + AL Ib + + + oso rexw + 15 + rAX Iz + sext + + + aso rexr rexx rexb + 80 /reg=2 + Eb Ib + + + aso rexr rexx rexb + 82 /reg=2 + Eb Ib + inv64 + + + aso oso rexw rexr rexx rexb + 81 /reg=2 + Ev Iz + sext + + + aso oso rexw rexr rexx rexb + 83 /reg=2 + Ev Ib + sext + + + + + add + + aso rexr rexx rexb + 00 + Eb Gb + + + aso oso rexw rexr rexx rexb + 01 + Ev Gv + + + aso rexr rexx rexb + 02 + Gb Eb + + + aso oso rexw rexr rexx rexb + 03 + Gv Ev + + + 04 + AL Ib + + + oso rexw + 05 + rAX Iz + sext + + + aso rexr rexx rexb + 80 /reg=0 + Eb Ib + + + aso rexr rexx rexb + 82 /reg=0 + Eb Ib + inv64 + + + aso oso rexw rexr rexx rexb + 81 /reg=0 + Ev Iz + sext + + + aso oso rexw rexr rexx rexb + 83 /reg=0 + Ev Ib + sext + + + + + + + addpd + + aso rexr rexx rexb + sse66 0f 58 + V W + + + + + addps + + aso rexr rexx rexb + 0f 58 + V W + + + + + addsd + + aso rexr rexx rexb + ssef2 0f 58 + V W + + + + + addss + + aso rexr rexx rexb + ssef3 0f 58 + V W + + + + + and + + aso rexr rexx rexb + 20 + Eb Gb + + + aso oso rexw rexr rexx rexb + 21 + Ev Gv + + + aso rexr rexx rexb + 22 + Gb Eb + + + aso oso rexw rexr rexx rexb + 23 + Gv Ev + + + 24 + AL Ib + + + oso rexw + 25 + rAX Iz + sext + + + aso rexw rexr rexx rexb + 80 /reg=4 + Eb Ib + + + aso rexr rexx rexb + 82 /reg=4 + Eb Ib + inv64 + + + aso oso rexw rexr rexx rexb + 81 /reg=4 + Ev Iz + sext + + + aso oso rexw rexr rexx rexb + 83 /reg=4 + Ev Ib + sext + + + + + andpd + + aso rexr rexx rexb + sse66 0f 54 + V W + + + + + andps + + aso rexr rexx rexb + 0f 54 + V W + + + + + andnpd + + aso rexr rexx rexb + sse66 0f 55 + V W + + + + + andnps + + aso rexr rexx rexb + 0f 55 + V W + + + + + arpl + + aso + 63 /m=16 + Ew Gw + inv64 + + + aso + 63 /m=32 + Ew Gw + inv64 + + + + + movsxd + + aso oso rexw rexx rexr rexb + 63 /m=64 + Gv Ed + + + + + bound + + aso oso + 62 + Gv M + inv64 + + + + + bsf + + aso oso rexw rexr rexx rexb + 0f bc + Gv Ev + + + + + bsr + + aso oso rexw rexr rexx rexb + 0f bd + Gv Ev + + + + + bswap + + oso rexw rexb + 0f c8 + rAXr8 + + + oso rexw rexb + 0f c9 + rCXr9 + + + oso rexw rexb + 0f ca + rDXr10 + + + oso rexw rexb + 0f cb + rBXr11 + + + oso rexw rexb + 0f cc + rSPr12 + + + oso rexw rexb + 0f cd + rBPr13 + + + oso rexw rexb + 0f ce + rSIr14 + + + oso rexw rexb + 0f cf + rDIr15 + + + + + bt + + aso oso rexw rexr rexx rexb + 0f ba /reg=4 + Ev Ib + + + aso oso rexw rexr rexx rexb + 0f a3 + Ev Gv + + + + + btc + + aso oso rexw rexr rexx rexb + 0f bb + Ev Gv + + + aso oso rexw rexr rexx rexb + 0f ba /reg=7 + Ev Ib + + + + + btr + + aso oso rexw rexr rexx rexb + 0f b3 + Ev Gv + + + aso oso rexw rexr rexx rexb + 0f ba /reg=6 + Ev Ib + + + + + bts + + aso oso rexw rexr rexx rexb + 0f ab + Ev Gv + + + aso oso rexw rexr rexx rexb + 0f ba /reg=5 + Ev Ib + + + + + call + + aso oso rexw rexr rexx rexb + ff /reg=2 + Ev + def64 + + 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rexx rexb + ssef2 0f 12 /mod=11 + V W + + + aso rexr rexx rexb + ssef2 0f 12 /mod=!11 + V W + + + + + movshdup + + aso rexr rexx rexb + ssef3 0f 16 /mod=11 + V W + + + aso rexr rexx rexb + ssef3 0f 16 /mod=!11 + V W + + + + + movsldup + + aso rexr rexx rexb + ssef3 0f 12 /mod=11 + V W + + + aso rexr rexx rexb + ssef3 0f 12 /mod=!11 + V W + + + + + + + pabsb + + aso rexr rexx rexb + 0f 38 1c + P Q + + + aso rexr rexx rexb + sse66 0f 38 1c + V W + + + + + pabsw + + aso rexr rexx rexb + 0f 38 1d + P Q + + + aso rexr rexx rexb + sse66 0f 38 1d + V W + + + + + pabsd + + aso rexr rexx rexb + 0f 38 1e + P Q + + + aso rexr rexx rexb + sse66 0f 38 1e + V W + + + + + psignb + + aso rexr rexx rexb + 0f 38 00 + P Q + + + aso rexr rexx rexb + sse66 0f 38 00 + V W + + + + + phaddw + + aso rexr rexx rexb + 0f 38 01 + P Q + + + aso rexr rexx rexb + sse66 0f 38 01 + V W + + + + + phaddd + + aso rexr rexx rexb + 0f 38 02 + P Q + + + aso rexr rexx rexb + sse66 0f 38 02 + V W + + + + + phaddsw + + aso rexr rexx rexb + 0f 38 03 + P Q + + + aso rexr rexx rexb + sse66 0f 38 03 + V W + + + + + pmaddubsw + + aso rexr rexx rexb + 0f 38 04 + P Q + + + aso rexr rexx rexb + sse66 0f 38 04 + V W + + + + + phsubw + + aso rexr rexx rexb + 0f 38 05 + P Q + + + aso rexr rexx rexb + sse66 0f 38 05 + V W + + + + + phsubd + + aso rexr rexx rexb + 0f 38 06 + P Q + + + aso rexr rexx rexb + sse66 0f 38 06 + V W + + + + + phsubsw + + aso rexr rexx rexb + 0f 38 07 + P Q + + + aso rexr rexx rexb + sse66 0f 38 07 + V W + + + + + psignb + + aso rexr rexx rexb + 0f 38 08 + P Q + + + aso rexr rexx rexb + sse66 0f 38 08 + V W + + + + + psignd + + aso rexr rexx rexb + 0f 38 0a + P Q + + + aso rexr rexx rexb + sse66 0f 38 0a + V W + + + + + psignw + + aso rexr rexx rexb + 0f 38 09 + P Q + + + aso rexr rexx rexb + sse66 0f 38 09 + V W + + + + + pmulhrsw + + aso rexr rexx rexb + 0f 38 0b + P Q + + + aso rexr rexx rexb + sse66 0f 38 0b + V W + + + + + palignr + + aso rexr rexx rexb + 0f 3a 0f + P Q Ib + + + aso rexr rexx rexb + sse66 0f 3a 0f + V W Ib + + + + + + + pblendvb + + aso rexr rexx rexb + sse66 0f 38 10 + V W + + + + + pmuldq + + aso rexr rexx rexb + sse66 0f 38 28 + V W + + + + + pminsb + + aso rexr rexx rexb + sse66 0f 38 38 + V W + + + + + pminsd + + aso rexr rexx rexb + sse66 0f 38 39 + V W + + + + + pminuw + + aso rexr rexx rexb + sse66 0f 38 3a + V W + + + + + pminud + + aso rexr rexx rexb + sse66 0f 38 3b + V W + + + + + pmaxsb + + aso rexr rexx rexb + sse66 0f 38 3c + V W + + + + + pmaxsd + + aso rexr rexx rexb + sse66 0f 38 3d + V W + + + + + pmaxud + + aso rexr rexx rexb + sse66 0f 38 3f + V W + + + + + pmulld + + aso rexr rexx rexb + sse66 0f 38 40 + V W + + + + + phminposuw + + aso rexr rexx rexb + sse66 0f 38 41 + V W + + + + + roundps + + aso rexr rexx rexb + sse66 0f 3a 08 + V W Ib + + + + + roundpd + + aso rexr rexx rexb + sse66 0f 3a 09 + V W Ib + + + + + roundss + + aso rexr rexx rexb + sse66 0f 3a 0a + V W Ib + + + + + roundsd + + aso rexr rexx rexb + sse66 0f 3a 0b + V W Ib + + + + + blendpd + + aso rexr rexx rexb + sse66 0f 3a 0d + V W Ib + + + + + pblendw + + aso rexr rexx rexb + sse66 0f 3a 0e + V W Ib + + + + + blendps + + aso rexr rexx rexb + sse66 0f 3a 0c + V W Ib + + + + + blendvpd + + aso rexr rexx rexb + sse66 0f 38 15 + V W + + + + + blendvps + + aso rexr rexx rexb + sse66 0f 38 14 + V W + + + + + dpps + + aso rexr rexx rexb + sse66 0f 3a 40 + V W Ib + + + + + dppd + + aso rexr rexx rexb + sse66 0f 3a 41 + V W Ib + + + + + mpsadbw + + aso rexr rexx rexb + sse66 0f 3a 42 + V W Ib + + + + + extractps + + aso rexr rexw rexb + sse66 0f 3a 17 + MdRy V Ib + + + + + invalid + + + diff --git a/Source/JavaScriptCore/disassembler/udis86/ud_opcode.py b/Source/JavaScriptCore/disassembler/udis86/ud_opcode.py new file mode 100644 index 000000000..f82738062 --- /dev/null +++ b/Source/JavaScriptCore/disassembler/udis86/ud_opcode.py @@ -0,0 +1,235 @@ +# udis86 - scripts/ud_opcode.py +# +# Copyright (c) 2009 Vivek Thampi +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without modification, +# are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +# ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +class UdOpcodeTables: + + TableInfo = { + 'opctbl' : { 'name' : 'UD_TAB__OPC_TABLE', 'size' : 256 }, + '/sse' : { 'name' : 'UD_TAB__OPC_SSE', 'size' : 4 }, + '/reg' : { 'name' : 'UD_TAB__OPC_REG', 'size' : 8 }, + '/rm' : { 'name' : 'UD_TAB__OPC_RM', 'size' : 8 }, + '/mod' : { 'name' : 'UD_TAB__OPC_MOD', 'size' : 2 }, + '/m' : { 'name' : 'UD_TAB__OPC_MODE', 'size' : 3 }, + '/x87' : { 'name' : 'UD_TAB__OPC_X87', 'size' : 64 }, + '/a' : { 'name' : 'UD_TAB__OPC_ASIZE', 'size' : 3 }, + '/o' : { 'name' : 'UD_TAB__OPC_OSIZE', 'size' : 3 }, + '/3dnow' : { 'name' : 'UD_TAB__OPC_3DNOW', 'size' : 256 }, + 'vendor' : { 'name' : 'UD_TAB__OPC_VENDOR', 'size' : 3 }, + } + + OpcodeTable0 = { + 'type' : 'opctbl', + 'entries' : {}, + 'meta' : 'table0' + } + + OpcExtIndex = { + + # ssef2, ssef3, sse66 + 'sse': { + 'none' : '00', + 'f2' : '01', + 'f3' : '02', + '66' : '03' + }, + + # /mod= + 'mod': { + '!11' : '00', + '11' : '01' + }, + + # /m=, /o=, /a= + 'mode': { + '16' : '00', + '32' : '01', + '64' : '02' + }, + + 'vendor' : { + 'amd' : '00', + 'intel' : '01', + 'any' : '02' + } + } + + InsnTable = [] + MnemonicsTable = [] + + ThreeDNowTable = {} + + def sizeOfTable( self, t ): + return self.TableInfo[ t ][ 'size' ] + + def nameOfTable( self, t ): + return self.TableInfo[ t ][ 'name' ] + + # + # Updates a table entry: If the entry doesn't exist + # it will create the entry, otherwise, it will walk + # while validating the path. + # + def updateTable( self, table, index, type, meta ): + if not index in table[ 'entries' ]: + table[ 'entries' ][ index ] = { 'type' : type, 'entries' : {}, 'meta' : meta } + if table[ 'entries' ][ index ][ 'type' ] != type: + raise NameError( "error: violation in opcode mapping (overwrite) %s with %s." % + ( table[ 'entries' ][ index ][ 'type' ], type) ) + return table[ 'entries' ][ index ] + + class Insn: + """An abstract type representing an instruction in the opcode map. + """ + + # A mapping of opcode extensions to their representational + # values used in the opcode map. + OpcExtMap = { + '/rm' : lambda v: "%02x" % int(v, 16), + '/x87' : lambda v: "%02x" % int(v, 16), + '/3dnow' : lambda v: "%02x" % int(v, 16), + '/reg' : lambda v: "%02x" % int(v, 16), + # modrm.mod + # (!11, 11) => (00, 01) + '/mod' : lambda v: '00' if v == '!11' else '01', + # Mode extensions: + # (16, 32, 64) => (00, 01, 02) + '/o' : lambda v: "%02x" % (int(v) / 32), + '/a' : lambda v: "%02x" % (int(v) / 32), + '/m' : lambda v: "%02x" % (int(v) / 32), + '/sse' : lambda v: UdOpcodeTables.OpcExtIndex['sse'][v] + } + + def __init__(self, prefixes, mnemonic, opcodes, operands, vendor): + self.opcodes = opcodes + self.prefixes = prefixes + self.mnemonic = mnemonic + self.operands = operands + self.vendor = vendor + self.opcext = {} + + ssePrefix = None + if self.opcodes[0] in ('ssef2', 'ssef3', 'sse66'): + ssePrefix = self.opcodes[0][3:] + self.opcodes.pop(0) + + # do some preliminary decoding of the instruction type + # 1byte, 2byte or 3byte instruction? + self.nByteInsn = 1 + if self.opcodes[0] == '0f': # 2byte + # 2+ byte opcodes are always disambiguated by an + # sse prefix, unless it is a 3d now instruction + # which is 0f 0f ... + if self.opcodes[1] != '0f' and ssePrefix is None: + ssePrefix = 'none' + if self.opcodes[1] in ('38', '3a'): # 3byte + self.nByteInsn = 3 + else: + self.nByteInsn = 2 + + # The opcode that indexes into the opcode table. + self.opcode = self.opcodes[self.nByteInsn - 1] + + # Record opcode extensions + for opcode in self.opcodes[self.nByteInsn:]: + arg, val = opcode.split('=') + self.opcext[arg] = self.OpcExtMap[arg](val) + + # Record sse extension: the reason sse extension is handled + # separately is that historically sse was handled as a first + # class opcode, not as an extension. Now that sse is handled + # as an extension, we do the manual conversion here, as opposed + # to modifying the opcode xml file. + if ssePrefix is not None: + self.opcext['/sse'] = self.OpcExtMap['/sse'](ssePrefix) + + def parse(self, table, insn): + index = insn.opcodes[0]; + if insn.nByteInsn > 1: + assert index == '0f' + table = self.updateTable(table, index, 'opctbl', '0f') + index = insn.opcodes[1] + + if insn.nByteInsn == 3: + table = self.updateTable(table, index, 'opctbl', index) + index = insn.opcodes[2] + + # Walk down the tree, create levels as needed, for opcode + # extensions. The order is important, and determines how + # well the opcode table is packed. Also note, /sse must be + # before /o, because /sse may consume operand size prefix + # affect the outcome of /o. + for ext in ('/mod', '/x87', '/reg', '/rm', '/sse', + '/o', '/a', '/m', '/3dnow'): + if ext in insn.opcext: + table = self.updateTable(table, index, ext, ext) + index = insn.opcext[ext] + + # additional table for disambiguating vendor + if len(insn.vendor): + table = self.updateTable(table, index, 'vendor', insn.vendor) + index = self.OpcExtIndex['vendor'][insn.vendor] + + # make leaf node entries + leaf = self.updateTable(table, index, 'insn', '') + + leaf['mnemonic'] = insn.mnemonic + leaf['prefixes'] = insn.prefixes + leaf['operands'] = insn.operands + + # add instruction to linear table of instruction forms + self.InsnTable.append({ 'prefixes' : insn.prefixes, + 'mnemonic' : insn.mnemonic, + 'operands' : insn.operands }) + + # add mnemonic to mnemonic table + if not insn.mnemonic in self.MnemonicsTable: + self.MnemonicsTable.append(insn.mnemonic) + + + # Adds an instruction definition to the opcode tables + def addInsnDef( self, prefixes, mnemonic, opcodes, operands, vendor ): + insn = self.Insn(prefixes=prefixes, + mnemonic=mnemonic, + opcodes=opcodes, + operands=operands, + vendor=vendor) + self.parse(self.OpcodeTable0, insn) + + def print_table( self, table, pfxs ): + print("%s |" % pfxs) + keys = table[ 'entries' ].keys() + if ( len( keys ) ): + keys.sort() + for idx in keys: + e = table[ 'entries' ][ idx ] + if e[ 'type' ] == 'insn': + print("%s |-<%s>" % ( pfxs, idx )), + print("%s %s" % ( e[ 'mnemonic' ], ' '.join( e[ 'operands'] ))) + else: + print("%s |-<%s> %s" % ( pfxs, idx, e['type'] )) + self.print_table( e, pfxs + ' |' ) + + def print_tree( self ): + self.print_table( self.OpcodeTable0, '' ) diff --git a/Source/JavaScriptCore/disassembler/udis86/ud_optable.py b/Source/JavaScriptCore/disassembler/udis86/ud_optable.py new file mode 100644 index 000000000..0350643fd --- /dev/null +++ b/Source/JavaScriptCore/disassembler/udis86/ud_optable.py @@ -0,0 +1,103 @@ +# udis86 - scripts/ud_optable.py (optable.xml parser) +# +# Copyright (c) 2009 Vivek Thampi +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without modification, +# are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +# ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +import os +import sys +from xml.dom import minidom + +class UdOptableXmlParser: + + def parseDef( self, node ): + ven = '' + pfx = [] + opc = [] + opr = [] + for def_node in node.childNodes: + if not def_node.localName: + continue + if def_node.localName == 'pfx': + pfx = def_node.firstChild.data.split(); + elif def_node.localName == 'opc': + opc = def_node.firstChild.data.split(); + elif def_node.localName == 'opr': + opr = def_node.firstChild.data.split(); + elif def_node.localName == 'mode': + pfx.extend( def_node.firstChild.data.split() ); + elif def_node.localName == 'syn': + pfx.extend( def_node.firstChild.data.split() ); + elif def_node.localName == 'vendor': + ven = ( def_node.firstChild.data ); + else: + print("warning: invalid node - %s" % def_node.localName) + continue + return ( pfx, opc, opr, ven ) + + def parse( self, xml, fn ): + xmlDoc = minidom.parse( xml ) + self.TlNode = xmlDoc.firstChild + + while self.TlNode and self.TlNode.localName != "x86optable": + self.TlNode = self.TlNode.nextSibling + + for insnNode in self.TlNode.childNodes: + if not insnNode.localName: + continue + if insnNode.localName != "instruction": + print("warning: invalid insn node - %s" % insnNode.localName) + continue + + mnemonic = insnNode.getElementsByTagName( 'mnemonic' )[ 0 ].firstChild.data + vendor = '' + + for node in insnNode.childNodes: + if node.localName == 'vendor': + vendor = node.firstChild.data + elif node.localName == 'def': + ( prefixes, opcodes, operands, local_vendor ) = \ + self.parseDef( node ) + if ( len( local_vendor ) ): + vendor = local_vendor + # callback + fn( prefixes, mnemonic, opcodes, operands, vendor ) + + +def printFn( pfx, mnm, opc, opr, ven ): + print('def: '), + if len( pfx ): + print(' '.join( pfx )), + print("%s %s %s %s" % \ + ( mnm, ' '.join( opc ), ' '.join( opr ), ven )) + + +def parse( xml, callback ): + parser = UdOptableXmlParser() + parser.parse( xml, callback ) + +def main(): + parser = UdOptableXmlParser() + parser.parse( sys.argv[ 1 ], printFn ) + +if __name__ == "__main__": + main() diff --git a/Source/JavaScriptCore/disassembler/udis86/udis86.c b/Source/JavaScriptCore/disassembler/udis86/udis86.c new file mode 100644 index 000000000..264103423 --- /dev/null +++ b/Source/JavaScriptCore/disassembler/udis86/udis86.c @@ -0,0 +1,182 @@ +/* udis86 - libudis86/udis86.c + * + * Copyright (c) 2002-2009 Vivek Thampi + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "config.h" + +#if USE(UDIS86) + +#include "udis86_input.h" +#include "udis86_extern.h" + +#ifndef __UD_STANDALONE__ +# include +# include +#endif /* __UD_STANDALONE__ */ + +/* ============================================================================= + * ud_init() - Initializes ud_t object. + * ============================================================================= + */ +extern void +ud_init(struct ud* u) +{ + memset((void*)u, 0, sizeof(struct ud)); + ud_set_mode(u, 16); + u->mnemonic = UD_Iinvalid; + ud_set_pc(u, 0); +#ifndef __UD_STANDALONE__ + ud_set_input_file(u, stdin); +#endif /* __UD_STANDALONE__ */ +} + +/* ============================================================================= + * ud_disassemble() - disassembles one instruction and returns the number of + * bytes disassembled. A zero means end of disassembly. + * ============================================================================= + */ +extern unsigned int +ud_disassemble(struct ud* u) +{ + if (ud_input_end(u)) + return 0; + + + u->insn_buffer[0] = u->insn_hexcode[0] = 0; + + + if (ud_decode(u) == 0) + return 0; + if (u->translator) + u->translator(u); + return ud_insn_len(u); +} + +/* ============================================================================= + * ud_set_mode() - Set Disassemly Mode. + * ============================================================================= + */ +extern void +ud_set_mode(struct ud* u, uint8_t m) +{ + switch(m) { + case 16: + case 32: + case 64: u->dis_mode = m ; return; + default: u->dis_mode = 16; return; + } +} + +/* ============================================================================= + * ud_set_vendor() - Set vendor. + * ============================================================================= + */ +extern void +ud_set_vendor(struct ud* u, unsigned v) +{ + switch(v) { + case UD_VENDOR_INTEL: + u->vendor = v; + break; + case UD_VENDOR_ANY: + u->vendor = v; + break; + default: + u->vendor = UD_VENDOR_AMD; + } +} + +/* ============================================================================= + * ud_set_pc() - Sets code origin. + * ============================================================================= + */ +extern void +ud_set_pc(struct ud* u, uint64_t o) +{ + u->pc = o; +} + +/* ============================================================================= + * ud_set_syntax() - Sets the output syntax. + * ============================================================================= + */ +extern void +ud_set_syntax(struct ud* u, void (*t)(struct ud*)) +{ + u->translator = t; +} + +/* ============================================================================= + * ud_insn() - returns the disassembled instruction + * ============================================================================= + */ +extern char* +ud_insn_asm(struct ud* u) +{ + return u->insn_buffer; +} + +/* ============================================================================= + * ud_insn_offset() - Returns the offset. + * ============================================================================= + */ +extern uint64_t +ud_insn_off(struct ud* u) +{ + return u->insn_offset; +} + + +/* ============================================================================= + * ud_insn_hex() - Returns hex form of disassembled instruction. + * ============================================================================= + */ +extern char* +ud_insn_hex(struct ud* u) +{ + return u->insn_hexcode; +} + +/* ============================================================================= + * ud_insn_ptr() - Returns code disassembled. + * ============================================================================= + */ +extern uint8_t* +ud_insn_ptr(struct ud* u) +{ + return u->inp_sess; +} + +/* ============================================================================= + * ud_insn_len() - Returns the count of bytes disassembled. + * ============================================================================= + */ +extern unsigned int +ud_insn_len(struct ud* u) +{ + return u->inp_ctr; +} + +#endif // USE(UDIS86) diff --git a/Source/JavaScriptCore/disassembler/udis86/udis86.h b/Source/JavaScriptCore/disassembler/udis86/udis86.h new file mode 100644 index 000000000..baaf495e0 --- /dev/null +++ b/Source/JavaScriptCore/disassembler/udis86/udis86.h @@ -0,0 +1,33 @@ +/* udis86 - udis86.h + * + * Copyright (c) 2002-2009 Vivek Thampi + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef UDIS86_H +#define UDIS86_H + +#include "udis86_types.h" +#include "udis86_extern.h" +#include "udis86_itab.h" + +#endif diff --git a/Source/JavaScriptCore/disassembler/udis86/udis86_decode.c b/Source/JavaScriptCore/disassembler/udis86/udis86_decode.c new file mode 100644 index 000000000..579903642 --- /dev/null +++ b/Source/JavaScriptCore/disassembler/udis86/udis86_decode.c @@ -0,0 +1,1142 @@ +/* udis86 - libudis86/decode.c + * + * Copyright (c) 2002-2009 Vivek Thampi + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "config.h" + +#if USE(UDIS86) + +#include "udis86_extern.h" +#include "udis86_types.h" +#include "udis86_input.h" +#include "udis86_decode.h" +#include + +#define dbg(x, n...) +/* #define dbg printf */ + +#ifndef __UD_STANDALONE__ +# include +#endif /* __UD_STANDALONE__ */ + +/* The max number of prefixes to an instruction */ +#define MAX_PREFIXES 15 + +/* instruction aliases and special cases */ +static struct ud_itab_entry s_ie__invalid = + { UD_Iinvalid, O_NONE, O_NONE, O_NONE, P_none }; + +static int +decode_ext(struct ud *u, uint16_t ptr); + + +static inline int +eff_opr_mode(int dis_mode, int rex_w, int pfx_opr) +{ + if (dis_mode == 64) { + return rex_w ? 64 : (pfx_opr ? 16 : 32); + } else if (dis_mode == 32) { + return pfx_opr ? 16 : 32; + } else { + ASSERT(dis_mode == 16); + return pfx_opr ? 32 : 16; + } +} + + +static inline int +eff_adr_mode(int dis_mode, int pfx_adr) +{ + if (dis_mode == 64) { + return pfx_adr ? 32 : 64; + } else if (dis_mode == 32) { + return pfx_adr ? 16 : 32; + } else { + ASSERT(dis_mode == 16); + return pfx_adr ? 32 : 16; + } +} + + +/* Looks up mnemonic code in the mnemonic string table + * Returns NULL if the mnemonic code is invalid + */ +const char * ud_lookup_mnemonic( enum ud_mnemonic_code c ) +{ + return ud_mnemonics_str[ c ]; +} + + +/* + * decode_prefixes + * + * Extracts instruction prefixes. + */ +static int +decode_prefixes(struct ud *u) +{ + unsigned int have_pfx = 1; + unsigned int i; + uint8_t curr; + + /* if in error state, bail out */ + if ( u->error ) + return -1; + + /* keep going as long as there are prefixes available */ + for ( i = 0; have_pfx ; ++i ) { + + /* Get next byte. */ + ud_inp_next(u); + if ( u->error ) + return -1; + curr = ud_inp_curr( u ); + + /* rex prefixes in 64bit mode */ + if ( u->dis_mode == 64 && ( curr & 0xF0 ) == 0x40 ) { + u->pfx_rex = curr; + } else { + switch ( curr ) + { + case 0x2E : + u->pfx_seg = UD_R_CS; + u->pfx_rex = 0; + break; + case 0x36 : + u->pfx_seg = UD_R_SS; + u->pfx_rex = 0; + break; + case 0x3E : + u->pfx_seg = UD_R_DS; + u->pfx_rex = 0; + break; + case 0x26 : + u->pfx_seg = UD_R_ES; + u->pfx_rex = 0; + break; + case 0x64 : + u->pfx_seg = UD_R_FS; + u->pfx_rex = 0; + break; + case 0x65 : + u->pfx_seg = UD_R_GS; + u->pfx_rex = 0; + break; + case 0x67 : /* adress-size override prefix */ + u->pfx_adr = 0x67; + u->pfx_rex = 0; + break; + case 0xF0 : + u->pfx_lock = 0xF0; + u->pfx_rex = 0; + break; + case 0x66: + /* the 0x66 sse prefix is only effective if no other sse prefix + * has already been specified. + */ + if ( !u->pfx_insn ) u->pfx_insn = 0x66; + u->pfx_opr = 0x66; + u->pfx_rex = 0; + break; + case 0xF2: + u->pfx_insn = 0xF2; + u->pfx_repne = 0xF2; + u->pfx_rex = 0; + break; + case 0xF3: + u->pfx_insn = 0xF3; + u->pfx_rep = 0xF3; + u->pfx_repe = 0xF3; + u->pfx_rex = 0; + break; + default : + /* No more prefixes */ + have_pfx = 0; + break; + } + } + + /* check if we reached max instruction length */ + if ( i + 1 == MAX_INSN_LENGTH ) { + u->error = 1; + break; + } + } + + /* return status */ + if ( u->error ) + return -1; + + /* rewind back one byte in stream, since the above loop + * stops with a non-prefix byte. + */ + ud_inp_back(u); + return 0; +} + + +static inline unsigned int modrm( struct ud * u ) +{ + if ( !u->have_modrm ) { + u->modrm = ud_inp_next( u ); + u->have_modrm = 1; + } + return u->modrm; +} + + +static unsigned int resolve_operand_size( const struct ud * u, unsigned int s ) +{ + switch ( s ) + { + case SZ_V: + return ( u->opr_mode ); + case SZ_Z: + return ( u->opr_mode == 16 ) ? 16 : 32; + case SZ_P: + return ( u->opr_mode == 16 ) ? SZ_WP : SZ_DP; + case SZ_MDQ: + return ( u->opr_mode == 16 ) ? 32 : u->opr_mode; + case SZ_RDQ: + return ( u->dis_mode == 64 ) ? 64 : 32; + default: + return s; + } +} + + +static int resolve_mnemonic( struct ud* u ) +{ + /* far/near flags */ + u->br_far = 0; + u->br_near = 0; + /* readjust operand sizes for call/jmp instrcutions */ + if ( u->mnemonic == UD_Icall || u->mnemonic == UD_Ijmp ) { + /* WP: 16:16 pointer */ + if ( u->operand[ 0 ].size == SZ_WP ) { + u->operand[ 0 ].size = 16; + u->br_far = 1; + u->br_near= 0; + /* DP: 32:32 pointer */ + } else if ( u->operand[ 0 ].size == SZ_DP ) { + u->operand[ 0 ].size = 32; + u->br_far = 1; + u->br_near= 0; + } else { + u->br_far = 0; + u->br_near= 1; + } + /* resolve 3dnow weirdness. */ + } else if ( u->mnemonic == UD_I3dnow ) { + u->mnemonic = ud_itab[ u->le->table[ ud_inp_curr( u ) ] ].mnemonic; + } + /* SWAPGS is only valid in 64bits mode */ + if ( u->mnemonic == UD_Iswapgs && u->dis_mode != 64 ) { + u->error = 1; + return -1; + } + + if (u->mnemonic == UD_Ixchg) { + if ((u->operand[0].type == UD_OP_REG && u->operand[0].base == UD_R_AX && + u->operand[1].type == UD_OP_REG && u->operand[1].base == UD_R_AX) || + (u->operand[0].type == UD_OP_REG && u->operand[0].base == UD_R_EAX && + u->operand[1].type == UD_OP_REG && u->operand[1].base == UD_R_EAX)) { + u->operand[0].type = UD_NONE; + u->operand[1].type = UD_NONE; + u->mnemonic = UD_Inop; + } + } + + if (u->mnemonic == UD_Inop && u->pfx_rep) { + u->pfx_rep = 0; + u->mnemonic = UD_Ipause; + } + return 0; +} + + +/* ----------------------------------------------------------------------------- + * decode_a()- Decodes operands of the type seg:offset + * ----------------------------------------------------------------------------- + */ +static void +decode_a(struct ud* u, struct ud_operand *op) +{ + if (u->opr_mode == 16) { + /* seg16:off16 */ + op->type = UD_OP_PTR; + op->size = 32; + op->lval.ptr.off = ud_inp_uint16(u); + op->lval.ptr.seg = ud_inp_uint16(u); + } else { + /* seg16:off32 */ + op->type = UD_OP_PTR; + op->size = 48; + op->lval.ptr.off = ud_inp_uint32(u); + op->lval.ptr.seg = ud_inp_uint16(u); + } +} + +/* ----------------------------------------------------------------------------- + * decode_gpr() - Returns decoded General Purpose Register + * ----------------------------------------------------------------------------- + */ +static enum ud_type +decode_gpr(register struct ud* u, unsigned int s, unsigned char rm) +{ + s = resolve_operand_size(u, s); + + switch (s) { + case 64: + return UD_R_RAX + rm; + case SZ_DP: + case 32: + return UD_R_EAX + rm; + case SZ_WP: + case 16: + return UD_R_AX + rm; + case 8: + if (u->dis_mode == 64 && u->pfx_rex) { + if (rm >= 4) + return UD_R_SPL + (rm-4); + return UD_R_AL + rm; + } else return UD_R_AL + rm; + default: + return 0; + } +} + +/* ----------------------------------------------------------------------------- + * resolve_gpr64() - 64bit General Purpose Register-Selection. + * ----------------------------------------------------------------------------- + */ +static enum ud_type +resolve_gpr64(struct ud* u, enum ud_operand_code gpr_op, enum ud_operand_size * size) +{ + if (gpr_op >= OP_rAXr8 && gpr_op <= OP_rDIr15) + gpr_op = (gpr_op - OP_rAXr8) | (REX_B(u->pfx_rex) << 3); + else gpr_op = (gpr_op - OP_rAX); + + if (u->opr_mode == 16) { + *size = 16; + return gpr_op + UD_R_AX; + } + if (u->dis_mode == 32 || + (u->opr_mode == 32 && ! (REX_W(u->pfx_rex) || u->default64))) { + *size = 32; + return gpr_op + UD_R_EAX; + } + + *size = 64; + return gpr_op + UD_R_RAX; +} + +/* ----------------------------------------------------------------------------- + * resolve_gpr32 () - 32bit General Purpose Register-Selection. + * ----------------------------------------------------------------------------- + */ +static enum ud_type +resolve_gpr32(struct ud* u, enum ud_operand_code gpr_op) +{ + gpr_op = gpr_op - OP_eAX; + + if (u->opr_mode == 16) + return gpr_op + UD_R_AX; + + return gpr_op + UD_R_EAX; +} + +/* ----------------------------------------------------------------------------- + * resolve_reg() - Resolves the register type + * ----------------------------------------------------------------------------- + */ +static enum ud_type +resolve_reg(struct ud* u, unsigned int type, unsigned char i) +{ + switch (type) { + case T_MMX : return UD_R_MM0 + (i & 7); + case T_XMM : return UD_R_XMM0 + i; + case T_CRG : return UD_R_CR0 + i; + case T_DBG : return UD_R_DR0 + i; + case T_SEG : { + /* + * Only 6 segment registers, anything else is an error. + */ + if ((i & 7) > 5) { + u->error = 1; + } else { + return UD_R_ES + (i & 7); + } + } + case T_NONE: + default: return UD_NONE; + } +} + +/* ----------------------------------------------------------------------------- + * decode_imm() - Decodes Immediate values. + * ----------------------------------------------------------------------------- + */ +static void +decode_imm(struct ud* u, unsigned int s, struct ud_operand *op) +{ + op->size = resolve_operand_size(u, s); + op->type = UD_OP_IMM; + + switch (op->size) { + case 8: op->lval.sbyte = ud_inp_uint8(u); break; + case 16: op->lval.uword = ud_inp_uint16(u); break; + case 32: op->lval.udword = ud_inp_uint32(u); break; + case 64: op->lval.uqword = ud_inp_uint64(u); break; + default: return; + } +} + + +/* + * decode_modrm_reg + * + * Decodes reg field of mod/rm byte + * + */ +static void +decode_modrm_reg(struct ud *u, + struct ud_operand *operand, + unsigned int type, + unsigned int size) +{ + uint8_t reg = (REX_R(u->pfx_rex) << 3) | MODRM_REG(modrm(u)); + operand->type = UD_OP_REG; + operand->size = resolve_operand_size(u, size); + + if (type == T_GPR) { + operand->base = decode_gpr(u, operand->size, reg); + } else { + operand->base = resolve_reg(u, type, reg); + } +} + + +/* + * decode_modrm_rm + * + * Decodes rm field of mod/rm byte + * + */ +static void +decode_modrm_rm(struct ud *u, + struct ud_operand *op, + unsigned char type, + unsigned int size) + +{ + unsigned char mod, rm, reg; + + /* get mod, r/m and reg fields */ + mod = MODRM_MOD(modrm(u)); + rm = (REX_B(u->pfx_rex) << 3) | MODRM_RM(modrm(u)); + reg = (REX_R(u->pfx_rex) << 3) | MODRM_REG(modrm(u)); + + UNUSED_PARAM(reg); + + op->size = resolve_operand_size(u, size); + + /* + * If mod is 11b, then the modrm.rm specifies a register. + * + */ + if (mod == 3) { + op->type = UD_OP_REG; + if (type == T_GPR) { + op->base = decode_gpr(u, op->size, rm); + } else { + op->base = resolve_reg(u, type, (REX_B(u->pfx_rex) << 3) | (rm & 7)); + } + return; + } + + + /* + * !11 => Memory Address + */ + op->type = UD_OP_MEM; + + if (u->adr_mode == 64) { + op->base = UD_R_RAX + rm; + if (mod == 1) { + op->offset = 8; + } else if (mod == 2) { + op->offset = 32; + } else if (mod == 0 && (rm & 7) == 5) { + op->base = UD_R_RIP; + op->offset = 32; + } else { + op->offset = 0; + } + /* + * Scale-Index-Base (SIB) + */ + if ((rm & 7) == 4) { + ud_inp_next(u); + + op->scale = (1 << SIB_S(ud_inp_curr(u))) & ~1; + op->index = UD_R_RAX + (SIB_I(ud_inp_curr(u)) | (REX_X(u->pfx_rex) << 3)); + op->base = UD_R_RAX + (SIB_B(ud_inp_curr(u)) | (REX_B(u->pfx_rex) << 3)); + + /* special conditions for base reference */ + if (op->index == UD_R_RSP) { + op->index = UD_NONE; + op->scale = UD_NONE; + } + + if (op->base == UD_R_RBP || op->base == UD_R_R13) { + if (mod == 0) { + op->base = UD_NONE; + } + if (mod == 1) { + op->offset = 8; + } else { + op->offset = 32; + } + } + } + } else if (u->adr_mode == 32) { + op->base = UD_R_EAX + rm; + if (mod == 1) { + op->offset = 8; + } else if (mod == 2) { + op->offset = 32; + } else if (mod == 0 && rm == 5) { + op->base = UD_NONE; + op->offset = 32; + } else { + op->offset = 0; + } + + /* Scale-Index-Base (SIB) */ + if ((rm & 7) == 4) { + ud_inp_next(u); + + op->scale = (1 << SIB_S(ud_inp_curr(u))) & ~1; + op->index = UD_R_EAX + (SIB_I(ud_inp_curr(u)) | (REX_X(u->pfx_rex) << 3)); + op->base = UD_R_EAX + (SIB_B(ud_inp_curr(u)) | (REX_B(u->pfx_rex) << 3)); + + if (op->index == UD_R_ESP) { + op->index = UD_NONE; + op->scale = UD_NONE; + } + + /* special condition for base reference */ + if (op->base == UD_R_EBP) { + if (mod == 0) { + op->base = UD_NONE; + } + if (mod == 1) { + op->offset = 8; + } else { + op->offset = 32; + } + } + } + } else { + const unsigned int bases[] = { UD_R_BX, UD_R_BX, UD_R_BP, UD_R_BP, + UD_R_SI, UD_R_DI, UD_R_BP, UD_R_BX }; + const unsigned int indices[] = { UD_R_SI, UD_R_DI, UD_R_SI, UD_R_DI, + UD_NONE, UD_NONE, UD_NONE, UD_NONE }; + op->base = bases[rm & 7]; + op->index = indices[rm & 7]; + if (mod == 0 && rm == 6) { + op->offset= 16; + op->base = UD_NONE; + } else if (mod == 1) { + op->offset = 8; + } else if (mod == 2) { + op->offset = 16; + } + } + + /* + * extract offset, if any + */ + switch (op->offset) { + case 8 : op->lval.ubyte = ud_inp_uint8(u); break; + case 16: op->lval.uword = ud_inp_uint16(u); break; + case 32: op->lval.udword = ud_inp_uint32(u); break; + case 64: op->lval.uqword = ud_inp_uint64(u); break; + default: break; + } +} + +/* ----------------------------------------------------------------------------- + * decode_o() - Decodes offset + * ----------------------------------------------------------------------------- + */ +static void +decode_o(struct ud* u, unsigned int s, struct ud_operand *op) +{ + switch (u->adr_mode) { + case 64: + op->offset = 64; + op->lval.uqword = ud_inp_uint64(u); + break; + case 32: + op->offset = 32; + op->lval.udword = ud_inp_uint32(u); + break; + case 16: + op->offset = 16; + op->lval.uword = ud_inp_uint16(u); + break; + default: + return; + } + op->type = UD_OP_MEM; + op->size = resolve_operand_size(u, s); +} + +/* ----------------------------------------------------------------------------- + * decode_operands() - Disassembles Operands. + * ----------------------------------------------------------------------------- + */ +static int +decode_operand(struct ud *u, + struct ud_operand *operand, + enum ud_operand_code type, + unsigned int size) +{ + switch (type) { + case OP_A : + decode_a(u, operand); + break; + case OP_MR: + if (MODRM_MOD(modrm(u)) == 3) { + decode_modrm_rm(u, operand, T_GPR, + size == SZ_DY ? SZ_MDQ : SZ_V); + } else if (size == SZ_WV) { + decode_modrm_rm( u, operand, T_GPR, SZ_W); + } else if (size == SZ_BV) { + decode_modrm_rm( u, operand, T_GPR, SZ_B); + } else if (size == SZ_DY) { + decode_modrm_rm( u, operand, T_GPR, SZ_D); + } else { + ASSERT(!"unexpected size"); + } + break; + case OP_M: + if (MODRM_MOD(modrm(u)) == 3) { + u->error = 1; + } + /* intended fall through */ + case OP_E: + decode_modrm_rm(u, operand, T_GPR, size); + break; + case OP_G: + decode_modrm_reg(u, operand, T_GPR, size); + break; + case OP_I: + decode_imm(u, size, operand); + break; + case OP_I1: + operand->type = UD_OP_CONST; + operand->lval.udword = 1; + break; + case OP_PR: + if (MODRM_MOD(modrm(u)) != 3) { + u->error = 1; + } + decode_modrm_rm(u, operand, T_MMX, size); + break; + case OP_P: + decode_modrm_reg(u, operand, T_MMX, size); + break; + case OP_VR: + if (MODRM_MOD(modrm(u)) != 3) { + u->error = 1; + } + /* intended fall through */ + case OP_W: + decode_modrm_rm(u, operand, T_XMM, size); + break; + case OP_V: + decode_modrm_reg(u, operand, T_XMM, size); + break; + case OP_S: + decode_modrm_reg(u, operand, T_SEG, size); + break; + case OP_AL: + case OP_CL: + case OP_DL: + case OP_BL: + case OP_AH: + case OP_CH: + case OP_DH: + case OP_BH: + operand->type = UD_OP_REG; + operand->base = UD_R_AL + (type - OP_AL); + operand->size = 8; + break; + case OP_DX: + operand->type = UD_OP_REG; + operand->base = UD_R_DX; + operand->size = 16; + break; + case OP_O: + decode_o(u, size, operand); + break; + case OP_rAXr8: + case OP_rCXr9: + case OP_rDXr10: + case OP_rBXr11: + case OP_rSPr12: + case OP_rBPr13: + case OP_rSIr14: + case OP_rDIr15: + case OP_rAX: + case OP_rCX: + case OP_rDX: + case OP_rBX: + case OP_rSP: + case OP_rBP: + case OP_rSI: + case OP_rDI: + operand->type = UD_OP_REG; + operand->base = resolve_gpr64(u, type, &operand->size); + break; + case OP_ALr8b: + case OP_CLr9b: + case OP_DLr10b: + case OP_BLr11b: + case OP_AHr12b: + case OP_CHr13b: + case OP_DHr14b: + case OP_BHr15b: { + ud_type_t gpr = (type - OP_ALr8b) + UD_R_AL + + (REX_B(u->pfx_rex) << 3); + if (UD_R_AH <= gpr && u->pfx_rex) { + gpr = gpr + 4; + } + operand->type = UD_OP_REG; + operand->base = gpr; + break; + } + case OP_eAX: + case OP_eCX: + case OP_eDX: + case OP_eBX: + case OP_eSP: + case OP_eBP: + case OP_eSI: + case OP_eDI: + operand->type = UD_OP_REG; + operand->base = resolve_gpr32(u, type); + operand->size = u->opr_mode == 16 ? 16 : 32; + break; + case OP_ES: + case OP_CS: + case OP_DS: + case OP_SS: + case OP_FS: + case OP_GS: + /* in 64bits mode, only fs and gs are allowed */ + if (u->dis_mode == 64) { + if (type != OP_FS && type != OP_GS) { + u->error= 1; + } + } + operand->type = UD_OP_REG; + operand->base = (type - OP_ES) + UD_R_ES; + operand->size = 16; + break; + case OP_J : + decode_imm(u, size, operand); + operand->type = UD_OP_JIMM; + break ; + case OP_Q: + decode_modrm_rm(u, operand, T_MMX, size); + break; + case OP_R : + decode_modrm_rm(u, operand, T_GPR, size); + break; + case OP_C: + decode_modrm_reg(u, operand, T_CRG, size); + break; + case OP_D: + decode_modrm_reg(u, operand, T_DBG, size); + break; + case OP_I3 : + operand->type = UD_OP_CONST; + operand->lval.sbyte = 3; + break; + case OP_ST0: + case OP_ST1: + case OP_ST2: + case OP_ST3: + case OP_ST4: + case OP_ST5: + case OP_ST6: + case OP_ST7: + operand->type = UD_OP_REG; + operand->base = (type - OP_ST0) + UD_R_ST0; + operand->size = 0; + break; + case OP_AX: + operand->type = UD_OP_REG; + operand->base = UD_R_AX; + operand->size = 16; + break; + default : + operand->type = UD_NONE; + break; + } + return 0; +} + + +/* + * decode_operands + * + * Disassemble upto 3 operands of the current instruction being + * disassembled. By the end of the function, the operand fields + * of the ud structure will have been filled. + */ +static int +decode_operands(struct ud* u) +{ + decode_operand(u, &u->operand[0], + u->itab_entry->operand1.type, + u->itab_entry->operand1.size); + decode_operand(u, &u->operand[1], + u->itab_entry->operand2.type, + u->itab_entry->operand2.size); + decode_operand(u, &u->operand[2], + u->itab_entry->operand3.type, + u->itab_entry->operand3.size); + return 0; +} + +/* ----------------------------------------------------------------------------- + * clear_insn() - clear instruction structure + * ----------------------------------------------------------------------------- + */ +static void +clear_insn(register struct ud* u) +{ + u->error = 0; + u->pfx_seg = 0; + u->pfx_opr = 0; + u->pfx_adr = 0; + u->pfx_lock = 0; + u->pfx_repne = 0; + u->pfx_rep = 0; + u->pfx_repe = 0; + u->pfx_rex = 0; + u->pfx_insn = 0; + u->mnemonic = UD_Inone; + u->itab_entry = NULL; + u->have_modrm = 0; + + memset( &u->operand[ 0 ], 0, sizeof( struct ud_operand ) ); + memset( &u->operand[ 1 ], 0, sizeof( struct ud_operand ) ); + memset( &u->operand[ 2 ], 0, sizeof( struct ud_operand ) ); +} + +static int +resolve_mode( struct ud* u ) +{ + /* if in error state, bail out */ + if ( u->error ) return -1; + + /* propagate prefix effects */ + if ( u->dis_mode == 64 ) { /* set 64bit-mode flags */ + + /* Check validity of instruction m64 */ + if ( P_INV64( u->itab_entry->prefix ) ) { + u->error = 1; + return -1; + } + + /* effective rex prefix is the effective mask for the + * instruction hard-coded in the opcode map. + */ + u->pfx_rex = ( u->pfx_rex & 0x40 ) | + ( u->pfx_rex & REX_PFX_MASK( u->itab_entry->prefix ) ); + + /* whether this instruction has a default operand size of + * 64bit, also hardcoded into the opcode map. + */ + u->default64 = P_DEF64( u->itab_entry->prefix ); + /* calculate effective operand size */ + if ( REX_W( u->pfx_rex ) ) { + u->opr_mode = 64; + } else if ( u->pfx_opr ) { + u->opr_mode = 16; + } else { + /* unless the default opr size of instruction is 64, + * the effective operand size in the absence of rex.w + * prefix is 32. + */ + u->opr_mode = ( u->default64 ) ? 64 : 32; + } + + /* calculate effective address size */ + u->adr_mode = (u->pfx_adr) ? 32 : 64; + } else if ( u->dis_mode == 32 ) { /* set 32bit-mode flags */ + u->opr_mode = ( u->pfx_opr ) ? 16 : 32; + u->adr_mode = ( u->pfx_adr ) ? 16 : 32; + } else if ( u->dis_mode == 16 ) { /* set 16bit-mode flags */ + u->opr_mode = ( u->pfx_opr ) ? 32 : 16; + u->adr_mode = ( u->pfx_adr ) ? 32 : 16; + } + + /* These flags determine which operand to apply the operand size + * cast to. + */ + u->c1 = ( P_C1( u->itab_entry->prefix ) ) ? 1 : 0; + u->c2 = ( P_C2( u->itab_entry->prefix ) ) ? 1 : 0; + u->c3 = ( P_C3( u->itab_entry->prefix ) ) ? 1 : 0; + + /* set flags for implicit addressing */ + u->implicit_addr = P_IMPADDR( u->itab_entry->prefix ); + + return 0; +} + +static int gen_hex( struct ud *u ) +{ + unsigned int i; + unsigned char *src_ptr = ud_inp_sess( u ); + char* src_hex; + + /* bail out if in error stat. */ + if ( u->error ) return -1; + /* output buffer pointe */ + src_hex = ( char* ) u->insn_hexcode; + /* for each byte used to decode instruction */ + for ( i = 0; i < u->inp_ctr; ++i, ++src_ptr) { + sprintf( src_hex, "%02x", *src_ptr & 0xFF ); + src_hex += 2; + } + return 0; +} + + +static inline int +decode_insn(struct ud *u, uint16_t ptr) +{ + ASSERT((ptr & 0x8000) == 0); + u->itab_entry = &ud_itab[ ptr ]; + u->mnemonic = u->itab_entry->mnemonic; + return (resolve_mode(u) == 0 && + decode_operands(u) == 0 && + resolve_mnemonic(u) == 0) ? 0 : -1; +} + + +/* + * decode_3dnow() + * + * Decoding 3dnow is a little tricky because of its strange opcode + * structure. The final opcode disambiguation depends on the last + * byte that comes after the operands have been decoded. Fortunately, + * all 3dnow instructions have the same set of operand types. So we + * go ahead and decode the instruction by picking an arbitrarily chosen + * valid entry in the table, decode the operands, and read the final + * byte to resolve the menmonic. + */ +static inline int +decode_3dnow(struct ud* u) +{ + uint16_t ptr; + ASSERT(u->le->type == UD_TAB__OPC_3DNOW); + ASSERT(u->le->table[0xc] != 0); + decode_insn(u, u->le->table[0xc]); + ud_inp_next(u); + if (u->error) { + return -1; + } + ptr = u->le->table[ud_inp_curr(u)]; + ASSERT((ptr & 0x8000) == 0); + u->mnemonic = ud_itab[ptr].mnemonic; + return 0; +} + + +static int +decode_ssepfx(struct ud *u) +{ + uint8_t idx = ((u->pfx_insn & 0xf) + 1) / 2; + if (u->le->table[idx] == 0) { + idx = 0; + } + if (idx && u->le->table[idx] != 0) { + /* + * "Consume" the prefix as a part of the opcode, so it is no + * longer exported as an instruction prefix. + */ + switch (u->pfx_insn) { + case 0xf2: + u->pfx_repne = 0; + break; + case 0xf3: + u->pfx_rep = 0; + u->pfx_repe = 0; + break; + case 0x66: + u->pfx_opr = 0; + break; + } + } + return decode_ext(u, u->le->table[idx]); +} + + +/* + * decode_ext() + * + * Decode opcode extensions (if any) + */ +static int +decode_ext(struct ud *u, uint16_t ptr) +{ + uint8_t idx = 0; + if ((ptr & 0x8000) == 0) { + return decode_insn(u, ptr); + } + u->le = &ud_lookup_table_list[(~0x8000 & ptr)]; + if (u->le->type == UD_TAB__OPC_3DNOW) { + return decode_3dnow(u); + } + + switch (u->le->type) { + case UD_TAB__OPC_MOD: + /* !11 = 0, 11 = 1 */ + idx = (MODRM_MOD(modrm(u)) + 1) / 4; + break; + /* disassembly mode/operand size/address size based tables. + * 16 = 0,, 32 = 1, 64 = 2 + */ + case UD_TAB__OPC_MODE: + idx = u->dis_mode / 32; + break; + case UD_TAB__OPC_OSIZE: + idx = eff_opr_mode(u->dis_mode, REX_W(u->pfx_rex), u->pfx_opr) / 32; + break; + case UD_TAB__OPC_ASIZE: + idx = eff_adr_mode(u->dis_mode, u->pfx_adr) / 32; + break; + case UD_TAB__OPC_X87: + idx = modrm(u) - 0xC0; + break; + case UD_TAB__OPC_VENDOR: + if (u->vendor == UD_VENDOR_ANY) { + /* choose a valid entry */ + idx = (u->le->table[idx] != 0) ? 0 : 1; + } else if (u->vendor == UD_VENDOR_AMD) { + idx = 0; + } else { + idx = 1; + } + break; + case UD_TAB__OPC_RM: + idx = MODRM_RM(modrm(u)); + break; + case UD_TAB__OPC_REG: + idx = MODRM_REG(modrm(u)); + break; + case UD_TAB__OPC_SSE: + return decode_ssepfx(u); + default: + ASSERT(!"not reached"); + break; + } + + return decode_ext(u, u->le->table[idx]); +} + + +static inline int +decode_opcode(struct ud *u) +{ + uint16_t ptr; + ASSERT(u->le->type == UD_TAB__OPC_TABLE); + ud_inp_next(u); + if (u->error) { + return -1; + } + ptr = u->le->table[ud_inp_curr(u)]; + if (ptr & 0x8000) { + u->le = &ud_lookup_table_list[ptr & ~0x8000]; + if (u->le->type == UD_TAB__OPC_TABLE) { + return decode_opcode(u); + } + } + return decode_ext(u, ptr); +} + + +/* ============================================================================= + * ud_decode() - Instruction decoder. Returns the number of bytes decoded. + * ============================================================================= + */ +unsigned int +ud_decode(struct ud *u) +{ + ud_inp_start(u); + clear_insn(u); + u->le = &ud_lookup_table_list[0]; + u->error = decode_prefixes(u) == -1 || + decode_opcode(u) == -1 || + u->error; + /* Handle decode error. */ + if (u->error) { + /* clear out the decode data. */ + clear_insn(u); + /* mark the sequence of bytes as invalid. */ + u->itab_entry = & s_ie__invalid; + u->mnemonic = u->itab_entry->mnemonic; + } + + /* maybe this stray segment override byte + * should be spewed out? + */ + if ( !P_SEG( u->itab_entry->prefix ) && + u->operand[0].type != UD_OP_MEM && + u->operand[1].type != UD_OP_MEM ) + u->pfx_seg = 0; + + u->insn_offset = u->pc; /* set offset of instruction */ + u->insn_fill = 0; /* set translation buffer index to 0 */ + u->pc += u->inp_ctr; /* move program counter by bytes decoded */ + gen_hex( u ); /* generate hex code */ + + /* return number of bytes disassembled. */ + return u->inp_ctr; +} + +/* +vim: set ts=2 sw=2 expandtab +*/ + +#endif // USE(UDIS86) diff --git a/Source/JavaScriptCore/disassembler/udis86/udis86_decode.h b/Source/JavaScriptCore/disassembler/udis86/udis86_decode.h new file mode 100644 index 000000000..940ed5ad6 --- /dev/null +++ b/Source/JavaScriptCore/disassembler/udis86/udis86_decode.h @@ -0,0 +1,258 @@ +/* udis86 - libudis86/decode.h + * + * Copyright (c) 2002-2009 Vivek Thampi + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef UD_DECODE_H +#define UD_DECODE_H + +#include "udis86_types.h" +#include "udis86_itab.h" + +#define MAX_INSN_LENGTH 15 + +/* register classes */ +#define T_NONE 0 +#define T_GPR 1 +#define T_MMX 2 +#define T_CRG 3 +#define T_DBG 4 +#define T_SEG 5 +#define T_XMM 6 + +/* itab prefix bits */ +#define P_none ( 0 ) +#define P_cast ( 1 << 0 ) +#define P_CAST(n) ( ( n >> 0 ) & 1 ) +#define P_c1 ( 1 << 0 ) +#define P_C1(n) ( ( n >> 0 ) & 1 ) +#define P_rexb ( 1 << 1 ) +#define P_REXB(n) ( ( n >> 1 ) & 1 ) +#define P_depM ( 1 << 2 ) +#define P_DEPM(n) ( ( n >> 2 ) & 1 ) +#define P_c3 ( 1 << 3 ) +#define P_C3(n) ( ( n >> 3 ) & 1 ) +#define P_inv64 ( 1 << 4 ) +#define P_INV64(n) ( ( n >> 4 ) & 1 ) +#define P_rexw ( 1 << 5 ) +#define P_REXW(n) ( ( n >> 5 ) & 1 ) +#define P_c2 ( 1 << 6 ) +#define P_C2(n) ( ( n >> 6 ) & 1 ) +#define P_def64 ( 1 << 7 ) +#define P_DEF64(n) ( ( n >> 7 ) & 1 ) +#define P_rexr ( 1 << 8 ) +#define P_REXR(n) ( ( n >> 8 ) & 1 ) +#define P_oso ( 1 << 9 ) +#define P_OSO(n) ( ( n >> 9 ) & 1 ) +#define P_aso ( 1 << 10 ) +#define P_ASO(n) ( ( n >> 10 ) & 1 ) +#define P_rexx ( 1 << 11 ) +#define P_REXX(n) ( ( n >> 11 ) & 1 ) +#define P_ImpAddr ( 1 << 12 ) +#define P_IMPADDR(n) ( ( n >> 12 ) & 1 ) +#define P_seg ( 1 << 13 ) +#define P_SEG(n) ( ( n >> 13 ) & 1 ) +#define P_sext ( 1 << 14 ) +#define P_SEXT(n) ( ( n >> 14 ) & 1 ) + +/* rex prefix bits */ +#define REX_W(r) ( ( 0xF & ( r ) ) >> 3 ) +#define REX_R(r) ( ( 0x7 & ( r ) ) >> 2 ) +#define REX_X(r) ( ( 0x3 & ( r ) ) >> 1 ) +#define REX_B(r) ( ( 0x1 & ( r ) ) >> 0 ) +#define REX_PFX_MASK(n) ( ( P_REXW(n) << 3 ) | \ + ( P_REXR(n) << 2 ) | \ + ( P_REXX(n) << 1 ) | \ + ( P_REXB(n) << 0 ) ) + +/* scable-index-base bits */ +#define SIB_S(b) ( ( b ) >> 6 ) +#define SIB_I(b) ( ( ( b ) >> 3 ) & 7 ) +#define SIB_B(b) ( ( b ) & 7 ) + +/* modrm bits */ +#define MODRM_REG(b) ( ( ( b ) >> 3 ) & 7 ) +#define MODRM_NNN(b) ( ( ( b ) >> 3 ) & 7 ) +#define MODRM_MOD(b) ( ( ( b ) >> 6 ) & 3 ) +#define MODRM_RM(b) ( ( b ) & 7 ) + +/* operand type constants -- order is important! */ + +enum ud_operand_code { + OP_NONE, + + OP_A, OP_E, OP_M, OP_G, + OP_I, + + OP_AL, OP_CL, OP_DL, OP_BL, + OP_AH, OP_CH, OP_DH, OP_BH, + + OP_ALr8b, OP_CLr9b, OP_DLr10b, OP_BLr11b, + OP_AHr12b, OP_CHr13b, OP_DHr14b, OP_BHr15b, + + OP_AX, OP_CX, OP_DX, OP_BX, + OP_SI, OP_DI, OP_SP, OP_BP, + + OP_rAX, OP_rCX, OP_rDX, OP_rBX, + OP_rSP, OP_rBP, OP_rSI, OP_rDI, + + OP_rAXr8, OP_rCXr9, OP_rDXr10, OP_rBXr11, + OP_rSPr12, OP_rBPr13, OP_rSIr14, OP_rDIr15, + + OP_eAX, OP_eCX, OP_eDX, OP_eBX, + OP_eSP, OP_eBP, OP_eSI, OP_eDI, + + OP_ES, OP_CS, OP_SS, OP_DS, + OP_FS, OP_GS, + + OP_ST0, OP_ST1, OP_ST2, OP_ST3, + OP_ST4, OP_ST5, OP_ST6, OP_ST7, + + OP_J, OP_S, OP_O, + OP_I1, OP_I3, + + OP_V, OP_W, OP_Q, OP_P, + + OP_R, OP_C, OP_D, OP_VR, OP_PR, + + OP_MR +} UD_ATTR_PACKED; + + +/* operand size constants */ + +enum ud_operand_size { + SZ_NA = 0, + SZ_Z = 1, + SZ_V = 2, + SZ_P = 3, + SZ_WP = 4, + SZ_DP = 5, + SZ_MDQ = 6, + SZ_RDQ = 7, + + /* the following values are used as is, + * and thus hard-coded. changing them + * will break internals + */ + SZ_B = 8, + SZ_W = 16, + SZ_D = 32, + SZ_Q = 64, + SZ_T = 80, + SZ_O = 128, + + SZ_WV = 17, + SZ_BV = 18, + SZ_DY = 19 + +} UD_ATTR_PACKED; + + +/* A single operand of an entry in the instruction table. + * (internal use only) + */ +struct ud_itab_entry_operand +{ + enum ud_operand_code type; + enum ud_operand_size size; +}; + + +/* A single entry in an instruction table. + *(internal use only) + */ +struct ud_itab_entry +{ + enum ud_mnemonic_code mnemonic; + struct ud_itab_entry_operand operand1; + struct ud_itab_entry_operand operand2; + struct ud_itab_entry_operand operand3; + uint32_t prefix; +}; + +struct ud_lookup_table_list_entry { + const uint16_t *table; + enum ud_table_type type; + const char *meta; +}; + + +static inline unsigned int sse_pfx_idx( const unsigned int pfx ) +{ + /* 00 = 0 + * f2 = 1 + * f3 = 2 + * 66 = 3 + */ + return ( ( pfx & 0xf ) + 1 ) / 2; +} + +static inline unsigned int mode_idx( const unsigned int mode ) +{ + /* 16 = 0 + * 32 = 1 + * 64 = 2 + */ + return ( mode / 32 ); +} + +static inline unsigned int modrm_mod_idx( const unsigned int mod ) +{ + /* !11 = 0 + * 11 = 1 + */ + return ( mod + 1 ) / 4; +} + +static inline unsigned int vendor_idx( const unsigned int vendor ) +{ + switch ( vendor ) { + case UD_VENDOR_AMD: return 0; + case UD_VENDOR_INTEL: return 1; + case UD_VENDOR_ANY: return 2; + default: return 2; + } +} + +static inline unsigned int is_group_ptr( uint16_t ptr ) +{ + return ( 0x8000 & ptr ); +} + +static inline unsigned int group_idx( uint16_t ptr ) +{ + return ( ~0x8000 & ptr ); +} + + +extern struct ud_itab_entry ud_itab[]; +extern struct ud_lookup_table_list_entry ud_lookup_table_list[]; + +#endif /* UD_DECODE_H */ + +/* vim:cindent + * vim:expandtab + * vim:ts=4 + * vim:sw=4 + */ diff --git a/Source/JavaScriptCore/disassembler/udis86/udis86_extern.h b/Source/JavaScriptCore/disassembler/udis86/udis86_extern.h new file mode 100644 index 000000000..8e87721e8 --- /dev/null +++ b/Source/JavaScriptCore/disassembler/udis86/udis86_extern.h @@ -0,0 +1,88 @@ +/* udis86 - libudis86/extern.h + * + * Copyright (c) 2002-2009 Vivek Thampi + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef UD_EXTERN_H +#define UD_EXTERN_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "udis86_types.h" + +/* ============================= PUBLIC API ================================= */ + +extern void ud_init(struct ud*); + +extern void ud_set_mode(struct ud*, uint8_t); + +extern void ud_set_pc(struct ud*, uint64_t); + +extern void ud_set_input_hook(struct ud*, int (*)(struct ud*)); + +extern void ud_set_input_buffer(struct ud*, uint8_t*, size_t); + +#ifndef __UD_STANDALONE__ +extern void ud_set_input_file(struct ud*, FILE*); +#endif /* __UD_STANDALONE__ */ + +extern void ud_set_vendor(struct ud*, unsigned); + +extern void ud_set_syntax(struct ud*, void (*)(struct ud*)); + +extern void ud_input_skip(struct ud*, size_t); + +extern int ud_input_end(struct ud*); + +extern unsigned int ud_decode(struct ud*); + +extern unsigned int ud_disassemble(struct ud*); + +extern void ud_translate_intel(struct ud*); + +extern void ud_translate_att(struct ud*); + +extern char* ud_insn_asm(struct ud* u); + +extern uint8_t* ud_insn_ptr(struct ud* u); + +extern uint64_t ud_insn_off(struct ud*); + +extern char* ud_insn_hex(struct ud*); + +extern unsigned int ud_insn_len(struct ud* u); + +extern const char* ud_lookup_mnemonic(enum ud_mnemonic_code c); + +extern void ud_set_user_opaque_data(struct ud*, void*); + +extern void *ud_get_user_opaque_data(struct ud*); + +/* ========================================================================== */ + +#ifdef __cplusplus +} +#endif +#endif diff --git a/Source/JavaScriptCore/disassembler/udis86/udis86_input.c b/Source/JavaScriptCore/disassembler/udis86/udis86_input.c new file mode 100644 index 000000000..4dbe32876 --- /dev/null +++ b/Source/JavaScriptCore/disassembler/udis86/udis86_input.c @@ -0,0 +1,262 @@ +/* udis86 - libudis86/input.c + * + * Copyright (c) 2002-2009 Vivek Thampi + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include "config.h" + +#if USE(UDIS86) + +#include "udis86_extern.h" +#include "udis86_types.h" +#include "udis86_input.h" + +/* ----------------------------------------------------------------------------- + * inp_buff_hook() - Hook for buffered inputs. + * ----------------------------------------------------------------------------- + */ +static int +inp_buff_hook(struct ud* u) +{ + if (u->inp_buff < u->inp_buff_end) + return *u->inp_buff++; + else return -1; +} + +#ifndef __UD_STANDALONE__ +/* ----------------------------------------------------------------------------- + * inp_file_hook() - Hook for FILE inputs. + * ----------------------------------------------------------------------------- + */ +static int +inp_file_hook(struct ud* u) +{ + return fgetc(u->inp_file); +} +#endif /* __UD_STANDALONE__*/ + +/* ============================================================================= + * ud_inp_set_hook() - Sets input hook. + * ============================================================================= + */ +extern void +ud_set_input_hook(register struct ud* u, int (*hook)(struct ud*)) +{ + u->inp_hook = hook; + ud_inp_init(u); +} + +extern void +ud_set_user_opaque_data( struct ud * u, void * opaque ) +{ + u->user_opaque_data = opaque; +} + +extern void * +ud_get_user_opaque_data( struct ud * u ) +{ + return u->user_opaque_data; +} + +/* ============================================================================= + * ud_inp_set_buffer() - Set buffer as input. + * ============================================================================= + */ +extern void +ud_set_input_buffer(register struct ud* u, uint8_t* buf, size_t len) +{ + u->inp_hook = inp_buff_hook; + u->inp_buff = buf; + u->inp_buff_end = buf + len; + ud_inp_init(u); +} + +#ifndef __UD_STANDALONE__ +/* ============================================================================= + * ud_input_set_file() - Set buffer as input. + * ============================================================================= + */ +extern void +ud_set_input_file(register struct ud* u, FILE* f) +{ + u->inp_hook = inp_file_hook; + u->inp_file = f; + ud_inp_init(u); +} +#endif /* __UD_STANDALONE__ */ + +/* ============================================================================= + * ud_input_skip() - Skip n input bytes. + * ============================================================================= + */ +extern void +ud_input_skip(struct ud* u, size_t n) +{ + while (n--) { + u->inp_hook(u); + } +} + +/* ============================================================================= + * ud_input_end() - Test for end of input. + * ============================================================================= + */ +extern int +ud_input_end(struct ud* u) +{ + return (u->inp_curr == u->inp_fill) && u->inp_end; +} + +/* ----------------------------------------------------------------------------- + * ud_inp_next() - Loads and returns the next byte from input. + * + * inp_curr and inp_fill are pointers to the cache. The program is written based + * on the property that they are 8-bits in size, and will eventually wrap around + * forming a circular buffer. So, the size of the cache is 256 in size, kind of + * unnecessary yet optimized. + * + * A buffer inp_sess stores the bytes disassembled for a single session. + * ----------------------------------------------------------------------------- + */ +extern uint8_t ud_inp_next(struct ud* u) +{ + int c = -1; + /* if current pointer is not upto the fill point in the + * input cache. + */ + if ( u->inp_curr != u->inp_fill ) { + c = u->inp_cache[ ++u->inp_curr ]; + /* if !end-of-input, call the input hook and get a byte */ + } else if ( u->inp_end || ( c = u->inp_hook( u ) ) == -1 ) { + /* end-of-input, mark it as an error, since the decoder, + * expected a byte more. + */ + u->error = 1; + /* flag end of input */ + u->inp_end = 1; + return 0; + } else { + /* increment pointers, we have a new byte. */ + u->inp_curr = ++u->inp_fill; + /* add the byte to the cache */ + u->inp_cache[ u->inp_fill ] = c; + } + /* record bytes input per decode-session. */ + u->inp_sess[ u->inp_ctr++ ] = c; + /* return byte */ + return ( uint8_t ) c; +} + +/* ----------------------------------------------------------------------------- + * ud_inp_back() - Move back a single byte in the stream. + * ----------------------------------------------------------------------------- + */ +extern void +ud_inp_back(struct ud* u) +{ + if ( u->inp_ctr > 0 ) { + --u->inp_curr; + --u->inp_ctr; + } +} + +/* ----------------------------------------------------------------------------- + * ud_inp_peek() - Peek into the next byte in source. + * ----------------------------------------------------------------------------- + */ +extern uint8_t +ud_inp_peek(struct ud* u) +{ + uint8_t r = ud_inp_next(u); + if ( !u->error ) ud_inp_back(u); /* Don't backup if there was an error */ + return r; +} + +/* ----------------------------------------------------------------------------- + * ud_inp_move() - Move ahead n input bytes. + * ----------------------------------------------------------------------------- + */ +extern void +ud_inp_move(struct ud* u, size_t n) +{ + while (n--) + ud_inp_next(u); +} + +/*------------------------------------------------------------------------------ + * ud_inp_uintN() - return uintN from source. + *------------------------------------------------------------------------------ + */ +extern uint8_t +ud_inp_uint8(struct ud* u) +{ + return ud_inp_next(u); +} + +extern uint16_t +ud_inp_uint16(struct ud* u) +{ + uint16_t r, ret; + + ret = ud_inp_next(u); + r = ud_inp_next(u); + return ret | (r << 8); +} + +extern uint32_t +ud_inp_uint32(struct ud* u) +{ + uint32_t r, ret; + + ret = ud_inp_next(u); + r = ud_inp_next(u); + ret = ret | (r << 8); + r = ud_inp_next(u); + ret = ret | (r << 16); + r = ud_inp_next(u); + return ret | (r << 24); +} + +extern uint64_t +ud_inp_uint64(struct ud* u) +{ + uint64_t r, ret; + + ret = ud_inp_next(u); + r = ud_inp_next(u); + ret = ret | (r << 8); + r = ud_inp_next(u); + ret = ret | (r << 16); + r = ud_inp_next(u); + ret = ret | (r << 24); + r = ud_inp_next(u); + ret = ret | (r << 32); + r = ud_inp_next(u); + ret = ret | (r << 40); + r = ud_inp_next(u); + ret = ret | (r << 48); + r = ud_inp_next(u); + return ret | (r << 56); +} + +#endif // USE(UDIS86) diff --git a/Source/JavaScriptCore/disassembler/udis86/udis86_input.h b/Source/JavaScriptCore/disassembler/udis86/udis86_input.h new file mode 100644 index 000000000..96865a88b --- /dev/null +++ b/Source/JavaScriptCore/disassembler/udis86/udis86_input.h @@ -0,0 +1,67 @@ +/* udis86 - libudis86/input.h + * + * Copyright (c) 2002-2009 Vivek Thampi + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef UD_INPUT_H +#define UD_INPUT_H + +#include "udis86_types.h" + +uint8_t ud_inp_next(struct ud*); +uint8_t ud_inp_peek(struct ud*); +uint8_t ud_inp_uint8(struct ud*); +uint16_t ud_inp_uint16(struct ud*); +uint32_t ud_inp_uint32(struct ud*); +uint64_t ud_inp_uint64(struct ud*); +void ud_inp_move(struct ud*, size_t); +void ud_inp_back(struct ud*); + +/* ud_inp_init() - Initializes the input system. */ +#define ud_inp_init(u) \ +do { \ + u->inp_curr = 0; \ + u->inp_fill = 0; \ + u->inp_ctr = 0; \ + u->inp_end = 0; \ +} while (0) + +/* ud_inp_start() - Should be called before each de-code operation. */ +#define ud_inp_start(u) u->inp_ctr = 0 + +/* ud_inp_back() - Resets the current pointer to its position before the current + * instruction disassembly was started. + */ +#define ud_inp_reset(u) \ +do { \ + u->inp_curr -= u->inp_ctr; \ + u->inp_ctr = 0; \ +} while (0) + +/* ud_inp_sess() - Returns the pointer to current session. */ +#define ud_inp_sess(u) (u->inp_sess) + +/* inp_cur() - Returns the current input byte. */ +#define ud_inp_curr(u) ((u)->inp_cache[(u)->inp_curr]) + +#endif diff --git a/Source/JavaScriptCore/disassembler/udis86/udis86_itab_holder.c b/Source/JavaScriptCore/disassembler/udis86/udis86_itab_holder.c new file mode 100644 index 000000000..80dda3a19 --- /dev/null +++ b/Source/JavaScriptCore/disassembler/udis86/udis86_itab_holder.c @@ -0,0 +1,33 @@ +/* + * Copyright (C) 2012 Apple Inc. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY APPLE INC. ``AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL APPLE INC. OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY + * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "config.h" + +#if USE(UDIS86) + +#include "udis86_itab.c" + +#endif + diff --git a/Source/JavaScriptCore/disassembler/udis86/udis86_syn-att.c b/Source/JavaScriptCore/disassembler/udis86/udis86_syn-att.c new file mode 100644 index 000000000..c9c84880a --- /dev/null +++ b/Source/JavaScriptCore/disassembler/udis86/udis86_syn-att.c @@ -0,0 +1,265 @@ +/* udis86 - libudis86/syn-att.c + * + * Copyright (c) 2002-2009 Vivek Thampi + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include "config.h" + +#if USE(UDIS86) + +#include "udis86_types.h" +#include "udis86_extern.h" +#include "udis86_decode.h" +#include "udis86_itab.h" +#include "udis86_syn.h" + +/* ----------------------------------------------------------------------------- + * opr_cast() - Prints an operand cast. + * ----------------------------------------------------------------------------- + */ +static void +opr_cast(struct ud* u, struct ud_operand* op) +{ + switch(op->size) { + case 16 : case 32 : + mkasm(u, "*"); break; + default: break; + } +} + +/* ----------------------------------------------------------------------------- + * gen_operand() - Generates assembly output for each operand. + * ----------------------------------------------------------------------------- + */ +static void +gen_operand(struct ud* u, struct ud_operand* op) +{ + switch(op->type) { + case UD_OP_REG: + mkasm(u, "%%%s", ud_reg_tab[op->base - UD_R_AL]); + break; + + case UD_OP_MEM: + if (u->br_far) opr_cast(u, op); + if (u->pfx_seg) + mkasm(u, "%%%s:", ud_reg_tab[u->pfx_seg - UD_R_AL]); + if (op->offset == 8) { + if (op->lval.sbyte < 0) + mkasm(u, "-0x%x", (-op->lval.sbyte) & 0xff); + else + mkasm(u, "0x%x", op->lval.sbyte); + } + else if (op->offset == 16) { + if (op->lval.sword < 0) + mkasm(u, "-0x%x", (-op->lval.sword) & 0xffff); + else + mkasm(u, "0x%x", op->lval.sword); + } else if (op->offset == 32) { + if (op->lval.sdword < 0) + mkasm(u, "-0x%x", (-op->lval.sdword) & 0xffffffff); + else + mkasm(u, "0x%x", op->lval.sdword); + } else if (op->offset == 64) { + if (op->lval.sdword < 0) + mkasm(u, "-0x" FMT64 "x", (uint64_t)-op->lval.sqword); + else + mkasm(u, "0x" FMT64 "x", (uint64_t)op->lval.sqword); + } + + if (op->base) + mkasm(u, "(%%%s", ud_reg_tab[op->base - UD_R_AL]); + if (op->index) { + if (op->base) + mkasm(u, ","); + else mkasm(u, "("); + mkasm(u, "%%%s", ud_reg_tab[op->index - UD_R_AL]); + } + if (op->scale) + mkasm(u, ",%d", op->scale); + if (op->base || op->index) + mkasm(u, ")"); + break; + + case UD_OP_IMM: { + int64_t imm = 0; + uint64_t sext_mask = 0xffffffffffffffffull; + unsigned sext_size = op->size; + + switch (op->size) { + case 8: imm = op->lval.sbyte; break; + case 16: imm = op->lval.sword; break; + case 32: imm = op->lval.sdword; break; + case 64: imm = op->lval.sqword; break; + } + if ( P_SEXT( u->itab_entry->prefix ) ) { + sext_size = u->operand[ 0 ].size; + if ( u->mnemonic == UD_Ipush ) + /* push sign-extends to operand size */ + sext_size = u->opr_mode; + } + if ( sext_size < 64 ) + sext_mask = ( 1ull << sext_size ) - 1; + mkasm( u, "$0x" FMT64 "x", (uint64_t)(imm & sext_mask) ); + + break; + } + + case UD_OP_JIMM: + switch (op->size) { + case 8: + mkasm(u, "0x" FMT64 "x", (uint64_t)(u->pc + op->lval.sbyte)); + break; + case 16: + mkasm(u, "0x" FMT64 "x", (uint64_t)((u->pc + op->lval.sword) & 0xffff) ); + break; + case 32: + if (u->dis_mode == 32) + mkasm(u, "0x" FMT64 "x", (uint64_t)((u->pc + op->lval.sdword) & 0xffffffff)); + else + mkasm(u, "0x" FMT64 "x", (uint64_t)(u->pc + op->lval.sdword)); + break; + default:break; + } + break; + + case UD_OP_PTR: + switch (op->size) { + case 32: + mkasm(u, "$0x%x, $0x%x", op->lval.ptr.seg, + op->lval.ptr.off & 0xFFFF); + break; + case 48: + mkasm(u, "$0x%x, $0x%lx", op->lval.ptr.seg, + (unsigned long)op->lval.ptr.off); + break; + } + break; + + default: return; + } +} + +/* ============================================================================= + * translates to AT&T syntax + * ============================================================================= + */ +extern void +ud_translate_att(struct ud *u) +{ + int size = 0; + unsigned i; + + /* check if P_OSO prefix is used */ + if (! P_OSO(u->itab_entry->prefix) && u->pfx_opr) { + switch (u->dis_mode) { + case 16: + mkasm(u, "o32 "); + break; + case 32: + case 64: + mkasm(u, "o16 "); + break; + } + } + + /* check if P_ASO prefix was used */ + if (! P_ASO(u->itab_entry->prefix) && u->pfx_adr) { + switch (u->dis_mode) { + case 16: + mkasm(u, "a32 "); + break; + case 32: + mkasm(u, "a16 "); + break; + case 64: + mkasm(u, "a32 "); + break; + } + } + + if (u->pfx_lock) + mkasm(u, "lock "); + if (u->pfx_rep) + mkasm(u, "rep "); + if (u->pfx_repne) + mkasm(u, "repne "); + + /* special instructions */ + switch (u->mnemonic) { + case UD_Iretf: + mkasm(u, "lret "); + break; + case UD_Idb: + mkasm(u, ".byte 0x%x", u->operand[0].lval.ubyte); + return; + case UD_Ijmp: + case UD_Icall: + if (u->br_far) mkasm(u, "l"); + mkasm(u, "%s", ud_lookup_mnemonic(u->mnemonic)); + break; + case UD_Ibound: + case UD_Ienter: + if (u->operand[0].type != UD_NONE) + gen_operand(u, &u->operand[0]); + if (u->operand[1].type != UD_NONE) { + mkasm(u, ","); + gen_operand(u, &u->operand[1]); + } + return; + default: + mkasm(u, "%s", ud_lookup_mnemonic(u->mnemonic)); + } + + for (i = 3; i--;) { + if (u->operand[i].size > size + && u->operand[i].type != UD_OP_JIMM) + size = u->operand[i].size; + } + + if (size == 8) + mkasm(u, "b"); + else if (size == 16) + mkasm(u, "w"); + else if (size == 32) + mkasm(u, "l"); + else if (size == 64) + mkasm(u, "q"); + + mkasm(u, " "); + + if (u->operand[2].type != UD_NONE) { + gen_operand(u, &u->operand[2]); + mkasm(u, ", "); + } + + if (u->operand[1].type != UD_NONE) { + gen_operand(u, &u->operand[1]); + mkasm(u, ", "); + } + + if (u->operand[0].type != UD_NONE) + gen_operand(u, &u->operand[0]); +} + +#endif // USE(UDIS86) + diff --git a/Source/JavaScriptCore/disassembler/udis86/udis86_syn-intel.c b/Source/JavaScriptCore/disassembler/udis86/udis86_syn-intel.c new file mode 100644 index 000000000..4ad42eb63 --- /dev/null +++ b/Source/JavaScriptCore/disassembler/udis86/udis86_syn-intel.c @@ -0,0 +1,278 @@ +/* udis86 - libudis86/syn-intel.c + * + * Copyright (c) 2002-2009 Vivek Thampi + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include "config.h" + +#if USE(UDIS86) + +#include "udis86_types.h" +#include "udis86_extern.h" +#include "udis86_decode.h" +#include "udis86_itab.h" +#include "udis86_syn.h" + +/* ----------------------------------------------------------------------------- + * opr_cast() - Prints an operand cast. + * ----------------------------------------------------------------------------- + */ +static void +opr_cast(struct ud* u, struct ud_operand* op) +{ + switch(op->size) { + case 8: mkasm(u, "byte " ); break; + case 16: mkasm(u, "word " ); break; + case 32: mkasm(u, "dword "); break; + case 64: mkasm(u, "qword "); break; + case 80: mkasm(u, "tword "); break; + default: break; + } + if (u->br_far) + mkasm(u, "far "); +} + +/* ----------------------------------------------------------------------------- + * gen_operand() - Generates assembly output for each operand. + * ----------------------------------------------------------------------------- + */ +static void gen_operand(struct ud* u, struct ud_operand* op, int syn_cast) +{ + switch(op->type) { + case UD_OP_REG: + mkasm(u, "%s", ud_reg_tab[op->base - UD_R_AL]); + break; + + case UD_OP_MEM: { + + int op_f = 0; + + if (syn_cast) + opr_cast(u, op); + + mkasm(u, "["); + + if (u->pfx_seg) + mkasm(u, "%s:", ud_reg_tab[u->pfx_seg - UD_R_AL]); + + if (op->base) { + mkasm(u, "%s", ud_reg_tab[op->base - UD_R_AL]); + op_f = 1; + } + + if (op->index) { + if (op_f) + mkasm(u, "+"); + mkasm(u, "%s", ud_reg_tab[op->index - UD_R_AL]); + op_f = 1; + } + + if (op->scale) + mkasm(u, "*%d", op->scale); + + if (op->offset == 8) { + if (op->lval.sbyte < 0) + mkasm(u, "-0x%x", -op->lval.sbyte); + else mkasm(u, "%s0x%x", (op_f) ? "+" : "", op->lval.sbyte); + } + else if (op->offset == 16) + mkasm(u, "%s0x%x", (op_f) ? "+" : "", op->lval.uword); + else if (op->offset == 32) { + if (u->adr_mode == 64) { + if (op->lval.sdword < 0) + mkasm(u, "-0x%x", -op->lval.sdword); + else mkasm(u, "%s0x%x", (op_f) ? "+" : "", op->lval.sdword); + } + else mkasm(u, "%s0x%lx", (op_f) ? "+" : "", (unsigned long)op->lval.udword); + } + else if (op->offset == 64) + mkasm(u, "%s0x" FMT64 "x", (op_f) ? "+" : "", (uint64_t)op->lval.uqword); + + mkasm(u, "]"); + break; + } + + case UD_OP_IMM: { + int64_t imm = 0; + uint64_t sext_mask = 0xffffffffffffffffull; + unsigned sext_size = op->size; + + if (syn_cast) + opr_cast(u, op); + switch (op->size) { + case 8: imm = op->lval.sbyte; break; + case 16: imm = op->lval.sword; break; + case 32: imm = op->lval.sdword; break; + case 64: imm = op->lval.sqword; break; + } + if ( P_SEXT( u->itab_entry->prefix ) ) { + sext_size = u->operand[ 0 ].size; + if ( u->mnemonic == UD_Ipush ) + /* push sign-extends to operand size */ + sext_size = u->opr_mode; + } + if ( sext_size < 64 ) + sext_mask = ( 1ull << sext_size ) - 1; + mkasm( u, "0x" FMT64 "x", (uint64_t)(imm & sext_mask) ); + + break; + } + + + case UD_OP_JIMM: + if (syn_cast) opr_cast(u, op); + switch (op->size) { + case 8: + mkasm(u, "0x" FMT64 "x", (uint64_t)(u->pc + op->lval.sbyte)); + break; + case 16: + mkasm(u, "0x" FMT64 "x", (uint64_t)(( u->pc + op->lval.sword ) & 0xffff) ); + break; + case 32: + mkasm(u, "0x" FMT64 "x", (uint64_t)(( u->pc + op->lval.sdword ) & 0xfffffffful) ); + break; + default:break; + } + break; + + case UD_OP_PTR: + switch (op->size) { + case 32: + mkasm(u, "word 0x%x:0x%x", op->lval.ptr.seg, + op->lval.ptr.off & 0xFFFF); + break; + case 48: + mkasm(u, "dword 0x%x:0x%lx", op->lval.ptr.seg, + (unsigned long)op->lval.ptr.off); + break; + } + break; + + case UD_OP_CONST: + if (syn_cast) opr_cast(u, op); + mkasm(u, "%d", op->lval.udword); + break; + + default: return; + } +} + +/* ============================================================================= + * translates to intel syntax + * ============================================================================= + */ +extern void ud_translate_intel(struct ud* u) +{ + /* -- prefixes -- */ + + /* check if P_OSO prefix is used */ + if (! P_OSO(u->itab_entry->prefix) && u->pfx_opr) { + switch (u->dis_mode) { + case 16: + mkasm(u, "o32 "); + break; + case 32: + case 64: + mkasm(u, "o16 "); + break; + } + } + + /* check if P_ASO prefix was used */ + if (! P_ASO(u->itab_entry->prefix) && u->pfx_adr) { + switch (u->dis_mode) { + case 16: + mkasm(u, "a32 "); + break; + case 32: + mkasm(u, "a16 "); + break; + case 64: + mkasm(u, "a32 "); + break; + } + } + + if ( u->pfx_seg && + u->operand[0].type != UD_OP_MEM && + u->operand[1].type != UD_OP_MEM ) { + mkasm(u, "%s ", ud_reg_tab[u->pfx_seg - UD_R_AL]); + } + if (u->pfx_lock) + mkasm(u, "lock "); + if (u->pfx_rep) + mkasm(u, "rep "); + if (u->pfx_repne) + mkasm(u, "repne "); + + /* print the instruction mnemonic */ + mkasm(u, "%s ", ud_lookup_mnemonic(u->mnemonic)); + + /* operand 1 */ + if (u->operand[0].type != UD_NONE) { + int cast = 0; + if ( u->operand[0].type == UD_OP_IMM && + u->operand[1].type == UD_NONE ) + cast = u->c1; + if ( u->operand[0].type == UD_OP_MEM ) { + cast = u->c1; + if ( u->operand[1].type == UD_OP_IMM || + u->operand[1].type == UD_OP_CONST ) + cast = 1; + if ( u->operand[1].type == UD_NONE ) + cast = 1; + if ( ( u->operand[0].size != u->operand[1].size ) && u->operand[1].size ) + cast = 1; + } else if ( u->operand[ 0 ].type == UD_OP_JIMM ) { + if ( u->operand[ 0 ].size > 8 ) cast = 1; + } + gen_operand(u, &u->operand[0], cast); + } + /* operand 2 */ + if (u->operand[1].type != UD_NONE) { + int cast = 0; + mkasm(u, ", "); + if ( u->operand[1].type == UD_OP_MEM ) { + cast = u->c1; + + if ( u->operand[0].type != UD_OP_REG ) + cast = 1; + if ( u->operand[0].size != u->operand[1].size && u->operand[1].size ) + cast = 1; + if ( u->operand[0].type == UD_OP_REG && + u->operand[0].base >= UD_R_ES && + u->operand[0].base <= UD_R_GS ) + cast = 0; + } + gen_operand(u, &u->operand[1], cast ); + } + + /* operand 3 */ + if (u->operand[2].type != UD_NONE) { + mkasm(u, ", "); + gen_operand(u, &u->operand[2], u->c3); + } +} + +#endif // USE(UDIS86) + diff --git a/Source/JavaScriptCore/disassembler/udis86/udis86_syn.c b/Source/JavaScriptCore/disassembler/udis86/udis86_syn.c new file mode 100644 index 000000000..31a45ea5c --- /dev/null +++ b/Source/JavaScriptCore/disassembler/udis86/udis86_syn.c @@ -0,0 +1,86 @@ +/* udis86 - libudis86/syn.c + * + * Copyright (c) 2002-2009 Vivek Thampi + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "config.h" + +#if USE(UDIS86) + +/* ----------------------------------------------------------------------------- + * Intel Register Table - Order Matters (types.h)! + * ----------------------------------------------------------------------------- + */ +const char* ud_reg_tab[] = +{ + "al", "cl", "dl", "bl", + "ah", "ch", "dh", "bh", + "spl", "bpl", "sil", "dil", + "r8b", "r9b", "r10b", "r11b", + "r12b", "r13b", "r14b", "r15b", + + "ax", "cx", "dx", "bx", + "sp", "bp", "si", "di", + "r8w", "r9w", "r10w", "r11w", + "r12w", "r13W" , "r14w", "r15w", + + "eax", "ecx", "edx", "ebx", + "esp", "ebp", "esi", "edi", + "r8d", "r9d", "r10d", "r11d", + "r12d", "r13d", "r14d", "r15d", + + "rax", "rcx", "rdx", "rbx", + "rsp", "rbp", "rsi", "rdi", + "r8", "r9", "r10", "r11", + "r12", "r13", "r14", "r15", + + "es", "cs", "ss", "ds", + "fs", "gs", + + "cr0", "cr1", "cr2", "cr3", + "cr4", "cr5", "cr6", "cr7", + "cr8", "cr9", "cr10", "cr11", + "cr12", "cr13", "cr14", "cr15", + + "dr0", "dr1", "dr2", "dr3", + "dr4", "dr5", "dr6", "dr7", + "dr8", "dr9", "dr10", "dr11", + "dr12", "dr13", "dr14", "dr15", + + "mm0", "mm1", "mm2", "mm3", + "mm4", "mm5", "mm6", "mm7", + + "st0", "st1", "st2", "st3", + "st4", "st5", "st6", "st7", + + "xmm0", "xmm1", "xmm2", "xmm3", + "xmm4", "xmm5", "xmm6", "xmm7", + "xmm8", "xmm9", "xmm10", "xmm11", + "xmm12", "xmm13", "xmm14", "xmm15", + + "rip" +}; + +#endif // USE(UDIS86) + diff --git a/Source/JavaScriptCore/disassembler/udis86/udis86_syn.h b/Source/JavaScriptCore/disassembler/udis86/udis86_syn.h new file mode 100644 index 000000000..e8636163e --- /dev/null +++ b/Source/JavaScriptCore/disassembler/udis86/udis86_syn.h @@ -0,0 +1,47 @@ +/* udis86 - libudis86/syn.h + * + * Copyright (c) 2002-2009 + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef UD_SYN_H +#define UD_SYN_H + +#include "udis86_types.h" +#include + +#ifndef __UD_STANDALONE__ +# include +#endif /* __UD_STANDALONE__ */ + +extern const char* ud_reg_tab[]; + +static void mkasm(struct ud* u, const char* fmt, ...) WTF_ATTRIBUTE_PRINTF(2, 3); +static void mkasm(struct ud* u, const char* fmt, ...) +{ + va_list ap; + va_start(ap, fmt); + u->insn_fill += vsnprintf((char*) u->insn_buffer + u->insn_fill, UD_STRING_BUFFER_SIZE - u->insn_fill, fmt, ap); + va_end(ap); +} + +#endif diff --git a/Source/JavaScriptCore/disassembler/udis86/udis86_types.h b/Source/JavaScriptCore/disassembler/udis86/udis86_types.h new file mode 100644 index 000000000..176bf6d73 --- /dev/null +++ b/Source/JavaScriptCore/disassembler/udis86/udis86_types.h @@ -0,0 +1,242 @@ +/* udis86 - libudis86/types.h + * + * Copyright (c) 2002-2009 Vivek Thampi + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef UD_TYPES_H +#define UD_TYPES_H + +#ifndef __UD_STANDALONE__ +# include +#endif /* __UD_STANDALONE__ */ + +/* gcc specific extensions */ +#ifdef __GNUC__ +# define UD_ATTR_PACKED __attribute__((packed)) +#else +# define UD_ATTR_PACKED +#endif /* UD_ATTR_PACKED */ + +#ifdef _MSC_VER +# define FMT64 "%I64" + typedef unsigned __int8 uint8_t; + typedef unsigned __int16 uint16_t; + typedef unsigned __int32 uint32_t; + typedef unsigned __int64 uint64_t; + typedef __int8 int8_t; + typedef __int16 int16_t; + typedef __int32 int32_t; + typedef __int64 int64_t; +#else +# if defined(__GNU_LIBRARY__) && defined(__WORDSIZE) && (__WORDSIZE == 64) +# define FMT64 "%l" +# else +# define FMT64 "%ll" +# endif +# ifndef __UD_STANDALONE__ +# include +# endif /* __UD_STANDALONE__ */ +#endif + +/* ----------------------------------------------------------------------------- + * All possible "types" of objects in udis86. Order is Important! + * ----------------------------------------------------------------------------- + */ +enum ud_type +{ + UD_NONE, + + /* 8 bit GPRs */ + UD_R_AL, UD_R_CL, UD_R_DL, UD_R_BL, + UD_R_AH, UD_R_CH, UD_R_DH, UD_R_BH, + UD_R_SPL, UD_R_BPL, UD_R_SIL, UD_R_DIL, + UD_R_R8B, UD_R_R9B, UD_R_R10B, UD_R_R11B, + UD_R_R12B, UD_R_R13B, UD_R_R14B, UD_R_R15B, + + /* 16 bit GPRs */ + UD_R_AX, UD_R_CX, UD_R_DX, UD_R_BX, + UD_R_SP, UD_R_BP, UD_R_SI, UD_R_DI, + UD_R_R8W, UD_R_R9W, UD_R_R10W, UD_R_R11W, + UD_R_R12W, UD_R_R13W, UD_R_R14W, UD_R_R15W, + + /* 32 bit GPRs */ + UD_R_EAX, UD_R_ECX, UD_R_EDX, UD_R_EBX, + UD_R_ESP, UD_R_EBP, UD_R_ESI, UD_R_EDI, + UD_R_R8D, UD_R_R9D, UD_R_R10D, UD_R_R11D, + UD_R_R12D, UD_R_R13D, UD_R_R14D, UD_R_R15D, + + /* 64 bit GPRs */ + UD_R_RAX, UD_R_RCX, UD_R_RDX, UD_R_RBX, + UD_R_RSP, UD_R_RBP, UD_R_RSI, UD_R_RDI, + UD_R_R8, UD_R_R9, UD_R_R10, UD_R_R11, + UD_R_R12, UD_R_R13, UD_R_R14, UD_R_R15, + + /* segment registers */ + UD_R_ES, UD_R_CS, UD_R_SS, UD_R_DS, + UD_R_FS, UD_R_GS, + + /* control registers*/ + UD_R_CR0, UD_R_CR1, UD_R_CR2, UD_R_CR3, + UD_R_CR4, UD_R_CR5, UD_R_CR6, UD_R_CR7, + UD_R_CR8, UD_R_CR9, UD_R_CR10, UD_R_CR11, + UD_R_CR12, UD_R_CR13, UD_R_CR14, UD_R_CR15, + + /* debug registers */ + UD_R_DR0, UD_R_DR1, UD_R_DR2, UD_R_DR3, + UD_R_DR4, UD_R_DR5, UD_R_DR6, UD_R_DR7, + UD_R_DR8, UD_R_DR9, UD_R_DR10, UD_R_DR11, + UD_R_DR12, UD_R_DR13, UD_R_DR14, UD_R_DR15, + + /* mmx registers */ + UD_R_MM0, UD_R_MM1, UD_R_MM2, UD_R_MM3, + UD_R_MM4, UD_R_MM5, UD_R_MM6, UD_R_MM7, + + /* x87 registers */ + UD_R_ST0, UD_R_ST1, UD_R_ST2, UD_R_ST3, + UD_R_ST4, UD_R_ST5, UD_R_ST6, UD_R_ST7, + + /* extended multimedia registers */ + UD_R_XMM0, UD_R_XMM1, UD_R_XMM2, UD_R_XMM3, + UD_R_XMM4, UD_R_XMM5, UD_R_XMM6, UD_R_XMM7, + UD_R_XMM8, UD_R_XMM9, UD_R_XMM10, UD_R_XMM11, + UD_R_XMM12, UD_R_XMM13, UD_R_XMM14, UD_R_XMM15, + + UD_R_RIP, + + /* Operand Types */ + UD_OP_REG, UD_OP_MEM, UD_OP_PTR, UD_OP_IMM, + UD_OP_JIMM, UD_OP_CONST +}; + +#include "udis86_itab.h" + +/* ----------------------------------------------------------------------------- + * struct ud_operand - Disassembled instruction Operand. + * ----------------------------------------------------------------------------- + */ +struct ud_operand +{ + enum ud_type type; + uint8_t size; + union { + int8_t sbyte; + uint8_t ubyte; + int16_t sword; + uint16_t uword; + int32_t sdword; + uint32_t udword; + int64_t sqword; + uint64_t uqword; + + struct { + uint16_t seg; + uint32_t off; + } ptr; + } lval; + + enum ud_type base; + enum ud_type index; + uint8_t offset; + uint8_t scale; +}; + +#define UD_STRING_BUFFER_SIZE 64 + +/* ----------------------------------------------------------------------------- + * struct ud - The udis86 object. + * ----------------------------------------------------------------------------- + */ +struct ud +{ + int (*inp_hook) (struct ud*); + uint8_t inp_curr; + uint8_t inp_fill; +#ifndef __UD_STANDALONE__ + FILE* inp_file; +#endif + uint8_t inp_ctr; + uint8_t* inp_buff; + uint8_t* inp_buff_end; + uint8_t inp_end; + void (*translator)(struct ud*); + uint64_t insn_offset; + char insn_hexcode[32]; + char insn_buffer[UD_STRING_BUFFER_SIZE]; + unsigned int insn_fill; + uint8_t dis_mode; + uint64_t pc; + uint8_t vendor; + struct map_entry* mapen; + enum ud_mnemonic_code mnemonic; + struct ud_operand operand[3]; + uint8_t error; + uint8_t pfx_rex; + uint8_t pfx_seg; + uint8_t pfx_opr; + uint8_t pfx_adr; + uint8_t pfx_lock; + uint8_t pfx_rep; + uint8_t pfx_repe; + uint8_t pfx_repne; + uint8_t pfx_insn; + uint8_t default64; + uint8_t opr_mode; + uint8_t adr_mode; + uint8_t br_far; + uint8_t br_near; + uint8_t implicit_addr; + uint8_t c1; + uint8_t c2; + uint8_t c3; + uint8_t inp_cache[256]; + uint8_t inp_sess[64]; + uint8_t have_modrm; + uint8_t modrm; + void * user_opaque_data; + struct ud_itab_entry * itab_entry; + struct ud_lookup_table_list_entry *le; +}; + +/* ----------------------------------------------------------------------------- + * Type-definitions + * ----------------------------------------------------------------------------- + */ +typedef enum ud_type ud_type_t; +typedef enum ud_mnemonic_code ud_mnemonic_code_t; + +typedef struct ud ud_t; +typedef struct ud_operand ud_operand_t; + +#define UD_SYN_INTEL ud_translate_intel +#define UD_SYN_ATT ud_translate_att +#define UD_EOI -1 +#define UD_INP_CACHE_SZ 32 +#define UD_VENDOR_AMD 0 +#define UD_VENDOR_INTEL 1 +#define UD_VENDOR_ANY 2 + +#define bail_out(ud,error_code) longjmp( (ud)->bailout, error_code ) +#define try_decode(ud) if ( setjmp( (ud)->bailout ) == 0 ) +#define catch_error() else + +#endif -- cgit v1.2.1