<feed xmlns='http://www.w3.org/2005/Atom'>
<title>delta/coreboot/coreboot.git/src/include, branch master</title>
<subtitle>review.coreboot.org: coreboot.git
</subtitle>
<link rel='alternate' type='text/html' href='http://91.123.203.49/cgit/delta/coreboot/coreboot.git/'/>
<entry>
<title>console: Add format-checking __printf() to die()</title>
<updated>2023-05-17T11:23:59+00:00</updated>
<author>
<name>Nico Huber</name>
<email>nico.h@gmx.de</email>
</author>
<published>2023-05-12T13:46:24+00:00</published>
<link rel='alternate' type='text/html' href='http://91.123.203.49/cgit/delta/coreboot/coreboot.git/commit/?id=6a07db21b12b08c7b975921f2ee1196dd0ec92b3'/>
<id>6a07db21b12b08c7b975921f2ee1196dd0ec92b3</id>
<content type='text'>
Code changes are necessary because `-Wformat` warns about empty
format strings by default.

Change-Id: Ic8021b70f4cd4875b06f196f88b84940c9a79fe0
Signed-off-by: Nico Huber &lt;nico.h@gmx.de&gt;
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75147
Reviewed-by: Jérémy Compostella &lt;jeremy.compostella@intel.com&gt;
Tested-by: build bot (Jenkins) &lt;no-reply@coreboot.org&gt;
Reviewed-by: Angel Pons &lt;th3fanbus@gmail.com&gt;
Reviewed-by: Arthur Heymans &lt;arthur@aheymans.xyz&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Code changes are necessary because `-Wformat` warns about empty
format strings by default.

Change-Id: Ic8021b70f4cd4875b06f196f88b84940c9a79fe0
Signed-off-by: Nico Huber &lt;nico.h@gmx.de&gt;
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75147
Reviewed-by: Jérémy Compostella &lt;jeremy.compostella@intel.com&gt;
Tested-by: build bot (Jenkins) &lt;no-reply@coreboot.org&gt;
Reviewed-by: Angel Pons &lt;th3fanbus@gmail.com&gt;
Reviewed-by: Arthur Heymans &lt;arthur@aheymans.xyz&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>acpigen: Add printf-like function for debug string</title>
<updated>2023-05-16T12:22:32+00:00</updated>
<author>
<name>Cliff Huang</name>
<email>cliff.huang@intel.com</email>
</author>
<published>2023-02-18T08:17:26+00:00</published>
<link rel='alternate' type='text/html' href='http://91.123.203.49/cgit/delta/coreboot/coreboot.git/commit/?id=063a1b83f88bdfc090c60ebdfc111bc942958a1d'/>
<id>063a1b83f88bdfc090c60ebdfc111bc942958a1d</id>
<content type='text'>
Generate formatted string and ACPI code to print debug string.

For example (with pcie_rp = 1):

    acpigen_write_debug_sprintf("calling _ON for RP: %u", pcie_rp);

generates the following ACPI code:

    Debug = "calling _ON for RP: 1"

With this new function, the following functions are not needed anymore
and therefore are removed by this patch.

- acpigen_concatenate_string_string()
- acpigen_concatenate_string_int()
- acpigen_write_debug_concatenate_string_string()
- acpigen_write_debug_concatenate_string_int()

BRANCH=firmware-brya-14505.B
TEST=Add above functions in the acpigen code and check the generated
     SSDT table after OS boot. Check the debug messages is in the
     kernel log when /sys/modules/acpi/parameters/aml_debug_output is
     set to '1'.

Change-Id: Id4a42e5854516a22b7bc4559c2ed08680722c5ba
Signed-off-by: Cliff Huang &lt;cliff.huang@intel.com&gt;
Signed-off-by: Jeremy Compostella &lt;jeremy.compostella@intel.com&gt;
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73113
Tested-by: build bot (Jenkins) &lt;no-reply@coreboot.org&gt;
Reviewed-by: Bora Guvendik &lt;bora.guvendik@intel.com&gt;
Reviewed-by: Nico Huber &lt;nico.h@gmx.de&gt;
Reviewed-by: Zhixing Ma &lt;zhixing.ma@intel.com&gt;
Reviewed-by: Musse Abdullahi &lt;musse.abdullahi@intel.corp-partner.google.com&gt;
Reviewed-by: Angel Pons &lt;th3fanbus@gmail.com&gt;
Reviewed-by: Lean Sheng Tan &lt;sheng.tan@9elements.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Generate formatted string and ACPI code to print debug string.

For example (with pcie_rp = 1):

    acpigen_write_debug_sprintf("calling _ON for RP: %u", pcie_rp);

generates the following ACPI code:

    Debug = "calling _ON for RP: 1"

With this new function, the following functions are not needed anymore
and therefore are removed by this patch.

- acpigen_concatenate_string_string()
- acpigen_concatenate_string_int()
- acpigen_write_debug_concatenate_string_string()
- acpigen_write_debug_concatenate_string_int()

BRANCH=firmware-brya-14505.B
TEST=Add above functions in the acpigen code and check the generated
     SSDT table after OS boot. Check the debug messages is in the
     kernel log when /sys/modules/acpi/parameters/aml_debug_output is
     set to '1'.

Change-Id: Id4a42e5854516a22b7bc4559c2ed08680722c5ba
Signed-off-by: Cliff Huang &lt;cliff.huang@intel.com&gt;
Signed-off-by: Jeremy Compostella &lt;jeremy.compostella@intel.com&gt;
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73113
Tested-by: build bot (Jenkins) &lt;no-reply@coreboot.org&gt;
Reviewed-by: Bora Guvendik &lt;bora.guvendik@intel.com&gt;
Reviewed-by: Nico Huber &lt;nico.h@gmx.de&gt;
Reviewed-by: Zhixing Ma &lt;zhixing.ma@intel.com&gt;
Reviewed-by: Musse Abdullahi &lt;musse.abdullahi@intel.corp-partner.google.com&gt;
Reviewed-by: Angel Pons &lt;th3fanbus@gmail.com&gt;
Reviewed-by: Lean Sheng Tan &lt;sheng.tan@9elements.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>acpi/acpigen: add acpigen_resource_io to generate I/O resource</title>
<updated>2023-05-11T19:30:10+00:00</updated>
<author>
<name>Felix Held</name>
<email>felix-coreboot@felixheld.de</email>
</author>
<published>2023-05-09T14:18:51+00:00</published>
<link rel='alternate' type='text/html' href='http://91.123.203.49/cgit/delta/coreboot/coreboot.git/commit/?id=6695be65f331b3cc76189d828fbb14e2be95ab0d'/>
<id>6695be65f331b3cc76189d828fbb14e2be95ab0d</id>
<content type='text'>
Add the acpigen_resource_io helper function to generate an I/O range
resource.

Signed-off-by: Felix Held &lt;felix-coreboot@felixheld.de&gt;
Signed-off-by: Arthur Heymans &lt;arthur@aheymans.xyz&gt;
Change-Id: I177f59b52d4dbbff0a3ceeef5fc8c7455cef9ff8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75044
Tested-by: build bot (Jenkins) &lt;no-reply@coreboot.org&gt;
Reviewed-by: Tim Wawrzynczak &lt;inforichland@gmail.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add the acpigen_resource_io helper function to generate an I/O range
resource.

Signed-off-by: Felix Held &lt;felix-coreboot@felixheld.de&gt;
Signed-off-by: Arthur Heymans &lt;arthur@aheymans.xyz&gt;
Change-Id: I177f59b52d4dbbff0a3ceeef5fc8c7455cef9ff8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75044
Tested-by: build bot (Jenkins) &lt;no-reply@coreboot.org&gt;
Reviewed-by: Tim Wawrzynczak &lt;inforichland@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>acpi/acpigen: add acpigen_resource_bus_number to generate bus number</title>
<updated>2023-05-11T19:28:59+00:00</updated>
<author>
<name>Felix Held</name>
<email>felix-coreboot@felixheld.de</email>
</author>
<published>2023-05-09T14:10:35+00:00</published>
<link rel='alternate' type='text/html' href='http://91.123.203.49/cgit/delta/coreboot/coreboot.git/commit/?id=5a82f0d3a9124c2c7603cb971f3d4e9eb4a74246'/>
<id>5a82f0d3a9124c2c7603cb971f3d4e9eb4a74246</id>
<content type='text'>
Add the acpigen_resource_bus_number helper function to generate a bus
number range resource.

Signed-off-by: Felix Held &lt;felix-coreboot@felixheld.de&gt;
Signed-off-by: Arthur Heymans &lt;arthur@aheymans.xyz&gt;
Change-Id: Ib1f1da3dbe823c6bc4fc30c0622653410cfbf301
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75043
Tested-by: build bot (Jenkins) &lt;no-reply@coreboot.org&gt;
Reviewed-by: Tim Wawrzynczak &lt;inforichland@gmail.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add the acpigen_resource_bus_number helper function to generate a bus
number range resource.

Signed-off-by: Felix Held &lt;felix-coreboot@felixheld.de&gt;
Signed-off-by: Arthur Heymans &lt;arthur@aheymans.xyz&gt;
Change-Id: Ib1f1da3dbe823c6bc4fc30c0622653410cfbf301
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75043
Tested-by: build bot (Jenkins) &lt;no-reply@coreboot.org&gt;
Reviewed-by: Tim Wawrzynczak &lt;inforichland@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>drivers/pc80/rtc/mc146818rtc.c: Add Kconfig for RTC CMOS base addresses</title>
<updated>2023-05-08T17:51:08+00:00</updated>
<author>
<name>Jonathon Hall</name>
<email>jonathon.hall@puri.sm</email>
</author>
<published>2023-05-01T17:42:46+00:00</published>
<link rel='alternate' type='text/html' href='http://91.123.203.49/cgit/delta/coreboot/coreboot.git/commit/?id=78f8343c70551bdb8f2cc3716aed9f339a85530b'/>
<id>78f8343c70551bdb8f2cc3716aed9f339a85530b</id>
<content type='text'>
Configure the CMOS bank I/O base addresses with
PC_CMOS_BASE_PORT_BANK* rather than hard-coding as 0x70, 0x72.  The
defaults remain the same.

Change-Id: Ie44e5f5191c66f44e2df8ea0ff58a860be88bfcf
Signed-off-by: Jonathon Hall &lt;jonathon.hall@puri.sm&gt;
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74903
Reviewed-by: Kyösti Mälkki &lt;kyosti.malkki@gmail.com&gt;
Tested-by: build bot (Jenkins) &lt;no-reply@coreboot.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Configure the CMOS bank I/O base addresses with
PC_CMOS_BASE_PORT_BANK* rather than hard-coding as 0x70, 0x72.  The
defaults remain the same.

Change-Id: Ie44e5f5191c66f44e2df8ea0ff58a860be88bfcf
Signed-off-by: Jonathon Hall &lt;jonathon.hall@puri.sm&gt;
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74903
Reviewed-by: Kyösti Mälkki &lt;kyosti.malkki@gmail.com&gt;
Tested-by: build bot (Jenkins) &lt;no-reply@coreboot.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>acpi/acpigen: add acpigen_write_BBN to generate base bus number method</title>
<updated>2023-05-08T16:00:54+00:00</updated>
<author>
<name>Felix Held</name>
<email>felix-coreboot@felixheld.de</email>
</author>
<published>2023-05-04T21:00:06+00:00</published>
<link rel='alternate' type='text/html' href='http://91.123.203.49/cgit/delta/coreboot/coreboot.git/commit/?id=2d4112f76b004aa49ab8185cff4bd2313e01dff8'/>
<id>2d4112f76b004aa49ab8185cff4bd2313e01dff8</id>
<content type='text'>
Introduce acpigen_write_BBN to generate the ACPI method object that
returns the base bus number for a PCI(e) host bridge. When called, the
base_bus_number argument must be the first PCI bus number that got
assigned to the corresponding host bridge.

Signed-off-by: Felix Held &lt;felix-coreboot@felixheld.de&gt;
Change-Id: Ib67bf42b9c77c262d8a02d8f28ac5cb8482136b9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74991
Tested-by: build bot (Jenkins) &lt;no-reply@coreboot.org&gt;
Reviewed-by: Tim Wawrzynczak &lt;inforichland@gmail.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Introduce acpigen_write_BBN to generate the ACPI method object that
returns the base bus number for a PCI(e) host bridge. When called, the
base_bus_number argument must be the first PCI bus number that got
assigned to the corresponding host bridge.

Signed-off-by: Felix Held &lt;felix-coreboot@felixheld.de&gt;
Change-Id: Ib67bf42b9c77c262d8a02d8f28ac5cb8482136b9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74991
Tested-by: build bot (Jenkins) &lt;no-reply@coreboot.org&gt;
Reviewed-by: Tim Wawrzynczak &lt;inforichland@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>acpigen: Add a runtime method to override exposed _Sx sleep states</title>
<updated>2023-05-01T06:38:36+00:00</updated>
<author>
<name>Arthur Heymans</name>
<email>arthur@aheymans.xyz</email>
</author>
<published>2023-04-25T14:23:37+00:00</published>
<link rel='alternate' type='text/html' href='http://91.123.203.49/cgit/delta/coreboot/coreboot.git/commit/?id=0eb5974def63a2fc0dce6dfdad62b0b4c6f4b865'/>
<id>0eb5974def63a2fc0dce6dfdad62b0b4c6f4b865</id>
<content type='text'>
This allows mainboards to override available sleep states at runtime.
This is done by adding a IntObj in SSDT that DSDT consumes to override
the available _Sx states.

Signed-off-by: Arthur Heymans &lt;arthur@aheymans.xyz&gt;
Change-Id: Ic21830c1ef9c183b1e3005cc1f8b7daf7e9ea998
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74762
Reviewed-by: Nico Huber &lt;nico.h@gmx.de&gt;
Reviewed-by: Jakub Czapiga &lt;jacz@semihalf.com&gt;
Reviewed-by: Jan Samek &lt;jan.samek@siemens.com&gt;
Tested-by: build bot (Jenkins) &lt;no-reply@coreboot.org&gt;
Reviewed-by: Lean Sheng Tan &lt;sheng.tan@9elements.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This allows mainboards to override available sleep states at runtime.
This is done by adding a IntObj in SSDT that DSDT consumes to override
the available _Sx states.

Signed-off-by: Arthur Heymans &lt;arthur@aheymans.xyz&gt;
Change-Id: Ic21830c1ef9c183b1e3005cc1f8b7daf7e9ea998
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74762
Reviewed-by: Nico Huber &lt;nico.h@gmx.de&gt;
Reviewed-by: Jakub Czapiga &lt;jacz@semihalf.com&gt;
Reviewed-by: Jan Samek &lt;jan.samek@siemens.com&gt;
Tested-by: build bot (Jenkins) &lt;no-reply@coreboot.org&gt;
Reviewed-by: Lean Sheng Tan &lt;sheng.tan@9elements.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ACPI: Make FADT entries for RTC/CMOS architectural</title>
<updated>2023-04-29T01:20:54+00:00</updated>
<author>
<name>Kyösti Mälkki</name>
<email>kyosti.malkki@gmail.com</email>
</author>
<published>2023-04-17T12:20:40+00:00</published>
<link rel='alternate' type='text/html' href='http://91.123.203.49/cgit/delta/coreboot/coreboot.git/commit/?id=240baa31e8a804029069e21f523556d8628f6001'/>
<id>240baa31e8a804029069e21f523556d8628f6001</id>
<content type='text'>
For AMD, replace name RTC_ALT_CENTURY with RTC_CLK_ALTCENTURY
that points to same offset. Since the century field inside
RTC falls within the NVRAM space, and could interfere with
OPTION_TABLE, it is now guarded with config USE_PC_CMOS_ALTCENTURY.

There were no reference for the use of offset 0x48 for century.

Change-Id: I965a83dc8daaa02ad0935bdde5ca50110adb014a
Signed-off-by: Kyösti Mälkki &lt;kyosti.malkki@gmail.com&gt;
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74601
Reviewed-by: Elyes Haouas &lt;ehaouas@noos.fr&gt;
Tested-by: build bot (Jenkins) &lt;no-reply@coreboot.org&gt;
Reviewed-by: Felix Held &lt;felix-coreboot@felixheld.de&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
For AMD, replace name RTC_ALT_CENTURY with RTC_CLK_ALTCENTURY
that points to same offset. Since the century field inside
RTC falls within the NVRAM space, and could interfere with
OPTION_TABLE, it is now guarded with config USE_PC_CMOS_ALTCENTURY.

There were no reference for the use of offset 0x48 for century.

Change-Id: I965a83dc8daaa02ad0935bdde5ca50110adb014a
Signed-off-by: Kyösti Mälkki &lt;kyosti.malkki@gmail.com&gt;
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74601
Reviewed-by: Elyes Haouas &lt;ehaouas@noos.fr&gt;
Tested-by: build bot (Jenkins) &lt;no-reply@coreboot.org&gt;
Reviewed-by: Felix Held &lt;felix-coreboot@felixheld.de&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>vga: Change the arguments of vga_write_text to support extended ASCII</title>
<updated>2023-04-28T09:39:06+00:00</updated>
<author>
<name>Hsuan Ting Chen</name>
<email>roccochen@chromium.org</email>
</author>
<published>2023-02-20T03:49:35+00:00</published>
<link rel='alternate' type='text/html' href='http://91.123.203.49/cgit/delta/coreboot/coreboot.git/commit/?id=26a955507379f6933e4287fbbbae7b618657cf48'/>
<id>26a955507379f6933e4287fbbbae7b618657cf48</id>
<content type='text'>
VGA defined the extended ASCII set based on CP437, but the function
vga_write_text() accepts a signed char array.

This will cause unnecessary confusion that if we want to print u with
umlaut (code=129 in CP437), we need to explicitly cast it to -127 in
signed char.

Since we still want to leverage the built-in string utilities
which only accepts const char*, we still need to cast it to signed char
while processing, and cast it back to unsigned once we write into the
frame buffer.

BRANCH=brya
BUG=b:264666392
TEST=emerge-brya coreboot chromeos-bootimage

Signed-off-by: Hsuan Ting Chen &lt;roccochen@chromium.org&gt;
Change-Id: If555bbc05f40ce3f02339c0468afff6dda8b7ded
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73099
Tested-by: build bot (Jenkins) &lt;no-reply@coreboot.org&gt;
Reviewed-by: Tarun Tuli &lt;taruntuli@google.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
VGA defined the extended ASCII set based on CP437, but the function
vga_write_text() accepts a signed char array.

This will cause unnecessary confusion that if we want to print u with
umlaut (code=129 in CP437), we need to explicitly cast it to -127 in
signed char.

Since we still want to leverage the built-in string utilities
which only accepts const char*, we still need to cast it to signed char
while processing, and cast it back to unsigned once we write into the
frame buffer.

BRANCH=brya
BUG=b:264666392
TEST=emerge-brya coreboot chromeos-bootimage

Signed-off-by: Hsuan Ting Chen &lt;roccochen@chromium.org&gt;
Change-Id: If555bbc05f40ce3f02339c0468afff6dda8b7ded
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73099
Tested-by: build bot (Jenkins) &lt;no-reply@coreboot.org&gt;
Reviewed-by: Tarun Tuli &lt;taruntuli@google.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>arch/x86/ioapic: Promote ioapic_get_sci_pin()</title>
<updated>2023-04-26T10:53:16+00:00</updated>
<author>
<name>Kyösti Mälkki</name>
<email>kyosti.malkki@gmail.com</email>
</author>
<published>2023-04-10T14:03:32+00:00</published>
<link rel='alternate' type='text/html' href='http://91.123.203.49/cgit/delta/coreboot/coreboot.git/commit/?id=e742b68f1ac9324ce1f700323f1226e86d068a8c'/>
<id>e742b68f1ac9324ce1f700323f1226e86d068a8c</id>
<content type='text'>
Platform needs to implement this to provide information about SCI IRQ
pin and polarity, to be used for filling in ACPI FADT and MADT entries.

Change-Id: Icea7e9ca4abf3997c01617d2f78f25036d85a52f
Signed-off-by: Kyösti Mälkki &lt;kyosti.malkki@gmail.com&gt;
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74337
Tested-by: build bot (Jenkins) &lt;no-reply@coreboot.org&gt;
Reviewed-by: Arthur Heymans &lt;arthur@aheymans.xyz&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Platform needs to implement this to provide information about SCI IRQ
pin and polarity, to be used for filling in ACPI FADT and MADT entries.

Change-Id: Icea7e9ca4abf3997c01617d2f78f25036d85a52f
Signed-off-by: Kyösti Mälkki &lt;kyosti.malkki@gmail.com&gt;
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74337
Tested-by: build bot (Jenkins) &lt;no-reply@coreboot.org&gt;
Reviewed-by: Arthur Heymans &lt;arthur@aheymans.xyz&gt;
</pre>
</div>
</content>
</entry>
</feed>
