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* treewide: Add missing include guards to chip.hJan Samek2023-04-283-0/+15
* cpu/intel/speedstep: Separate single SSDT CPU entryKyösti Mälkki2023-04-261-35/+43
* cpu,soc/intel: Separate single SSDT CPU entryKyösti Mälkki2023-04-173-51/+60
* cpu,soc/intel: Sync ACPI CPU object implementationsKyösti Mälkki2023-04-143-31/+19
* cpu,soc/intel: Use acpigen_write_processor_device()Elyes Haouas2023-04-143-12/+12
* cpu/intel/speedstep: Refactor P-state coordinationKyösti Mälkki2023-04-141-7/+12
* intel/i82371eb,speedstep: Use dev_count_cpu()Kyösti Mälkki2023-04-141-13/+1
* arch/x86/include/cpu: introduce CPU_TABLE_END CPU table terminatorFelix Held2023-02-0915-17/+15
* cpu/intel/model_206ax/model_206ax_init: use CPUID_ALL_STEPPINGS_MASKFelix Held2023-02-081-10/+2
* arch/x86/cpu: introduce and use device_match_maskFelix Held2023-02-0815-103/+114
* mb/samsung: Enable VBOOT_VBNV_FLASHYu-Ping Wu2023-02-082-2/+0
* Add option to use Ada code in romstageJeremy Compostella2022-12-171-0/+13
* cpu/intel: Fix clearing MTRR for clang 64bitArthur Heymans2022-12-163-15/+18
* cpu/intel/206ax: Fix generating C state entriesArthur Heymans2022-12-141-1/+1
* cpu/intel/speedstep: Have nb and sb code provide c5/c6/slfmArthur Heymans2022-12-052-22/+3
* cpu/intel/model_206ax: Remove fake lapic deviceArthur Heymans2022-12-013-25/+6
* cpu/intel/sandybridge: Use enum for ACPI C statesArthur Heymans2022-12-011-3/+14
* aopen/dxplplusu: Support SMM_ASEG and SMM_TSEGKyösti Mälkki2022-11-284-37/+106
* cpu/intel/model_2065x: Don't use a magic APICArthur Heymans2022-11-252-13/+3
* cpu/intel/haswell: Move chip_ops to cpu clusterArthur Heymans2022-11-253-31/+15
* cpu/intel/car: Define post codesMartin Roth2022-11-236-49/+55
* src/cpu: Remove unnecessary space after castsElyes Haouas2022-11-221-1/+1
* cpu/intel/socket_*: Clean up Kconfig filesElyes Haouas2022-11-213-6/+10
* cpu/intel/socket_mPGA604: Drop non-working SSE2 disablementKyösti Mälkki2022-11-121-8/+0
* Revert "mb/aopen/dxplplusu: Remove board"Kyösti Mälkki2022-11-097-0/+127
* cpu/*: Drop PARALLEL_MP leftoversArthur Heymans2022-11-094-81/+0
* cpu: Include <cpu/cpu.h> instead of <arch/cpu.h>Elyes Haouas2022-11-0815-31/+33
* mb/aopen/dxplplusu: Remove boardArthur Heymans2022-11-077-107/+0
* cpu/intel/common: Fix typecasting issueSridhar Siricilla2022-10-281-1/+1
* mb/lenovo/haswell: Enable VBOOT_VBNV_FLASHYu-Ping Wu2022-10-271-1/+0
* cpu/intel: Clean up includesElyes Haouas2022-10-264-10/+12
* cpu/intel/common/fsb.c: Sorte includes and add <stdint.h>Elyes Haouas2022-10-061-4/+5
* cpu/intel/car/romstage.c: Clean up includes and add <types.h>Elyes Haouas2022-10-061-3/+3
* treewide: use is_enabled_cpu() on cycles over device listFabio Aiuto2022-09-291-5/+1
* cpu/intel/haswell: Update Broadwell ULT µcode updatesAngel Pons2022-09-201-1/+1
* cpu/intel/haswell: Hook up Crystal Well µcode updatesAngel Pons2022-09-201-0/+2
* cpu/intel/haswell: Do not include useless µcode updatesAngel Pons2022-09-201-2/+7
* cpu/intel/haswell: Allow up to six microcodes in the FIT tableJeremy Compostella2022-09-151-0/+3
* cpu: Get rid of unnecessary blank line {before,after} barceElyes HAOUAS2022-07-177-10/+0
* arch/x86: Mark prepare_and_run_postcar noreturnArthur Heymans2022-07-141-1/+0
* intel/microcode: Change log type from BIOS_ERR to BIOS_WARNINGSubrata Banik2022-06-261-2/+2
* microcode: Add error msg in case `intel_microcode_find()` return NULLSubrata Banik2022-06-221-1/+3
* cpu/intel/microcode: Create helper function to load microcode patchSubrata Banik2022-06-221-31/+26
* cpu/intel/microcode: Have API to re-load microcode patchSubrata Banik2022-06-221-0/+32
* cpu/intel/microcode: Fix `device enumeration` boot regressionSubrata Banik2022-06-171-7/+2
* arch/x86: Add a common romstage entryArthur Heymans2022-06-071-12/+3
* cpu/intel/microcode: Have provision to re-load microcode patchSubrata Banik2022-06-072-2/+17
* cpu/intel/model_fxx: Select SSE2Arthur Heymans2022-06-023-0/+3
* cbfs: Add CBFS_TYPE_INTEL_FIT and exclude it from CBFS verificationJulius Werner2022-06-011-2/+2
* arch/x86/postcar_loader.c: Change prepare_and_run_postcar signatureArthur Heymans2022-05-161-3/+1
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