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path: root/src/include/cpu/intel/speedstep.h
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* cpu/intel/speedstep: Have nb and sb code provide c5/c6/slfmArthur Heymans2022-12-051-3/+5
* src/include: Drop unneeded empty linesElyes HAOUAS2020-09-141-1/+0
* treewide: Remove "this file is part of" linesPatrick Georgi2020-05-111-1/+0
* src/include: Use SPDX for GPL-2.0-only filesAngel Pons2020-04-051-14/+2
* src (minus soc and mainboard): Remove copyright noticesPatrick Georgi2020-03-171-2/+0
* src: Move common IA-32 MSRs to <cpu/x86/msr.h>Elyes HAOUAS2018-10-111-5/+1
* src: Fix MSR_PKG_CST_CONFIG_CONTROL register nameElyes HAOUAS2018-10-051-1/+1
* intel: Use MSR_EBC_FREQUENCY_ID instead of 0x2cElyes HAOUAS2017-12-111-0/+1
* intel: Replace msr(0x198) with msr(IA32_PERF_STATUS)Elyes HAOUAS2017-11-301-1/+1
* cpu/intel: Add MSR to support enabling turbo frequencyShaunak Saha2016-11-091-1/+1
* tree: drop last paragraph of GPL copyright headerPatrick Georgi2015-10-311-4/+0
* Remove address from GPLv2 headersPatrick Georgi2015-05-211-2/+1
* acpi: Generate valid ACPI processor objectsTimothy Pearson2015-02-161-1/+1
* Drop prototype guarding for romccStefan Reinauer2013-05-101-2/+0
* Intel: Replace MSR 0xcd with MSR_FSB_FREQPatrick Georgi2013-02-111-0/+3
* speedstep: Deduplicate some MSR identifiersPatrick Georgi2013-02-091-0/+3
* Overhaul speedstep codeNico Huber2012-11-051-0/+74
* Merge cpu/intel/acpi.h into cpu/intel/speedstep.hNico Huber2012-11-011-0/+7
* Fixes and Sandybridge support for lapic cpu initStefan Reinauer2012-04-061-0/+3
* factor out cpu power management base into a separate file. And fix a bug inStefan Reinauer2010-12-111-0/+31
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