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| author | Chris Drake <cjdrake@gmail.com> | 2020-05-26 18:07:54 -0700 |
|---|---|---|
| committer | Chris Drake <cjdrake@gmail.com> | 2020-05-26 18:07:57 -0700 |
| commit | a3cf9b7b3b84d09cd6ba384366e0c1a57fc2a065 (patch) | |
| tree | 3009a7169e5f5b7f2348001459be871cd092317b | |
| parent | 00fe8d1d8910ce859b287829c169e5dd592ab411 (diff) | |
| download | pygments-git-a3cf9b7b3b84d09cd6ba384366e0c1a57fc2a065.tar.gz | |
Change Verilog 'wo' to 'wor'
There is no 'wo' keyword.
This was probably supposed to be 'wor', short for "wired OR".
| -rw-r--r-- | pygments/lexers/hdl.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/pygments/lexers/hdl.py b/pygments/lexers/hdl.py index 1472b5df..5a8cc264 100644 --- a/pygments/lexers/hdl.py +++ b/pygments/lexers/hdl.py @@ -105,7 +105,7 @@ class VerilogLexer(RegexLexer): (words(( 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'supply0', 'supply1', 'tri', 'triand', - 'trior', 'tri0', 'tri1', 'trireg', 'uwire', 'wire', 'wand', 'wo' + 'trior', 'tri0', 'tri1', 'trireg', 'uwire', 'wire', 'wand', 'wor' 'shortreal', 'real', 'realtime'), suffix=r'\b'), Keyword.Type), (r'[a-zA-Z_]\w*:(?!:)', Name.Label), |