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* all: fixup remaining regexlint warningsGeorg Brandl2020-09-061-2/+2
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* Update copyright year (fixes #1514.)Matthäus G. Chajdas2020-08-221-1/+1
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* Add Systemverilog Queue support #1496 (#1504)Kristof Mariën2020-08-051-1/+1
| | | Co-authored-by: Kristof Marien <kristof.marien@nokia.com>
* Improve SystemVerilog class/endclass lexer rules (#1471)Chris Drake2020-06-061-8/+10
| | | | | | | | | | | The class looks like: class class_identifier [#(param_decls)] [extends class_identifier #(params)]; ... endclass [: class_identifier] Using the same Java convention of Keyword.Declaration and Name.Class. Add a test_systemverilog_classes unit test to test_hdl.
* SystemVerilog keyword/operator improvements (#1464)Chris Drake2020-06-011-14/+20
| | | | | | | | | | | | | | | | | | | | | | | | | * Move SystemVerilog type keywords Put them next to the generic keywords list. * Change a couple SystemVerilog keywords to operators The 'inside' and 'dist' keywords are described as operators in the SystemVerilog standard, below unary increment/decrement, and above concatenation in precedence. See 1800-2017 tables 11-1 and 11-2 for a list of operators. This matches the description of pygemnts Operator.Word token: "For any operator that is a word (e.g. not)." * Add a SystemVerilog operators unit test Copy/paste the contents of 1800-2017 Table 11-2, and see what the SV lexer chops it up into. I made lots of comments for potential improvements. Some operators, such as '[' and '.' are being labeled as punctuation. Also, multi-character operators such as '<<<=' are being split up into multiple, single-character tokens, eg '<' '<' '<' '='.
* Change Verilog 'wo' to 'wor'Chris Drake2020-05-261-1/+1
| | | | | There is no 'wo' keyword. This was probably supposed to be 'wor', short for "wired OR".
* Update SystemVerilog literal constants (#1460)Chris Drake2020-05-261-6/+14
| | | | | | | | | | | | | | | | The original implementation was missing some of the more arcane features such as underbars, the character 's' for signed/unsigned, support for spaces before/after the base specifier, capital letter base specifiers (ie 'B 'D 'H), and the 4-state 'xXzZ?' characters. For regular integers, the 'l' and 'L' suffixes are not valid. That is, unlike C, in Verilog '42L' is not a valid int literal. Create a new test that exercises most of the interesting kinds of SystemVerilog numbers. This fixes a couple minor issues with what type of number the lexer returns. For example, Numbers like '42' used to return Integer.Hex, but now return Integer.Decimal.
* Fix a few SystemVerilog type keywords (#1454)Chris Drake2020-05-221-21/+25
| | | | | | | | | | | | | | | | | * Fix a few SystemVerilog type keywords First, add a few missing type keywords: chandle, const, event, string, time, type, var, void These are most of the 'variable' types listed in 1800-2017 6.8 "Variable declarations". Currently, this 'Keyword.Type' is not taking effect because the lexer is finding these keywords in the 'Keyword' list above. Remove the double declaration so we get the more specific token type. * Change signed/unsigned to Keyword.Type This is what the C/C++ lexer does, so it seems legit.
* Add support for (System)Verilog escaped identifiers.whitequark2020-05-041-0/+2
| | | | | | | The escaped identifiers start with a backslash, end with whitespace, and can include any character that is not whitespace. See IEEE 1364-2005 §3.7.1 and IEEE 1800-2017 §5.6.1.
* Add SystemVerilog (IEEE 1800-2012) keywords (#1436)Chris Drake2020-05-011-21/+82
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * Add SystemVerilog (IEEE 1800-2012) keywords See Table 22-6 -- IEEE 1800-2012 additional reserved keywords * implements * interconnect * nettype * soft * Add several SystemVerilog system tasks See IEEE 1800-2017 Chapter 20: "Utility system tasks and system functions". 20.2 : $exit $stop 20.3 : $realtime $stime $time 20.4 : $printtimescale $timeformat 20.5 : $bitstoreal $realtobits $bitstoshortreal $shortrealtobits $itor $rtoi $signed $unsigned $cast 20.6 : $bits $isunbounded $typename 20.7 : $unpacked_dimensions $dimensions $left $right $low $high $increment $size 20.8 : $clog2 $asin $ln $acos $log10 $atan $exp $atan2 $sqrt $hypot $pow $sinh $floor $cosh $ceil $tanh $sin $asinh $cos $acosh $tan $atanh 20.9 : $countbits $countones $onehot $onehot0 $isunknown 20.10: $fatal $error $warning $info 20.12: $asserton $assertoff $assertkill $assertcontrol $assertpasson $assertpassoff $assertfailon $assertfailoff $assertnonvacuouson $assertvacuousoff 20.13: $sampled $rose $fell $stable $changed $past $past_gclk $rose_gclk $fell_gclk $stable_gclk $changed_gclk $future_gclk $rising_gclk $falling_gclk $steady_gclk $changing_gclk 20.14: $coverage_control $coverage_get_max $coverage_get $coverage_merge $coverage_save $get_coverage $set_coverage_db_name $load_coverage_db 20.15: $dist_chi_square $dist_erlang $dist_exponential $dist_normal $dist_poisson $dist_t $dist_uniform 20.16: $q_initialize $q_add $q_remove $q_full $q_exam 20.17: $async$and$array $async$and$plane $async$nand$array $async$nand$plane $async$or$array $async$or$plane $async$nor$array $async$nor$plane $sync$and$array $sync$and$plane $sync$nand$array $sync$nand$plane $sync$or$array $sync$or$plane $sync$nor$array $sync$nor$plane 20.18: $system Also: * Replace '$test' '$plusargs' with '$test$plusargs'. * Add some comments for the remaining system tasks * Reorganize tasks into sections (w/ comments), according to spec Rather than just alphabetize this giant list, separate them into the sections by spec, then alphabetize within those sections. Hopefully, this will make it easier to extend in the future. * Fix typo: change 'wo' to 'wor' There is no 'wo' keyword. This was probably supposed to be 'wor', short for "wired OR".
* Verilog: get rid of "uppercase is constant" highlightingGeorg Brandl2019-11-241-66/+60
| | | | Seems quite arbitrary and has raised eyebrows (fixes #1204)
* Fixup all headers and some more minor problems.2.4.2Georg Brandl2019-05-281-1/+1
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* Copyright update.Georg Brandl2017-01-221-1/+1
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* Add support for partials and path segments for Handlebars.Christian Hammond2016-11-041-0/+382
This introduces support for some missing features to the Handlebars lexer: Partials and path segments. Partials mostly appeared to work before, but the `>` in `{{> ... }}` would appear as a syntax error, as could other components of the partial. This change introduces support for: * Standard partials: `{{> partialName}}` * Partials with parameters: `{{> partialName varname="value"}}` * Ddynamic partials: `{{> (partialFunc)}}` * Ddynamic partials with lookups: `{{> (lookup ../path "partialName")}}` * Partial blocks: `{{> @partial-block}}` * Inline partials: `{{#*inline}}..{{/inline}}` It also introduces support for path segments, which can reference content in the current context or in a parent context. For instance, `this.name`, `this/name`, `./name`, `../name`, `this/name`, etc. These are all now tracked as variables.