webkitgtk-2.4.11webkitgtk-2.4.11

1 files changed, 121 insertions, 811 deletions

diff --git a/Source/JavaScriptCore/assembler/X86Assembler.h b/Source/JavaScriptCore/assembler/X86Assembler.h
index 857d22ba6..1a43e206c 100644
--- a/Source/JavaScriptCore/assembler/X86Assembler.h
+++ b/Source/JavaScriptCore/assembler/X86Assembler.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2008, 2012-2016 Apple Inc. All rights reserved.
+ * Copyright (C) 2008, 2012, 2013 Apple Inc. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -29,103 +29,118 @@
 #if ENABLE(ASSEMBLER) && (CPU(X86) || CPU(X86_64))
 
 #include "AssemblerBuffer.h"
-#include "AssemblerCommon.h"
 #include "JITCompilationEffort.h"
 #include <limits.h>
 #include <stdint.h>
 #include <wtf/Assertions.h>
 #include <wtf/Vector.h>
 
+#if USE(MASM_PROBE)
+#include <xmmintrin.h>
+#endif
+
 namespace JSC {
 
 inline bool CAN_SIGN_EXTEND_8_32(int32_t value) { return value == (int32_t)(signed char)value; }
 
 namespace X86Registers {
+    typedef enum {
+        eax,
+        ecx,
+        edx,
+        ebx,
+        esp,
+        ebp,
+        esi,
+        edi,
 
-#define FOR_EACH_CPU_REGISTER(V) \
-    FOR_EACH_CPU_GPREGISTER(V) \
-    FOR_EACH_CPU_SPECIAL_REGISTER(V) \
-    FOR_EACH_CPU_FPREGISTER(V)
-
-// The following are defined as pairs of the following value:
-// 1. type of the storage needed to save the register value by the JIT probe.
-// 2. name of the register.
-#define FOR_EACH_CPU_GPREGISTER(V) \
-    V(void*, eax) \
-    V(void*, ecx) \
-    V(void*, edx) \
-    V(void*, ebx) \
-    V(void*, esp) \
-    V(void*, ebp) \
-    V(void*, esi) \
-    V(void*, edi) \
-    FOR_EACH_X86_64_CPU_GPREGISTER(V)
-
-#define FOR_EACH_CPU_SPECIAL_REGISTER(V) \
-    V(void*, eip) \
-    V(void*, eflags) \
-
-// Note: the JITs only stores double values in the FP registers.
-#define FOR_EACH_CPU_FPREGISTER(V) \
-    V(double, xmm0) \
-    V(double, xmm1) \
-    V(double, xmm2) \
-    V(double, xmm3) \
-    V(double, xmm4) \
-    V(double, xmm5) \
-    V(double, xmm6) \
-    V(double, xmm7) \
-    FOR_EACH_X86_64_CPU_FPREGISTER(V)
+#if CPU(X86_64)
+        r8,
+        r9,
+        r10,
+        r11,
+        r12,
+        r13,
+        r14,
+        r15,
+#endif
+    } RegisterID;
 
-#if CPU(X86)
+    typedef enum {
+        xmm0,
+        xmm1,
+        xmm2,
+        xmm3,
+        xmm4,
+        xmm5,
+        xmm6,
+        xmm7,
 
-#define FOR_EACH_X86_64_CPU_GPREGISTER(V) // Nothing to add.
-#define FOR_EACH_X86_64_CPU_FPREGISTER(V) // Nothing to add.
+#if CPU(X86_64)
+        xmm8,
+        xmm9,
+        xmm10,
+        xmm11,
+        xmm12,
+        xmm13,
+        xmm14,
+        xmm15,
+#endif
+    } XMMRegisterID;
+
+#if USE(MASM_PROBE)
+    #define FOR_EACH_CPU_REGISTER(V) \
+        FOR_EACH_CPU_GPREGISTER(V) \
+        FOR_EACH_CPU_SPECIAL_REGISTER(V) \
+        FOR_EACH_CPU_FPREGISTER(V)
+
+    #define FOR_EACH_CPU_GPREGISTER(V) \
+        V(void*, eax) \
+        V(void*, ebx) \
+        V(void*, ecx) \
+        V(void*, edx) \
+        V(void*, esi) \
+        V(void*, edi) \
+        V(void*, ebp) \
+        V(void*, esp) \
+        FOR_EACH_X86_64_CPU_GPREGISTER(V)
+
+    #define FOR_EACH_CPU_SPECIAL_REGISTER(V) \
+        V(void*, eip) \
+        V(void*, eflags) \
+
+    #define FOR_EACH_CPU_FPREGISTER(V) \
+        V(__m128, xmm0) \
+        V(__m128, xmm1) \
+        V(__m128, xmm2) \
+        V(__m128, xmm3) \
+        V(__m128, xmm4) \
+        V(__m128, xmm5) \
+        V(__m128, xmm6) \
+        V(__m128, xmm7)
 
+#if CPU(X86)
+    #define FOR_EACH_X86_64_CPU_GPREGISTER(V) // Nothing to add.
 #elif CPU(X86_64)
-
-#define FOR_EACH_X86_64_CPU_GPREGISTER(V) \
-    V(void*, r8) \
-    V(void*, r9) \
-    V(void*, r10) \
-    V(void*, r11) \
-    V(void*, r12) \
-    V(void*, r13) \
-    V(void*, r14) \
-    V(void*, r15)
-
-#define FOR_EACH_X86_64_CPU_FPREGISTER(V) \
-    V(double, xmm8) \
-    V(double, xmm9) \
-    V(double, xmm10) \
-    V(double, xmm11) \
-    V(double, xmm12) \
-    V(double, xmm13) \
-    V(double, xmm14) \
-    V(double, xmm15)
-
+    #define FOR_EACH_X86_64_CPU_GPREGISTER(V) \
+        V(void*, r8) \
+        V(void*, r9) \
+        V(void*, r10) \
+        V(void*, r11) \
+        V(void*, r12) \
+        V(void*, r13) \
+        V(void*, r14) \
+        V(void*, r15)
 #endif // CPU(X86_64)
-
-typedef enum {
-    #define DECLARE_REGISTER(_type, _regName) _regName,
-    FOR_EACH_CPU_GPREGISTER(DECLARE_REGISTER)
-    #undef DECLARE_REGISTER
-} RegisterID;
-
-typedef enum {
-    #define DECLARE_REGISTER(_type, _regName) _regName,
-    FOR_EACH_CPU_FPREGISTER(DECLARE_REGISTER)
-    #undef DECLARE_REGISTER
-} XMMRegisterID;
-
-} // namespace X86Register
+#endif // USE(MASM_PROBE)
+}
 
 class X86Assembler {
 public:
     typedef X86Registers::RegisterID RegisterID;
     
-    static constexpr RegisterID firstRegister() { return X86Registers::eax; }
-    static constexpr RegisterID lastRegister()
+    static RegisterID firstRegister() { return X86Registers::eax; }
+    static RegisterID lastRegister()
     {
 #if CPU(X86_64)
         return X86Registers::r15;
@@ -137,8 +152,8 @@ public:
     typedef X86Registers::XMMRegisterID XMMRegisterID;
     typedef XMMRegisterID FPRegisterID;
     
-    static constexpr FPRegisterID firstFPRegister() { return X86Registers::xmm0; }
-    static constexpr FPRegisterID lastFPRegister()
+    static FPRegisterID firstFPRegister() { return X86Registers::xmm0; }
+    static FPRegisterID lastFPRegister()
     {
 #if CPU(X86_64)
         return X86Registers::xmm15;
@@ -170,43 +185,21 @@ public:
     } Condition;
 
 private:
-    // OneByteOpcodeID defines the bytecode for 1 byte instruction. It also contains the prefixes
-    // for two bytes instructions.
-    // TwoByteOpcodeID, ThreeByteOpcodeID define the opcodes for the multibytes instructions.
-    //
-    // The encoding for each instruction can be found in the Intel Architecture Manual in the appendix
-    // "Opcode Map."
-    //
-    // Each opcode can have a suffix describing the type of argument. The full list of suffixes is
-    // in the "Key to Abbreviations" section of the "Opcode Map".
-    // The most common argument types are:
-    //     -E: The argument is either a GPR or a memory address.
-    //     -G: The argument is a GPR.
-    //     -I: The argument is an immediate.
-    // The most common sizes are:
-    //     -v: 32 or 64bit depending on the operand-size attribute.
-    //     -z: 32bit in both 32bit and 64bit mode. Common for immediate values.
     typedef enum {
-        OP_ADD_EbGb                     = 0x00,
         OP_ADD_EvGv                     = 0x01,
         OP_ADD_GvEv                     = 0x03,
-        OP_ADD_EAXIv                    = 0x05,
         OP_OR_EvGv                      = 0x09,
         OP_OR_GvEv                      = 0x0B,
-        OP_OR_EAXIv                     = 0x0D,
         OP_2BYTE_ESCAPE                 = 0x0F,
         OP_AND_EvGv                     = 0x21,
         OP_AND_GvEv                     = 0x23,
         OP_SUB_EvGv                     = 0x29,
         OP_SUB_GvEv                     = 0x2B,
-        OP_SUB_EAXIv                    = 0x2D,
         PRE_PREDICT_BRANCH_NOT_TAKEN    = 0x2E,
         OP_XOR_EvGv                     = 0x31,
         OP_XOR_GvEv                     = 0x33,
-        OP_XOR_EAXIv                    = 0x35,
         OP_CMP_EvGv                     = 0x39,
         OP_CMP_GvEv                     = 0x3B,
-        OP_CMP_EAXIv                    = 0x3D,
 #if CPU(X86_64)
         PRE_REX                         = 0x40,
 #endif
@@ -231,12 +224,9 @@ private:
         OP_LEA                          = 0x8D,
         OP_GROUP1A_Ev                   = 0x8F,
         OP_NOP                          = 0x90,
-        OP_XCHG_EAX                     = 0x90,
         OP_CDQ                          = 0x99,
         OP_MOV_EAXOv                    = 0xA1,
         OP_MOV_OvEAX                    = 0xA3,
-        OP_TEST_ALIb                    = 0xA8,
-        OP_TEST_EAXIv                   = 0xA9,
         OP_MOV_EAXIv                    = 0xB8,
         OP_GROUP2_EvIb                  = 0xC1,
         OP_RET                          = 0xC3,
@@ -245,7 +235,6 @@ private:
         OP_INT3                         = 0xCC,
         OP_GROUP2_Ev1                   = 0xD1,
         OP_GROUP2_EvCL                  = 0xD3,
-        OP_ESCAPE_D9                    = 0xD9,
         OP_ESCAPE_DD                    = 0xDD,
         OP_CALL_rel32                   = 0xE8,
         OP_JMP_rel32                    = 0xE9,
@@ -263,33 +252,25 @@ private:
         OP2_MOVSD_WsdVsd    = 0x11,
         OP2_MOVSS_VsdWsd    = 0x10,
         OP2_MOVSS_WsdVsd    = 0x11,
-        OP2_MOVAPD_VpdWpd   = 0x28,
-        OP2_MOVAPS_VpdWpd   = 0x28,
         OP2_CVTSI2SD_VsdEd  = 0x2A,
         OP2_CVTTSD2SI_GdWsd = 0x2C,
         OP2_UCOMISD_VsdWsd  = 0x2E,
-        OP2_3BYTE_ESCAPE_3A = 0x3A,
-        OP2_CMOVCC          = 0x40,
         OP2_ADDSD_VsdWsd    = 0x58,
         OP2_MULSD_VsdWsd    = 0x59,
         OP2_CVTSD2SS_VsdWsd = 0x5A,
         OP2_CVTSS2SD_VsdWsd = 0x5A,
         OP2_SUBSD_VsdWsd    = 0x5C,
         OP2_DIVSD_VsdWsd    = 0x5E,
-        OP2_MOVMSKPD_VdEd   = 0x50,
         OP2_SQRTSD_VsdWsd   = 0x51,
-        OP2_ANDPS_VpdWpd    = 0x54,
         OP2_ANDNPD_VpdWpd   = 0x55,
         OP2_XORPD_VpdWpd    = 0x57,
         OP2_MOVD_VdEd       = 0x6E,
         OP2_MOVD_EdVd       = 0x7E,
         OP2_JCC_rel32       = 0x80,
         OP_SETCC            = 0x90,
-        OP2_3BYTE_ESCAPE_AE = 0xAE,
+        OP2_3BYTE_ESCAPE    = 0xAE,
         OP2_IMUL_GvEv       = 0xAF,
         OP2_MOVZX_GvEb      = 0xB6,
-        OP2_BSR             = 0xBD,
-        OP2_LZCNT           = 0xBD,
         OP2_MOVSX_GvEb      = 0xBE,
         OP2_MOVZX_GvEw      = 0xB7,
         OP2_MOVSX_GvEw      = 0xBF,
@@ -300,17 +281,9 @@ private:
     } TwoByteOpcodeID;
     
     typedef enum {
-        OP3_ROUNDSS_VssWssIb = 0x0A,
-        OP3_ROUNDSD_VsdWsdIb = 0x0B,
-        OP3_MFENCE           = 0xF0,
+        OP3_MFENCE          = 0xF0,
     } ThreeByteOpcodeID;
 
-    
-    TwoByteOpcodeID cmovcc(Condition cond)
-    {
-        return (TwoByteOpcodeID)(OP2_CMOVCC + cond);
-    }
-
     TwoByteOpcodeID jccRel32(Condition cond)
     {
         return (TwoByteOpcodeID)(OP2_JCC_rel32 + cond);
@@ -344,7 +317,6 @@ private:
         GROUP3_OP_TEST = 0,
         GROUP3_OP_NOT  = 2,
         GROUP3_OP_NEG  = 3,
-        GROUP3_OP_DIV = 6,
         GROUP3_OP_IDIV = 7,
 
         GROUP5_OP_CALLN = 2,
@@ -356,7 +328,6 @@ private:
         GROUP14_OP_PSLLQ = 6,
         GROUP14_OP_PSRLQ = 2,
 
-        ESCAPE_D9_FSTP_singleReal = 3,
         ESCAPE_DD_FSTP_doubleReal = 3,
     } GroupOpcodeID;
     
@@ -436,43 +407,13 @@ public:
         m_formatter.oneByteOp(OP_ADD_EvGv, src, base, offset);
     }
 
-    void addl_rm(RegisterID src, int offset, RegisterID base, RegisterID index, int scale)
-    {
-        m_formatter.oneByteOp(OP_ADD_EvGv, src, base, index, scale, offset);
-    }
-
-    void addb_rm(RegisterID src, int offset, RegisterID base)
-    {
-        m_formatter.oneByteOp8(OP_ADD_EbGb, src, base, offset);
-    }
-
-    void addb_rm(RegisterID src, int offset, RegisterID base, RegisterID index, int scale)
-    {
-        m_formatter.oneByteOp8(OP_ADD_EbGb, src, base, index, scale, offset);
-    }
-
-    void addw_rm(RegisterID src, int offset, RegisterID base)
-    {
-        m_formatter.prefix(PRE_OPERAND_SIZE);
-        m_formatter.oneByteOp8(OP_ADD_EvGv, src, base, offset);
-    }
-
-    void addw_rm(RegisterID src, int offset, RegisterID base, RegisterID index, int scale)
-    {
-        m_formatter.prefix(PRE_OPERAND_SIZE);
-        m_formatter.oneByteOp8(OP_ADD_EvGv, src, base, index, scale, offset);
-    }
-
     void addl_ir(int imm, RegisterID dst)
     {
         if (CAN_SIGN_EXTEND_8_32(imm)) {
             m_formatter.oneByteOp(OP_GROUP1_EvIb, GROUP1_OP_ADD, dst);
             m_formatter.immediate8(imm);
         } else {
-            if (dst == X86Registers::eax)
-                m_formatter.oneByteOp(OP_ADD_EAXIv);
-            else
-                m_formatter.oneByteOp(OP_GROUP1_EvIz, GROUP1_OP_ADD, dst);
+            m_formatter.oneByteOp(OP_GROUP1_EvIz, GROUP1_OP_ADD, dst);
             m_formatter.immediate32(imm);
         }
     }
@@ -488,53 +429,6 @@ public:
         }
     }
 
-    void addl_im(int imm, int offset, RegisterID base, RegisterID index, int scale)
-    {
-        if (CAN_SIGN_EXTEND_8_32(imm)) {
-            m_formatter.oneByteOp(OP_GROUP1_EvIb, GROUP1_OP_ADD, base, index, scale, offset);
-            m_formatter.immediate8(imm);
-        } else {
-            m_formatter.oneByteOp(OP_GROUP1_EvIz, GROUP1_OP_ADD, base, index, scale, offset);
-            m_formatter.immediate32(imm);
-        }
-    }
-
-    void addb_im(int imm, int offset, RegisterID base)
-    {
-        m_formatter.oneByteOp8(OP_GROUP1_EbIb, GROUP1_OP_ADD, base, offset);
-        m_formatter.immediate8(imm);
-    }
-
-    void addb_im(int imm, int offset, RegisterID base, RegisterID index, int scale)
-    {
-        m_formatter.oneByteOp8(OP_GROUP1_EbIb, GROUP1_OP_ADD, base, index, scale, offset);
-        m_formatter.immediate8(imm);
-    }
-
-    void addw_im(int imm, int offset, RegisterID base)
-    {
-        m_formatter.prefix(PRE_OPERAND_SIZE);
-        if (CAN_SIGN_EXTEND_8_32(imm)) {
-            m_formatter.oneByteOp8(OP_GROUP1_EvIb, GROUP1_OP_ADD, base, offset);
-            m_formatter.immediate8(imm);
-        } else {
-            m_formatter.oneByteOp8(OP_GROUP1_EvIz, GROUP1_OP_ADD, base, offset);
-            m_formatter.immediate16(imm);
-        }
-    }
-
-    void addw_im(int imm, int offset, RegisterID base, RegisterID index, int scale)
-    {
-        m_formatter.prefix(PRE_OPERAND_SIZE);
-        if (CAN_SIGN_EXTEND_8_32(imm)) {
-            m_formatter.oneByteOp8(OP_GROUP1_EvIb, GROUP1_OP_ADD, base, index, scale, offset);
-            m_formatter.immediate8(imm);
-        } else {
-            m_formatter.oneByteOp8(OP_GROUP1_EvIz, GROUP1_OP_ADD, base, index, scale, offset);
-            m_formatter.immediate16(imm);
-        }
-    }
-
 #if CPU(X86_64)
     void addq_rr(RegisterID src, RegisterID dst)
     {
@@ -546,21 +440,13 @@ public:
         m_formatter.oneByteOp64(OP_ADD_GvEv, dst, base, offset);
     }
 
-    void addq_rm(RegisterID src, int offset, RegisterID base)
-    {
-        m_formatter.oneByteOp64(OP_ADD_EvGv, src, base, offset);
-    }
-
     void addq_ir(int imm, RegisterID dst)
     {
         if (CAN_SIGN_EXTEND_8_32(imm)) {
             m_formatter.oneByteOp64(OP_GROUP1_EvIb, GROUP1_OP_ADD, dst);
             m_formatter.immediate8(imm);
         } else {
-            if (dst == X86Registers::eax)
-                m_formatter.oneByteOp64(OP_ADD_EAXIv);
-            else
-                m_formatter.oneByteOp64(OP_GROUP1_EvIz, GROUP1_OP_ADD, dst);
+            m_formatter.oneByteOp64(OP_GROUP1_EvIz, GROUP1_OP_ADD, dst);
             m_formatter.immediate32(imm);
         }
     }
@@ -676,11 +562,6 @@ public:
     {
         m_formatter.oneByteOp64(OP_GROUP5_Ev, GROUP1_OP_ADD, dst);
     }
-
-    void incq_m(int offset, RegisterID base)
-    {
-        m_formatter.oneByteOp64(OP_GROUP5_Ev, GROUP1_OP_ADD, base, offset);
-    }
 #endif // CPU(X86_64)
 
     void negl_r(RegisterID dst)
@@ -710,18 +591,6 @@ public:
         m_formatter.oneByteOp(OP_GROUP3_Ev, GROUP3_OP_NOT, base, offset);
     }
 
-#if CPU(X86_64)
-    void notq_r(RegisterID dst)
-    {
-        m_formatter.oneByteOp64(OP_GROUP3_Ev, GROUP3_OP_NOT, dst);
-    }
-
-    void notq_m(int offset, RegisterID base)
-    {
-        m_formatter.oneByteOp64(OP_GROUP3_Ev, GROUP3_OP_NOT, base, offset);
-    }
-#endif
-
     void orl_rr(RegisterID src, RegisterID dst)
     {
         m_formatter.oneByteOp(OP_OR_EvGv, src, dst);
@@ -743,10 +612,7 @@ public:
             m_formatter.oneByteOp(OP_GROUP1_EvIb, GROUP1_OP_OR, dst);
             m_formatter.immediate8(imm);
         } else {
-            if (dst == X86Registers::eax)
-                m_formatter.oneByteOp(OP_OR_EAXIv);
-            else
-                m_formatter.oneByteOp(OP_GROUP1_EvIz, GROUP1_OP_OR, dst);
+            m_formatter.oneByteOp(OP_GROUP1_EvIz, GROUP1_OP_OR, dst);
             m_formatter.immediate32(imm);
         }
     }
@@ -774,10 +640,7 @@ public:
             m_formatter.oneByteOp64(OP_GROUP1_EvIb, GROUP1_OP_OR, dst);
             m_formatter.immediate8(imm);
         } else {
-            if (dst == X86Registers::eax)
-                m_formatter.oneByteOp64(OP_OR_EAXIv);
-            else
-                m_formatter.oneByteOp64(OP_GROUP1_EvIz, GROUP1_OP_OR, dst);
+            m_formatter.oneByteOp64(OP_GROUP1_EvIz, GROUP1_OP_OR, dst);
             m_formatter.immediate32(imm);
         }
     }
@@ -820,10 +683,7 @@ public:
             m_formatter.oneByteOp(OP_GROUP1_EvIb, GROUP1_OP_SUB, dst);
             m_formatter.immediate8(imm);
         } else {
-            if (dst == X86Registers::eax)
-                m_formatter.oneByteOp(OP_SUB_EAXIv);
-            else
-                m_formatter.oneByteOp(OP_GROUP1_EvIz, GROUP1_OP_SUB, dst);
+            m_formatter.oneByteOp(OP_GROUP1_EvIz, GROUP1_OP_SUB, dst);
             m_formatter.immediate32(imm);
         }
     }
@@ -845,37 +705,13 @@ public:
         m_formatter.oneByteOp64(OP_SUB_EvGv, src, dst);
     }
 
-    void subq_mr(int offset, RegisterID base, RegisterID dst)
-    {
-        m_formatter.oneByteOp64(OP_SUB_GvEv, dst, base, offset);
-    }
-
-    void subq_rm(RegisterID src, int offset, RegisterID base)
-    {
-        m_formatter.oneByteOp64(OP_SUB_EvGv, src, base, offset);
-    }
-
     void subq_ir(int imm, RegisterID dst)
     {
         if (CAN_SIGN_EXTEND_8_32(imm)) {
             m_formatter.oneByteOp64(OP_GROUP1_EvIb, GROUP1_OP_SUB, dst);
             m_formatter.immediate8(imm);
         } else {
-            if (dst == X86Registers::eax)
-                m_formatter.oneByteOp64(OP_SUB_EAXIv);
-            else
-                m_formatter.oneByteOp64(OP_GROUP1_EvIz, GROUP1_OP_SUB, dst);
-            m_formatter.immediate32(imm);
-        }
-    }
-
-    void subq_im(int imm, int offset, RegisterID base)
-    {
-        if (CAN_SIGN_EXTEND_8_32(imm)) {
-            m_formatter.oneByteOp64(OP_GROUP1_EvIb, GROUP1_OP_SUB, base, offset);
-            m_formatter.immediate8(imm);
-        } else {
-            m_formatter.oneByteOp64(OP_GROUP1_EvIz, GROUP1_OP_SUB, base, offset);
+            m_formatter.oneByteOp64(OP_GROUP1_EvIz, GROUP1_OP_SUB, dst);
             m_formatter.immediate32(imm);
         }
     }
@@ -924,10 +760,7 @@ public:
             m_formatter.oneByteOp(OP_GROUP1_EvIb, GROUP1_OP_XOR, dst);
             m_formatter.immediate8(imm);
         } else {
-            if (dst == X86Registers::eax)
-                m_formatter.oneByteOp(OP_XOR_EAXIv);
-            else
-                m_formatter.oneByteOp(OP_GROUP1_EvIz, GROUP1_OP_XOR, dst);
+            m_formatter.oneByteOp(OP_GROUP1_EvIz, GROUP1_OP_XOR, dst);
             m_formatter.immediate32(imm);
         }
     }
@@ -944,10 +777,7 @@ public:
             m_formatter.oneByteOp64(OP_GROUP1_EvIb, GROUP1_OP_XOR, dst);
             m_formatter.immediate8(imm);
         } else {
-            if (dst == X86Registers::eax)
-                m_formatter.oneByteOp64(OP_XOR_EAXIv);
-            else
-                m_formatter.oneByteOp64(OP_GROUP1_EvIz, GROUP1_OP_XOR, dst);
+            m_formatter.oneByteOp64(OP_GROUP1_EvIz, GROUP1_OP_XOR, dst);
             m_formatter.immediate32(imm);
         }
     }
@@ -969,54 +799,6 @@ public:
 
 #endif
 
-    void lzcnt_rr(RegisterID src, RegisterID dst)
-    {
-        m_formatter.prefix(PRE_SSE_F3);
-        m_formatter.twoByteOp(OP2_LZCNT, dst, src);
-    }
-
-    void lzcnt_mr(int offset, RegisterID base, RegisterID dst)
-    {
-        m_formatter.prefix(PRE_SSE_F3);
-        m_formatter.twoByteOp(OP2_LZCNT, dst, base, offset);
-    }
-
-#if CPU(X86_64)
-    void lzcntq_rr(RegisterID src, RegisterID dst)
-    {
-        m_formatter.prefix(PRE_SSE_F3);
-        m_formatter.twoByteOp64(OP2_LZCNT, dst, src);
-    }
-
-    void lzcntq_mr(int offset, RegisterID base, RegisterID dst)
-    {
-        m_formatter.prefix(PRE_SSE_F3);
-        m_formatter.twoByteOp64(OP2_LZCNT, dst, base, offset);
-    }
-#endif
-
-    void bsr_rr(RegisterID src, RegisterID dst)
-    {
-        m_formatter.twoByteOp(OP2_BSR, dst, src);
-    }
-
-    void bsr_mr(int offset, RegisterID base, RegisterID dst)
-    {
-        m_formatter.twoByteOp(OP2_BSR, dst, base, offset);
-    }
-
-#if CPU(X86_64)
-    void bsrq_rr(RegisterID src, RegisterID dst)
-    {
-        m_formatter.twoByteOp64(OP2_BSR, dst, src);
-    }
-
-    void bsrq_mr(int offset, RegisterID base, RegisterID dst)
-    {
-        m_formatter.twoByteOp64(OP2_BSR, dst, base, offset);
-    }
-#endif
-
     void sarl_i8r(int imm, RegisterID dst)
     {
         if (imm == 1)
@@ -1078,21 +860,6 @@ public:
         }
     }
 
-    void shrq_i8r(int imm, RegisterID dst)
-    {
-        if (imm == 1)
-            m_formatter.oneByteOp64(OP_GROUP2_Ev1, GROUP2_OP_SHR, dst);
-        else {
-            m_formatter.oneByteOp64(OP_GROUP2_EvIb, GROUP2_OP_SHR, dst);
-            m_formatter.immediate8(imm);
-        }
-    }
-
-    void shrq_CLr(RegisterID dst)
-    {
-        m_formatter.oneByteOp64(OP_GROUP2_EvCL, GROUP2_OP_SHR, dst);
-    }
-
     void shlq_i8r(int imm, RegisterID dst)
     {
         if (imm == 1)
@@ -1102,11 +869,6 @@ public:
             m_formatter.immediate8(imm);
         }
     }
-
-    void shlq_CLr(RegisterID dst)
-    {
-        m_formatter.oneByteOp64(OP_GROUP2_EvCL, GROUP2_OP_SHL, dst);
-    }
 #endif // CPU(X86_64)
 
     void imull_rr(RegisterID src, RegisterID dst)
@@ -1132,23 +894,11 @@ public:
         m_formatter.immediate32(value);
     }
 
-    void divl_r(RegisterID dst)
-    {
-        m_formatter.oneByteOp(OP_GROUP3_Ev, GROUP3_OP_DIV, dst);
-    }
-
     void idivl_r(RegisterID dst)
     {
         m_formatter.oneByteOp(OP_GROUP3_Ev, GROUP3_OP_IDIV, dst);
     }
 
-#if CPU(X86_64)
-    void idivq_r(RegisterID dst)
-    {
-        m_formatter.oneByteOp64(OP_GROUP3_Ev, GROUP3_OP_IDIV, dst);
-    }
-#endif // CPU(X86_64)
-
     // Comparisons:
 
     void cmpl_rr(RegisterID src, RegisterID dst)
@@ -1172,10 +922,7 @@ public:
             m_formatter.oneByteOp(OP_GROUP1_EvIb, GROUP1_OP_CMP, dst);
             m_formatter.immediate8(imm);
         } else {
-            if (dst == X86Registers::eax)
-                m_formatter.oneByteOp(OP_CMP_EAXIv);
-            else
-                m_formatter.oneByteOp(OP_GROUP1_EvIz, GROUP1_OP_CMP, dst);
+            m_formatter.oneByteOp(OP_GROUP1_EvIz, GROUP1_OP_CMP, dst);
             m_formatter.immediate32(imm);
         }
     }
@@ -1261,10 +1008,7 @@ public:
             m_formatter.oneByteOp64(OP_GROUP1_EvIb, GROUP1_OP_CMP, dst);
             m_formatter.immediate8(imm);
         } else {
-            if (dst == X86Registers::eax)
-                m_formatter.oneByteOp64(OP_CMP_EAXIv);
-            else
-                m_formatter.oneByteOp64(OP_GROUP1_EvIz, GROUP1_OP_CMP, dst);
+            m_formatter.oneByteOp64(OP_GROUP1_EvIz, GROUP1_OP_CMP, dst);
             m_formatter.immediate32(imm);
         }
     }
@@ -1347,10 +1091,7 @@ public:
     
     void testl_i32r(int imm, RegisterID dst)
     {
-        if (dst == X86Registers::eax)
-            m_formatter.oneByteOp(OP_TEST_EAXIv);
-        else
-            m_formatter.oneByteOp(OP_GROUP3_EvIz, GROUP3_OP_TEST, dst);
+        m_formatter.oneByteOp(OP_GROUP3_EvIz, GROUP3_OP_TEST, dst);
         m_formatter.immediate32(imm);
     }
 
@@ -1404,10 +1145,7 @@ public:
 
     void testq_i32r(int imm, RegisterID dst)
     {
-        if (dst == X86Registers::eax)
-            m_formatter.oneByteOp64(OP_TEST_EAXIv);
-        else
-            m_formatter.oneByteOp64(OP_GROUP3_EvIz, GROUP3_OP_TEST, dst);
+        m_formatter.oneByteOp64(OP_GROUP3_EvIz, GROUP3_OP_TEST, dst);
         m_formatter.immediate32(imm);
     }
 
@@ -1432,10 +1170,7 @@ public:
     
     void testb_i8r(int imm, RegisterID dst)
     {
-        if (dst == X86Registers::eax)
-            m_formatter.oneByteOp(OP_TEST_ALIb);
-        else
-            m_formatter.oneByteOp8(OP_GROUP3_EbIb, GROUP3_OP_TEST, dst);
+        m_formatter.oneByteOp8(OP_GROUP3_EbIb, GROUP3_OP_TEST, dst);
         m_formatter.immediate8(imm);
     }
 
@@ -1464,16 +1199,6 @@ public:
         setne_r(dst);
     }
 
-    void setnp_r(RegisterID dst)
-    {
-        m_formatter.twoByteOp8(setccOpcode(ConditionNP), (GroupOpcodeID)0, dst);
-    }
-
-    void setp_r(RegisterID dst)
-    {
-        m_formatter.twoByteOp8(setccOpcode(ConditionP), (GroupOpcodeID)0, dst);
-    }
-
     // Various move ops:
 
     void cdq()
@@ -1481,18 +1206,6 @@ public:
         m_formatter.oneByteOp(OP_CDQ);
     }
 
-#if CPU(X86_64)
-    void cqo()
-    {
-        m_formatter.oneByteOp64(OP_CDQ);
-    }
-#endif
-
-    void fstps(int offset, RegisterID base)
-    {
-        m_formatter.oneByteOp(OP_ESCAPE_D9, ESCAPE_D9_FSTP_singleReal, base, offset);
-    }
-
     void fstpl(int offset, RegisterID base)
     {
         m_formatter.oneByteOp(OP_ESCAPE_DD, ESCAPE_DD_FSTP_doubleReal, base, offset);
@@ -1500,33 +1213,13 @@ public:
 
     void xchgl_rr(RegisterID src, RegisterID dst)
     {
-        if (src == X86Registers::eax)
-            m_formatter.oneByteOp(OP_XCHG_EAX, dst);
-        else if (dst == X86Registers::eax)
-            m_formatter.oneByteOp(OP_XCHG_EAX, src);
-        else
-            m_formatter.oneByteOp(OP_XCHG_EvGv, src, dst);
-    }
-
-    void xchgl_rm(RegisterID src, int offset, RegisterID base)
-    {
-        m_formatter.oneByteOp(OP_XCHG_EvGv, src, base, offset);
+        m_formatter.oneByteOp(OP_XCHG_EvGv, src, dst);
     }
 
 #if CPU(X86_64)
     void xchgq_rr(RegisterID src, RegisterID dst)
     {
-        if (src == X86Registers::eax)
-            m_formatter.oneByteOp64(OP_XCHG_EAX, dst);
-        else if (dst == X86Registers::eax)
-            m_formatter.oneByteOp64(OP_XCHG_EAX, src);
-        else
-            m_formatter.oneByteOp64(OP_XCHG_EvGv, src, dst);
-    }
-
-    void xchgq_rm(RegisterID src, int offset, RegisterID base)
-    {
-        m_formatter.oneByteOp64(OP_XCHG_EvGv, src, base, offset);
+        m_formatter.oneByteOp64(OP_XCHG_EvGv, src, dst);
     }
 #endif
 
@@ -1637,16 +1330,7 @@ public:
     {
         m_formatter.oneByteOp8(OP_MOV_EbGb, src, base, index, scale, offset);
     }
-
-    void movw_rm(RegisterID src, int offset, RegisterID base)
-    {
-        m_formatter.prefix(PRE_OPERAND_SIZE);
-
-        // FIXME: We often use oneByteOp8 for 16-bit operations. It's not clear that this is
-        // necessary. https://bugs.webkit.org/show_bug.cgi?id=153433
-        m_formatter.oneByteOp8(OP_MOV_EvGv, src, base, offset);
-    }
-
+    
     void movw_rm(RegisterID src, int offset, RegisterID base, RegisterID index, int scale)
     {
         m_formatter.prefix(PRE_OPERAND_SIZE);
@@ -1727,12 +1411,6 @@ public:
         m_formatter.oneByteOp64(OP_MOV_EAXIv, dst);
         m_formatter.immediate64(imm);
     }
-
-    void mov_i32r(int32_t imm, RegisterID dst)
-    {
-        m_formatter.oneByteOp64(OP_GROUP11_EvIz, GROUP11_MOV, dst);
-        m_formatter.immediate32(imm);
-    }
     
     void movsxd_rr(RegisterID src, RegisterID dst)
     {
@@ -1819,118 +1497,15 @@ public:
         m_formatter.twoByteOp8(OP2_MOVZX_GvEb, dst, src);
     }
 
-    void movsbl_rr(RegisterID src, RegisterID dst)
-    {
-        m_formatter.twoByteOp8(OP2_MOVSX_GvEb, dst, src);
-    }
-
-    void movzwl_rr(RegisterID src, RegisterID dst)
-    {
-        m_formatter.twoByteOp8(OP2_MOVZX_GvEw, dst, src);
-    }
-
-    void movswl_rr(RegisterID src, RegisterID dst)
-    {
-        m_formatter.twoByteOp8(OP2_MOVSX_GvEw, dst, src);
-    }
-
-    void cmovl_rr(Condition cond, RegisterID src, RegisterID dst)
-    {
-        m_formatter.twoByteOp(cmovcc(cond), dst, src);
-    }
-
-    void cmovl_mr(Condition cond, int offset, RegisterID base, RegisterID dst)
-    {
-        m_formatter.twoByteOp(cmovcc(cond), dst, base, offset);
-    }
-
-    void cmovl_mr(Condition cond, int offset, RegisterID base, RegisterID index, int scale, RegisterID dst)
-    {
-        m_formatter.twoByteOp(cmovcc(cond), dst, base, index, scale, offset);
-    }
-
-    void cmovel_rr(RegisterID src, RegisterID dst)
-    {
-        m_formatter.twoByteOp(cmovcc(ConditionE), dst, src);
-    }
-    
-    void cmovnel_rr(RegisterID src, RegisterID dst)
-    {
-        m_formatter.twoByteOp(cmovcc(ConditionNE), dst, src);
-    }
-    
-    void cmovpl_rr(RegisterID src, RegisterID dst)
-    {
-        m_formatter.twoByteOp(cmovcc(ConditionP), dst, src);
-    }
-    
-    void cmovnpl_rr(RegisterID src, RegisterID dst)
-    {
-        m_formatter.twoByteOp(cmovcc(ConditionNP), dst, src);
-    }
-
-#if CPU(X86_64)
-    void cmovq_rr(Condition cond, RegisterID src, RegisterID dst)
-    {
-        m_formatter.twoByteOp64(cmovcc(cond), dst, src);
-    }
-
-    void cmovq_mr(Condition cond, int offset, RegisterID base, RegisterID dst)
-    {
-        m_formatter.twoByteOp64(cmovcc(cond), dst, base, offset);
-    }
-
-    void cmovq_mr(Condition cond, int offset, RegisterID base, RegisterID index, int scale, RegisterID dst)
-    {
-        m_formatter.twoByteOp64(cmovcc(cond), dst, base, index, scale, offset);
-    }
-
-    void cmoveq_rr(RegisterID src, RegisterID dst)
-    {
-        m_formatter.twoByteOp64(cmovcc(ConditionE), dst, src);
-    }
-
-    void cmovneq_rr(RegisterID src, RegisterID dst)
-    {
-        m_formatter.twoByteOp64(cmovcc(ConditionNE), dst, src);
-    }
-
-    void cmovpq_rr(RegisterID src, RegisterID dst)
-    {
-        m_formatter.twoByteOp64(cmovcc(ConditionP), dst, src);
-    }
-
-    void cmovnpq_rr(RegisterID src, RegisterID dst)
-    {
-        m_formatter.twoByteOp64(cmovcc(ConditionNP), dst, src);
-    }
-#else
-    void cmovl_mr(Condition cond, const void* addr, RegisterID dst)
-    {
-        m_formatter.twoByteOp(cmovcc(cond), dst, addr);
-    }
-#endif
-
     void leal_mr(int offset, RegisterID base, RegisterID dst)
     {
         m_formatter.oneByteOp(OP_LEA, dst, base, offset);
     }
-
-    void leal_mr(int offset, RegisterID base, RegisterID index, int scale, RegisterID dst)
-    {
-        m_formatter.oneByteOp(OP_LEA, dst, base, index, scale, offset);
-    }
-
 #if CPU(X86_64)
     void leaq_mr(int offset, RegisterID base, RegisterID dst)
     {
         m_formatter.oneByteOp64(OP_LEA, dst, base, offset);
     }
-
-    void leaq_mr(int offset, RegisterID base, RegisterID index, int scale, RegisterID dst)
-    {
-        m_formatter.oneByteOp64(OP_LEA, dst, base, index, scale, offset);
-    }
 #endif
 
     // Flow control:
@@ -2093,18 +1668,6 @@ public:
         m_formatter.twoByteOp(OP2_ADDSD_VsdWsd, (RegisterID)dst, base, offset);
     }
 
-    void addss_rr(XMMRegisterID src, XMMRegisterID dst)
-    {
-        m_formatter.prefix(PRE_SSE_F3);
-        m_formatter.twoByteOp(OP2_ADDSD_VsdWsd, (RegisterID)dst, (RegisterID)src);
-    }
-
-    void addss_mr(int offset, RegisterID base, XMMRegisterID dst)
-    {
-        m_formatter.prefix(PRE_SSE_F3);
-        m_formatter.twoByteOp(OP2_ADDSD_VsdWsd, (RegisterID)dst, base, offset);
-    }
-
 #if !CPU(X86_64)
     void addsd_mr(const void* address, XMMRegisterID dst)
     {
@@ -2153,24 +1716,12 @@ public:
         m_formatter.twoByteOp(OP2_CVTSD2SS_VsdWsd, dst, (RegisterID)src);
     }
 
-    void cvtsd2ss_mr(int offset, RegisterID base, XMMRegisterID dst)
-    {
-        m_formatter.prefix(PRE_SSE_F2);
-        m_formatter.twoByteOp(OP2_CVTSD2SS_VsdWsd, dst, base, offset);
-    }
-
     void cvtss2sd_rr(XMMRegisterID src, XMMRegisterID dst)
     {
         m_formatter.prefix(PRE_SSE_F3);
         m_formatter.twoByteOp(OP2_CVTSS2SD_VsdWsd, dst, (RegisterID)src);
     }
-
-    void cvtss2sd_mr(int offset, RegisterID base, XMMRegisterID dst)
-    {
-        m_formatter.prefix(PRE_SSE_F3);
-        m_formatter.twoByteOp(OP2_CVTSS2SD_VsdWsd, dst, base, offset);
-    }
-
+    
 #if CPU(X86_64)
     void cvttsd2siq_rr(XMMRegisterID src, RegisterID dst)
     {
@@ -2192,12 +1743,6 @@ public:
     }
 
 #if CPU(X86_64)
-    void movmskpd_rr(XMMRegisterID src, RegisterID dst)
-    {
-        m_formatter.prefix(PRE_SSE_66);
-        m_formatter.twoByteOp64(OP2_MOVMSKPD_VdEd, dst, (RegisterID)src);
-    }
-
     void movq_rr(XMMRegisterID src, RegisterID dst)
     {
         m_formatter.prefix(PRE_SSE_66);
@@ -2211,17 +1756,6 @@ public:
     }
 #endif
 
-    void movapd_rr(XMMRegisterID src, XMMRegisterID dst)
-    {
-        m_formatter.prefix(PRE_SSE_66);
-        m_formatter.twoByteOp(OP2_MOVAPD_VpdWpd, (RegisterID)dst, (RegisterID)src);
-    }
-
-    void movaps_rr(XMMRegisterID src, XMMRegisterID dst)
-    {
-        m_formatter.twoByteOp(OP2_MOVAPS_VpdWpd, (RegisterID)dst, (RegisterID)src);
-    }
-
     void movsd_rr(XMMRegisterID src, XMMRegisterID dst)
     {
         m_formatter.prefix(PRE_SSE_F2);
@@ -2239,12 +1773,6 @@ public:
         m_formatter.prefix(PRE_SSE_F2);
         m_formatter.twoByteOp(OP2_MOVSD_WsdVsd, (RegisterID)src, base, index, scale, offset);
     }
-
-    void movss_rm(XMMRegisterID src, int offset, RegisterID base)
-    {
-        m_formatter.prefix(PRE_SSE_F3);
-        m_formatter.twoByteOp(OP2_MOVSD_WsdVsd, (RegisterID)src, base, offset);
-    }
     
     void movss_rm(XMMRegisterID src, int offset, RegisterID base, RegisterID index, int scale)
     {
@@ -2263,13 +1791,7 @@ public:
         m_formatter.prefix(PRE_SSE_F2);
         m_formatter.twoByteOp(OP2_MOVSD_VsdWsd, dst, base, index, scale, offset);
     }
-
-    void movss_mr(int offset, RegisterID base, XMMRegisterID dst)
-    {
-        m_formatter.prefix(PRE_SSE_F3);
-        m_formatter.twoByteOp(OP2_MOVSD_VsdWsd, (RegisterID)dst, base, offset);
-    }
-
+    
     void movss_mr(int offset, RegisterID base, RegisterID index, int scale, XMMRegisterID dst)
     {
         m_formatter.prefix(PRE_SSE_F3);
@@ -2301,18 +1823,6 @@ public:
         m_formatter.twoByteOp(OP2_MULSD_VsdWsd, (RegisterID)dst, base, offset);
     }
 
-    void mulss_rr(XMMRegisterID src, XMMRegisterID dst)
-    {
-        m_formatter.prefix(PRE_SSE_F3);
-        m_formatter.twoByteOp(OP2_MULSD_VsdWsd, (RegisterID)dst, (RegisterID)src);
-    }
-
-    void mulss_mr(int offset, RegisterID base, XMMRegisterID dst)
-    {
-        m_formatter.prefix(PRE_SSE_F3);
-        m_formatter.twoByteOp(OP2_MULSD_VsdWsd, (RegisterID)dst, base, offset);
-    }
-
     void pextrw_irr(int whichWord, XMMRegisterID src, RegisterID dst)
     {
         m_formatter.prefix(PRE_SSE_66);
@@ -2352,18 +1862,6 @@ public:
         m_formatter.twoByteOp(OP2_SUBSD_VsdWsd, (RegisterID)dst, base, offset);
     }
 
-    void subss_rr(XMMRegisterID src, XMMRegisterID dst)
-    {
-        m_formatter.prefix(PRE_SSE_F3);
-        m_formatter.twoByteOp(OP2_SUBSD_VsdWsd, (RegisterID)dst, (RegisterID)src);
-    }
-
-    void subss_mr(int offset, RegisterID base, XMMRegisterID dst)
-    {
-        m_formatter.prefix(PRE_SSE_F3);
-        m_formatter.twoByteOp(OP2_SUBSD_VsdWsd, (RegisterID)dst, base, offset);
-    }
-
     void ucomisd_rr(XMMRegisterID src, XMMRegisterID dst)
     {
         m_formatter.prefix(PRE_SSE_66);
@@ -2376,16 +1874,6 @@ public:
         m_formatter.twoByteOp(OP2_UCOMISD_VsdWsd, (RegisterID)dst, base, offset);
     }
 
-    void ucomiss_rr(XMMRegisterID src, XMMRegisterID dst)
-    {
-        m_formatter.twoByteOp(OP2_UCOMISD_VsdWsd, (RegisterID)dst, (RegisterID)src);
-    }
-
-    void ucomiss_mr(int offset, RegisterID base, XMMRegisterID dst)
-    {
-        m_formatter.twoByteOp(OP2_UCOMISD_VsdWsd, (RegisterID)dst, base, offset);
-    }
-
     void divsd_rr(XMMRegisterID src, XMMRegisterID dst)
     {
         m_formatter.prefix(PRE_SSE_F2);
@@ -2398,34 +1886,8 @@ public:
         m_formatter.twoByteOp(OP2_DIVSD_VsdWsd, (RegisterID)dst, base, offset);
     }
 
-    void divss_rr(XMMRegisterID src, XMMRegisterID dst)
-    {
-        m_formatter.prefix(PRE_SSE_F3);
-        m_formatter.twoByteOp(OP2_DIVSD_VsdWsd, (RegisterID)dst, (RegisterID)src);
-    }
-
-    void divss_mr(int offset, RegisterID base, XMMRegisterID dst)
-    {
-        m_formatter.prefix(PRE_SSE_F3);
-        m_formatter.twoByteOp(OP2_DIVSD_VsdWsd, (RegisterID)dst, base, offset);
-    }
-
-    void andps_rr(XMMRegisterID src, XMMRegisterID dst)
-    {
-        m_formatter.twoByteOp(OP2_ANDPS_VpdWpd, (RegisterID)dst, (RegisterID)src);
-    }
-
-    void xorps_rr(XMMRegisterID src, XMMRegisterID dst)
-    {
-        m_formatter.twoByteOp(OP2_XORPD_VpdWpd, (RegisterID)dst, (RegisterID)src);
-    }
-
     void xorpd_rr(XMMRegisterID src, XMMRegisterID dst)
     {
-        if (src == dst) {
-            xorps_rr(src, dst);
-            return;
-        }
         m_formatter.prefix(PRE_SSE_66);
         m_formatter.twoByteOp(OP2_XORPD_VpdWpd, (RegisterID)dst, (RegisterID)src);
     }
@@ -2441,60 +1903,7 @@ public:
         m_formatter.prefix(PRE_SSE_F2);
         m_formatter.twoByteOp(OP2_SQRTSD_VsdWsd, (RegisterID)dst, (RegisterID)src);
     }
-
-    void sqrtsd_mr(int offset, RegisterID base, XMMRegisterID dst)
-    {
-        m_formatter.prefix(PRE_SSE_F2);
-        m_formatter.twoByteOp(OP2_SQRTSD_VsdWsd, (RegisterID)dst, base, offset);
-    }
-
-    void sqrtss_rr(XMMRegisterID src, XMMRegisterID dst)
-    {
-        m_formatter.prefix(PRE_SSE_F3);
-        m_formatter.twoByteOp(OP2_SQRTSD_VsdWsd, (RegisterID)dst, (RegisterID)src);
-    }
-
-    void sqrtss_mr(int offset, RegisterID base, XMMRegisterID dst)
-    {
-        m_formatter.prefix(PRE_SSE_F3);
-        m_formatter.twoByteOp(OP2_SQRTSD_VsdWsd, (RegisterID)dst, base, offset);
-    }
-
-    enum class RoundingType : uint8_t {
-        ToNearestWithTiesToEven = 0,
-        TowardNegativeInfiniti = 1,
-        TowardInfiniti = 2,
-        TowardZero = 3
-    };
-
-    void roundss_rr(XMMRegisterID src, XMMRegisterID dst, RoundingType rounding)
-    {
-        m_formatter.prefix(PRE_SSE_66);
-        m_formatter.threeByteOp(OP2_3BYTE_ESCAPE_3A, OP3_ROUNDSS_VssWssIb, (RegisterID)dst, (RegisterID)src);
-        m_formatter.immediate8(static_cast<uint8_t>(rounding));
-    }
-
-    void roundss_mr(int offset, RegisterID base, XMMRegisterID dst, RoundingType rounding)
-    {
-        m_formatter.prefix(PRE_SSE_66);
-        m_formatter.threeByteOp(OP2_3BYTE_ESCAPE_3A, OP3_ROUNDSS_VssWssIb, (RegisterID)dst, base, offset);
-        m_formatter.immediate8(static_cast<uint8_t>(rounding));
-    }
-
-    void roundsd_rr(XMMRegisterID src, XMMRegisterID dst, RoundingType rounding)
-    {
-        m_formatter.prefix(PRE_SSE_66);
-        m_formatter.threeByteOp(OP2_3BYTE_ESCAPE_3A, OP3_ROUNDSD_VsdWsdIb, (RegisterID)dst, (RegisterID)src);
-        m_formatter.immediate8(static_cast<uint8_t>(rounding));
-    }
-
-    void roundsd_mr(int offset, RegisterID base, XMMRegisterID dst, RoundingType rounding)
-    {
-        m_formatter.prefix(PRE_SSE_66);
-        m_formatter.threeByteOp(OP2_3BYTE_ESCAPE_3A, OP3_ROUNDSD_VsdWsdIb, (RegisterID)dst, base, offset);
-        m_formatter.immediate8(static_cast<uint8_t>(rounding));
-    }
-
+    
     // Misc instructions:
 
     void int3()
@@ -2514,7 +1923,7 @@ public:
     
     void mfence()
     {
-        m_formatter.threeByteOp(OP2_3BYTE_ESCAPE_AE, OP3_MFENCE);
+        m_formatter.threeByteOp(OP3_MFENCE);
     }
 
     // Assembler admin methods:
@@ -2645,9 +2054,9 @@ public:
 #if CPU(X86_64)
     static void revertJumpTo_movq_i64r(void* instructionStart, int64_t imm, RegisterID dst)
     {
-        const unsigned instructionSize = 10; // REX.W MOV IMM64
         const int rexBytes = 1;
         const int opcodeBytes = 1;
+        ASSERT(rexBytes + opcodeBytes <= maxJumpReplacementSize());
         uint8_t* ptr = reinterpret_cast<uint8_t*>(instructionStart);
         ptr[0] = PRE_REX | (1 << 3) | (dst >> 3);
         ptr[1] = OP_MOV_EAXIv | (dst & 7);
@@ -2657,33 +2066,11 @@ public:
             uint8_t asBytes[8];
         } u;
         u.asWord = imm;
-        for (unsigned i = rexBytes + opcodeBytes; i < instructionSize; ++i)
-            ptr[i] = u.asBytes[i - rexBytes - opcodeBytes];
-    }
-
-    static void revertJumpTo_movl_i32r(void* instructionStart, int32_t imm, RegisterID dst)
-    {
-        // We only revert jumps on inline caches, and inline caches always use the scratch register (r11).
-        // FIXME: If the above is ever false then we need to make this smarter with respect to emitting 
-        // the REX byte.
-        ASSERT(dst == X86Registers::r11);
-        const unsigned instructionSize = 6; // REX MOV IMM32
-        const int rexBytes = 1;
-        const int opcodeBytes = 1;
-        uint8_t* ptr = reinterpret_cast<uint8_t*>(instructionStart);
-        ptr[0] = PRE_REX | (dst >> 3);
-        ptr[1] = OP_MOV_EAXIv | (dst & 7);
-        
-        union {
-            uint32_t asWord;
-            uint8_t asBytes[4];
-        } u;
-        u.asWord = imm;
-        for (unsigned i = rexBytes + opcodeBytes; i < instructionSize; ++i)
+        for (unsigned i = rexBytes + opcodeBytes; i < static_cast<unsigned>(maxJumpReplacementSize()); ++i)
             ptr[i] = u.asBytes[i - rexBytes - opcodeBytes];
     }
 #endif
-
+    
     static void revertJumpTo_cmpl_ir_force32(void* instructionStart, int32_t imm, RegisterID dst)
     {
         const int opcodeBytes = 1;
@@ -2778,49 +2165,10 @@ public:
     {
         m_formatter.oneByteOp(OP_NOP);
     }
-
+    
     static void fillNops(void* base, size_t size)
     {
-#if CPU(X86_64)
-        static const uint8_t nops[10][10] = {
-            // nop
-            {0x90},
-            // xchg %ax,%ax
-            {0x66, 0x90},
-            // nopl (%[re]ax)
-            {0x0f, 0x1f, 0x00},
-            // nopl 8(%[re]ax)
-            {0x0f, 0x1f, 0x40, 0x08},
-            // nopl 8(%[re]ax,%[re]ax,1)
-            {0x0f, 0x1f, 0x44, 0x00, 0x08},
-            // nopw 8(%[re]ax,%[re]ax,1)
-            {0x66, 0x0f, 0x1f, 0x44, 0x00, 0x08},
-            // nopl 512(%[re]ax)
-            {0x0f, 0x1f, 0x80, 0x00, 0x02, 0x00, 0x00},
-            // nopl 512(%[re]ax,%[re]ax,1)
-            {0x0f, 0x1f, 0x84, 0x00, 0x00, 0x02, 0x00, 0x00},
-            // nopw 512(%[re]ax,%[re]ax,1)
-            {0x66, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x02, 0x00, 0x00},
-            // nopw %cs:512(%[re]ax,%[re]ax,1)
-            {0x66, 0x2e, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x02, 0x00, 0x00}
-        };
-
-        uint8_t* where = reinterpret_cast<uint8_t*>(base);
-        while (size) {
-            unsigned nopSize = static_cast<unsigned>(std::min<size_t>(size, 15));
-            unsigned numPrefixes = nopSize <= 10 ? 0 : nopSize - 10;
-            for (unsigned i = 0; i != numPrefixes; ++i)
-                *where++ = 0x66;
-
-            unsigned nopRest = nopSize - numPrefixes;
-            for (unsigned i = 0; i != nopRest; ++i)
-                *where++ = nops[nopRest-1][i];
-
-            size -= nopSize;
-        }
-#else
         memset(base, OP_NOP, size);
-#endif
     }
 
     // This is a no-op on x86
@@ -2993,32 +2341,12 @@ private:
         }
 #endif
 
-        void threeByteOp(TwoByteOpcodeID twoBytePrefix, ThreeByteOpcodeID opcode)
-        {
-            m_buffer.ensureSpace(maxInstructionSize);
-            m_buffer.putByteUnchecked(OP_2BYTE_ESCAPE);
-            m_buffer.putByteUnchecked(twoBytePrefix);
-            m_buffer.putByteUnchecked(opcode);
-        }
-
-        void threeByteOp(TwoByteOpcodeID twoBytePrefix, ThreeByteOpcodeID opcode, int reg, RegisterID rm)
-        {
-            m_buffer.ensureSpace(maxInstructionSize);
-            emitRexIfNeeded(reg, 0, rm);
-            m_buffer.putByteUnchecked(OP_2BYTE_ESCAPE);
-            m_buffer.putByteUnchecked(twoBytePrefix);
-            m_buffer.putByteUnchecked(opcode);
-            registerModRM(reg, rm);
-        }
-
-        void threeByteOp(TwoByteOpcodeID twoBytePrefix, ThreeByteOpcodeID opcode, int reg, RegisterID base, int displacement)
+        void threeByteOp(ThreeByteOpcodeID opcode)
         {
             m_buffer.ensureSpace(maxInstructionSize);
-            emitRexIfNeeded(reg, 0, base);
             m_buffer.putByteUnchecked(OP_2BYTE_ESCAPE);
-            m_buffer.putByteUnchecked(twoBytePrefix);
+            m_buffer.putByteUnchecked(OP2_3BYTE_ESCAPE);
             m_buffer.putByteUnchecked(opcode);
-            memoryModRM(reg, base, displacement);
         }
 
 #if CPU(X86_64)
@@ -3090,24 +2418,6 @@ private:
             m_buffer.putByteUnchecked(opcode);
             registerModRM(reg, rm);
         }
-
-        void twoByteOp64(TwoByteOpcodeID opcode, int reg, RegisterID base, int offset)
-        {
-            m_buffer.ensureSpace(maxInstructionSize);
-            emitRexW(reg, 0, base);
-            m_buffer.putByteUnchecked(OP_2BYTE_ESCAPE);
-            m_buffer.putByteUnchecked(opcode);
-            memoryModRM(reg, base, offset);
-        }
-
-        void twoByteOp64(TwoByteOpcodeID opcode, int reg, RegisterID base, RegisterID index, int scale, int offset)
-        {
-            m_buffer.ensureSpace(maxInstructionSize);
-            emitRexW(reg, index, base);
-            m_buffer.putByteUnchecked(OP_2BYTE_ESCAPE);
-            m_buffer.putByteUnchecked(opcode);
-            memoryModRM(reg, base, index, scale, offset);
-        }
 #endif
 
         // Byte-operands: