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| author | Jeffrey Walton <noloader@gmail.com> | 2017-09-02 19:25:37 -0400 |
|---|---|---|
| committer | Jeffrey Walton <noloader@gmail.com> | 2017-09-02 19:25:37 -0400 |
| commit | b9e871d1e8425e9add810f837326b2c0e5a5f33c (patch) | |
| tree | b9084779bf9f177496d76aa710c764420e265a72 /config.h | |
| parent | 4a28391495938ffadfa782601b3514ee11176e96 (diff) | |
| download | cryptopp-git-b9e871d1e8425e9add810f837326b2c0e5a5f33c.tar.gz | |
Add PPC, PPC64, AltiVec and Power8 awareness
We are going to try AltiVec/Powe8 crypto. It appears to be a lot like ARMv8-a crypto
Diffstat (limited to 'config.h')
| -rw-r--r-- | config.h | 29 |
1 files changed, 24 insertions, 5 deletions
@@ -413,14 +413,19 @@ NAMESPACE_END # undef CRYPTOPP_X64_MASM_AVAILABLE
#endif
-#if defined(__arm__) || defined(__aarch32__) || defined(_M_ARM)
- #define CRYPTOPP_BOOL_ARM32 1
-#endif
-
// Microsoft plans to support ARM-64, but its not clear how to detect it.
-// TODO: Add MSC_VER and ARM-64 platform define when available
+// TODO: Add MSC_VER and ARM-64 platform define when available
#if defined(__arm64__) || defined(__aarch64__) || defined(_M_ARM64)
#define CRYPTOPP_BOOL_ARM64 1
+#elif defined(__arm__) || defined(__aarch32__) || defined(_M_ARM)
+ #define CRYPTOPP_BOOL_ARM32 1
+#endif
+
+// AltiVec and Power8 crypto
+#if defined(__powerpc64__)
+ #define CRYPTOPP_BOOL_PPC64 1
+#elif defined(__powerpc__)
+ #define CRYPTOPP_BOOL_PPC32 1
#endif
#if defined(_MSC_VER) || defined(__BORLANDC__)
@@ -576,6 +581,20 @@ NAMESPACE_END #endif // ARM32, ARM64
+// ***************** AltiVec and Power8 ********************
+
+#if (CRYPTOPP_BOOL_PPC32 || CRYPTOPP_BOOL_PPC64)
+
+#if !defined(CRYPTOPP_ALTIVEC_CRYPTO_AVAILABLE) && !defined(CRYPTOPP_DISABLE_ASM)
+# if defined(__CRYPTO__) || defined(__ALTIVEC__) || defined(__POWER8_VECTOR__)
+# define CRYPTOPP_ALTIVEC_AES_AVAILABLE 1
+# define CRYPTOPP_ALTIVEC_SHA_AVAILABLE 1
+# define CRYPTOPP_ALTIVEC_CRC_AVAILABLE 1
+# endif
+#endif
+
+#endif // PPC, PPC64
+
// ***************** Miscellaneous ********************
// Nearly all Intel's and AMD's have SSE. Enable it independent of SSE ASM and intrinscs
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