summaryrefslogtreecommitdiff
path: root/blake2s_simd.cpp
Commit message (Collapse)AuthorAgeFilesLines
* Fix use of <x86intrin.h> for MSVC (GH #1198)Jeffrey Walton2023-04-151-3/+3
| | | | It seems Microsoft now defines GCC defines, like __BMI__
* Update BLAKE2s to avoid dependency on bJeffrey Walton2020-07-061-40/+47
|
* Silence GCC warnings in BLAKE2Jeffrey Walton2020-06-291-0/+5
|
* Update commentsJeffrey Walton2020-06-291-9/+9
|
* Speedup BLAKE2s message loading on PowerPCJeffrey Walton2020-06-291-4/+56
|
* Fix BLAKE2s on AIXJeffrey Walton2020-06-291-1/+1
|
* Use little-endian mask during BLAKE2 loadsJeffrey Walton2020-06-281-17/+20
|
* Update commentsJeffrey Walton2020-04-111-1/+1
|
* Update file header commentsJeffrey Walton2020-04-111-1/+1
|
* Remove unneeded PPC64 BLAKE2_Compress32_COREJeffrey Walton2020-04-061-10/+1
|
* Fix unaligned PPC64 loads in BLAKSE2sJeffrey Walton2020-04-051-10/+14
|
* Use Altivec as minimum ISA for Blake2sJeffrey Walton2020-04-051-19/+7
|
* Add XLC 12 loads and stores for AIX (PR #907)Jeffrey Walton2019-10-261-11/+11
| | | Add XLC 12 loads and stores for AIX
* Fix ARM headers and Android compile (PR #896)Jeffrey Walton2019-10-161-3/+2
| | | | | | | | | | | * Test fix ARM headers This problem has been festering for some time. The header file includes are slightly different than the ISA options. Some platforms need an include, others don't. * Fix cryptest-android.sh and cryptest-ios.sh * Fix MSVC ARM32 and ARM64 compile * Split ARM32 and ARM64 recipes in GNUmakefile
* Fix missing _mm_roti_epi32 and _mm_roti_epi64 under GCC (GH #859)Jeffrey Walton2019-07-021-0/+7
|
* Update commentsJeffrey Walton2019-05-281-5/+4
|
* Use PowerPC unaligned loads and stores with Power8 (GH #825, PR #826)Jeffrey Walton2019-04-271-6/+6
| | | Use PowerPC unaligned loads and stores with Power8. Formerly we were using Power7 as the floor because the IBM POWER Architecture manuals said unaligned loads and stores were available. However, some compilers generate bad code for unaligned loads and stores using `-march=power7`, so bump to a known good.
* Clear unused variable warning on AIXJeffrey Walton2019-01-221-0/+2
|
* Cleanup headers after Microsoft ARM64 portJeffrey Walton2019-01-041-2/+0
|
* Fix <arm_neon.h> include for ARM64 with MSVC compiler (GH #776)Jeffrey Walton2019-01-041-1/+2
|
* Add CRYPTOPP_POWER7_ALTIVEC for XLC 12 on AIX workaroundJeffrey Walton2018-11-241-3/+4
|
* Disable Altivec for BLAKE2s on AIX 7.1 and XLC 12.01 (GH #743)Jeffrey Walton2018-11-211-0/+8
|
* Rewrite BLAKE2 classesJeffrey Walton2018-11-201-18/+21
| | | | | | The ParameterBlocks for BLAKE2 had undefined behavior. We relied on the compiler packing the bytes in the structure, then we used the first byte as the start of an array. This rewrite does things correctly. We don't memset the structure, and we don't treat the structure as a contiguous array.
* Fix LLVM Clang compile on PowerPCJeffrey Walton2018-11-191-2/+5
|
* Update commentsJeffrey Walton2018-11-181-0/+5
|
* Add BLAKE2s and ChaCha CORE SIMD function (GH #656)Jeffrey Walton2018-11-181-3/+19
| | | | | The CORE function provides the implementation for ChaCha_OperateKeystream_ALTIVEC, ChaCha_OperateKeystream_POWER7, BLAKE2_Compress32_ALTIVEC and BLAKE2_Compress32_POWER7. Depending on the options used to compile the source files, either POWER7 or ALTIVEC will be used. This is needed to support the "new toolchain, ancient hardware" use case.
* Rename PPC vector functions from VectorFunc to VecFuncJeffrey Walton2018-11-151-59/+59
|
* Update commentsJeffrey Walton2018-11-151-3/+13
|
* Cleanup BLAKE2sJeffrey Walton2018-11-151-44/+10
|
* Rename files with dashes to underscores (GH #736)Jeffrey Walton2018-11-101-0/+1023
Also see https://groups.google.com/forum/#!topic/cryptopp-users/HBz-6gZZFOA on the mailing list
View Lorry Controller Status