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* Update BSP source files for UltraScale Cortex-A53 and Cortex-R5 and ↵Richard Barry2017-01-199-9/+9
| | | | | | | | Microblaze to the 2016.4 versions. Correct alignment issue in GCC Cortex-R port that was preventing full floating point usage in interrupts (other ports will be updated likewise). Update the UltraScale R5 demo to test the GCC Cortex-A9 port layer modification mentioned on the line above.
* Recreated MicroBlaze example using Vivado 2016.1 - the Microblaze project is ↵Richard Barry2016-05-1028-35/+5702
| | | | still a work in progress - not yet fully functional.
* Update the Microblaze hardware design and BSP to the latest IP and tool ↵Richard Barry2016-05-09160-7725/+3317
| | | | versions.
* Add FreeRTOS BSP for Xilinx SDK.Richard Barry2015-08-052-1/+1
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* Common scheduler code:Richard Barry2015-08-04149-0/+28791
| | | | | | | | | - Back out changes that allow mutexes to be given from a semaphore after tests showed issues that would not be fast to fix. Demo projects: - Update the Microblaze Kintex 7 project and BSP to use version 2015.2 of the Xilinx SDK.
* Add networking option to the Microblaze Kintex demo.Richard Barry2015-03-131-9/+0
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* Work-in-progress check in of MicroBlaze Kintex7 demo.Richard Barry2015-03-105-0/+201