diff options
| author | rtel <rtel@1d2547de-c912-0410-9cb9-b8ca96c0e9e2> | 2019-03-08 17:30:49 +0000 |
|---|---|---|
| committer | rtel <rtel@1d2547de-c912-0410-9cb9-b8ca96c0e9e2> | 2019-03-08 17:30:49 +0000 |
| commit | 60062b72f7f837b79d00e9dc341770dd7ee813d6 (patch) | |
| tree | 565a4eb1287bd194aa5d77e2dbf437e8ce666807 /FreeRTOS/Source | |
| parent | 938281bde82b54487a54e389fdbde84c633e123d (diff) | |
| download | freertos-60062b72f7f837b79d00e9dc341770dd7ee813d6.tar.gz | |
Correcting spelling mistakes in comments only.
git-svn-id: http://svn.code.sf.net/p/freertos/code/trunk@2645 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
Diffstat (limited to 'FreeRTOS/Source')
| -rw-r--r-- | FreeRTOS/Source/portable/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_chip_specific_extensions.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/FreeRTOS/Source/portable/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_chip_specific_extensions.h b/FreeRTOS/Source/portable/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_chip_specific_extensions.h index 51924f0be..7a47e1efb 100644 --- a/FreeRTOS/Source/portable/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_chip_specific_extensions.h +++ b/FreeRTOS/Source/portable/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_chip_specific_extensions.h @@ -75,7 +75,7 @@ /* Save additional registers found on the Pulpino. */
.macro portasmSAVE_ADDITIONAL_REGISTERS
addi sp, sp, -(portasmADDITIONAL_CONTEXT_SIZE * portWORD_SIZE) /* Make room for the additional registers. */
- csrr t0, lpstart0 /* Load additional registers into accessable temporary registers. */
+ csrr t0, lpstart0 /* Load additional registers into accessible temporary registers. */
csrr t1, lpend0
csrr t2, lpcount0
csrr t3, lpstart1
@@ -91,7 +91,7 @@ /* Restore the additional registers found on the Pulpino. */
.macro portasmRESTORE_ADDITIONAL_REGISTERS
- lw t0, 1 * portWORD_SIZE( sp ) /* Load additional registers into accessable temporary registers. */
+ lw t0, 1 * portWORD_SIZE( sp ) /* Load additional registers into accessible temporary registers. */
lw t1, 2 * portWORD_SIZE( sp )
lw t2, 3 * portWORD_SIZE( sp )
lw t3, 4 * portWORD_SIZE( sp )
|