Remove driver files that generate compiler warnings from the RISC-V_Renode_Emulator_SoftConsole project.

Update RISC-V ports so the interrupt stack is set to a known value before the scheduler is started if the interrupt stack is statically defined rather than re-using the main.c() stack.

git-svn-id: http://svn.code.sf.net/p/freertos/code/trunk@2754 1d2547de-c912-0410-9cb9-b8ca96c0e9e2

4 files changed, 32 insertions, 17 deletions

diff --git a/FreeRTOS/Source/portable/GCC/RISC-V/port.c b/FreeRTOS/Source/portable/GCC/RISC-V/port.c
index 4cd9daa93..652a8071e 100644
--- a/FreeRTOS/Source/portable/GCC/RISC-V/port.c
+++ b/FreeRTOS/Source/portable/GCC/RISC-V/port.c
@@ -34,6 +34,9 @@
 #include "task.h"

 #include "portmacro.h"

 

+/* Standard includes. */

+#include "string.h"

+

 #ifndef configCLINT_BASE_ADDRESS

 	#warning configCLINT_BASE_ADDRESS must be defined in FreeRTOSConfig.h.  If the target chip includes a Core Local Interrupter (CLINT) then set configCLINT_BASE_ADDRESS to the CLINT base address.  Otherwise set configCLINT_BASE_ADDRESS to 0.

 #endif

@@ -57,6 +60,11 @@ interrupt stack after the scheduler has started. */
 #ifdef configISR_STACK_SIZE_WORDS

 	static __attribute__ ((aligned(16))) StackType_t xISRStack[ configISR_STACK_SIZE_WORDS ] = { 0 };

 	const StackType_t xISRStackTop = ( StackType_t ) &( xISRStack[ configISR_STACK_SIZE_WORDS & ~portBYTE_ALIGNMENT_MASK ] );

+

+	/* Don't use 0xa5 as the stack fill bytes as that is used by the kernerl for

+	the task stacks, and so will legitimately appear in many positions within

+	the ISR stack. */

+	#define portISR_STACK_FILL_BYTE	0xee	

 #else

 	extern const uint32_t __freertos_irq_stack_top[];

 	const StackType_t xISRStackTop = ( StackType_t ) __freertos_irq_stack_top;

@@ -82,12 +90,8 @@ volatile uint64_t * pullMachineTimerCompareRegister = 0;
 stack checking.  A problem in the ISR stack will trigger an assert, not call the

 stack overflow hook function (because the stack overflow hook is specific to a

 task stack, not the ISR stack). */

-#if( configCHECK_FOR_STACK_OVERFLOW > 2 )

+#if defined( configISR_STACK_SIZE_WORDS ) && ( configCHECK_FOR_STACK_OVERFLOW > 2 )

 	#warning This path not tested, or even compiled yet.

-	/* Don't use 0xa5 as the stack fill bytes as that is used by the kernerl for

-	the task stacks, and so will legitimately appear in many positions within

-	the ISR stack. */

-	#define portISR_STACK_FILL_BYTE	0xee

 

 	static const uint8_t ucExpectedStackBytes[] = {

 									portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,		\

@@ -152,6 +156,12 @@ extern void xPortStartFirstTask( void );
 		stack that was being used by main() prior to the scheduler being

 		started. */

 		configASSERT( ( xISRStackTop & portBYTE_ALIGNMENT_MASK ) == 0 );

+

+		#ifdef configISR_STACK_SIZE_WORDS

+		{

+			memset( ( void * ) xISRStack, portISR_STACK_FILL_BYTE, sizeof( xISRStack ) );

+		}

+		#endif	 /* configISR_STACK_SIZE_WORDS */

 	}

 	#endif /* configASSERT_DEFINED */

 

diff --git a/FreeRTOS/Source/portable/GCC/RISC-V/portASM.S b/FreeRTOS/Source/portable/GCC/RISC-V/portASM.S
index fc1236e46..a28942a09 100644
--- a/FreeRTOS/Source/portable/GCC/RISC-V/portASM.S
+++ b/FreeRTOS/Source/portable/GCC/RISC-V/portASM.S
@@ -172,7 +172,7 @@ handle_asynchronous:
 			li t4, -1

 			lw t2, 0(t1)				/* Load the low word of ullNextTime into t2. */

 			lw t3, 4(t1)				/* Load the high word of ullNextTime into t3. */

-			sw t4, 0(t0)				/* Low word no smaller than old value. */

+			sw t4, 0(t0)				/* Low word no smaller than old value to start with - will be overwritten below. */

 			sw t3, 4(t0)				/* Store high word of ullNextTime into compare register.  No smaller than new value. */

 			sw t2, 0(t0)				/* Store low word of ullNextTime into compare register. */

 			lw t0, uxTimerIncrementsForOneTick	/* Load the value of ullTimerIncrementForOneTick into t0 (could this be optimized by storing in an array next to pullNextTime?). */

@@ -226,7 +226,7 @@ is_exception:
 	csrr t0, mcause						/* For viewing in the debugger only. */

 	csrr t1, mepc						/* For viewing in the debugger only */

 	csrr t2, mstatus

-	j is_exception

+	j is_exception						/* No other exceptions handled yet. */

 

 as_yet_unhandled:

 	csrr t0, mcause						/* For viewing in the debugger only. */

diff --git a/FreeRTOS/Source/portable/IAR/RISC-V/port.c b/FreeRTOS/Source/portable/IAR/RISC-V/port.c
index dd32a8e50..a5ec46553 100644
--- a/FreeRTOS/Source/portable/IAR/RISC-V/port.c
+++ b/FreeRTOS/Source/portable/IAR/RISC-V/port.c
@@ -34,6 +34,9 @@
 #include "task.h"

 #include "portmacro.h"

 

+/* Standard includes. */

+#include "string.h"

+

 #ifndef configCLINT_BASE_ADDRESS

 	#warning configCLINT_BASE_ADDRESS must be defined in FreeRTOSConfig.h.  If the target chip includes a Core Local Interrupter (CLINT) then set configCLINT_BASE_ADDRESS to the CLINT base address.  Otherwise set configCLINT_BASE_ADDRESS to 0.

 #endif

@@ -57,6 +60,11 @@ interrupt stack after the scheduler has started. */
 #ifdef configISR_STACK_SIZE_WORDS

 	static __attribute__ ((aligned(16))) StackType_t xISRStack[ configISR_STACK_SIZE_WORDS ] = { 0 };

 	const StackType_t xISRStackTop = ( StackType_t ) &( xISRStack[ configISR_STACK_SIZE_WORDS & ~portBYTE_ALIGNMENT_MASK ] );

+

+	/* Don't use 0xa5 as the stack fill bytes as that is used by the kernerl for

+	the task stacks, and so will legitimately appear in many positions within

+	the ISR stack. */

+	#define portISR_STACK_FILL_BYTE	0xee

 #else

 	extern const uint32_t __freertos_irq_stack_top[];

 	const StackType_t xISRStackTop = ( StackType_t ) __freertos_irq_stack_top;

@@ -77,17 +85,12 @@ const uint64_t *pullNextTime = &ullNextTime;
 const size_t uxTimerIncrementsForOneTick = ( size_t ) ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ); /* Assumes increment won't go over 32-bits. */

 volatile uint64_t * const pullMachineTimerCompareRegisterBase = ( uint64_t * ) ( configCLINT_BASE_ADDRESS + 0x4000 );

 volatile uint64_t * pullMachineTimerCompareRegister = 0;

-

 /* Set configCHECK_FOR_STACK_OVERFLOW to 3 to add ISR stack checking to task

 stack checking.  A problem in the ISR stack will trigger an assert, not call the

 stack overflow hook function (because the stack overflow hook is specific to a

 task stack, not the ISR stack). */

-#if( configCHECK_FOR_STACK_OVERFLOW > 2 )

+#if defined( configISR_STACK_SIZE_WORDS ) && ( configCHECK_FOR_STACK_OVERFLOW > 2 )

 	#warning This path not tested, or even compiled yet.

-	/* Don't use 0xa5 as the stack fill bytes as that is used by the kernerl for

-	the task stacks, and so will legitimately appear in many positions within

-	the ISR stack. */

-	#define portISR_STACK_FILL_BYTE	0xee

 

 	static const uint8_t ucExpectedStackBytes[] = {

 									portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,		\

diff --git a/FreeRTOS/Source/portable/IAR/RISC-V/portASM.s b/FreeRTOS/Source/portable/IAR/RISC-V/portASM.s
index c4082c7b3..bcd58a878 100644
--- a/FreeRTOS/Source/portable/IAR/RISC-V/portASM.s
+++ b/FreeRTOS/Source/portable/IAR/RISC-V/portASM.s
@@ -99,12 +99,12 @@ at the top of this file. */
 	EXTERN pxCurrentTCB

 	EXTERN ulPortTrapHandler

 	EXTERN vTaskSwitchContext

+	EXTERN xTaskIncrementTick

 	EXTERN Timer_IRQHandler

 	EXTERN pullMachineTimerCompareRegister

 	EXTERN pullNextTime

 	EXTERN uxTimerIncrementsForOneTick /* size_t type so 32-bit on 32-bit core and 64-bits on 64-bit core. */

 	EXTERN xISRStackTop

-	EXTERN xTaskIncrementTick

 	EXTERN portasmHANDLE_INTERRUPT

 

 /*-----------------------------------------------------------*/

@@ -231,11 +231,13 @@ test_if_environment_call:
 	j processed_source

 

 is_exception:

-	ebreak

-	j is_exception

+	csrr t0, CSR_MCAUSE					/* For viewing in the debugger only. */

+	csrr t1, CSR_MEPC					/* For viewing in the debugger only */

+	csrr t2, CSR_MSTATUS

+	j is_exception						/* No other exceptions handled yet. */

 

 as_yet_unhandled:

-	ebreak

+	csrr t0, mcause						/* For viewing in the debugger only. */

 	j as_yet_unhandled

 

 processed_source: