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| author | Sayed Adel <seiko@imavr.com> | 2021-05-20 15:32:09 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-05-20 15:32:09 +0200 |
| commit | 372adbe5be732619ec7365eee56f5da75ff7c434 (patch) | |
| tree | 50d08acf00a62edb1527244551fcb4232ec56361 | |
| parent | 290a0345c8a0eb33ba98172267e6d392110fe905 (diff) | |
| parent | b0c0ec10e6eaf93ea392a1641d82cd20eadf5d79 (diff) | |
| download | numpy-372adbe5be732619ec7365eee56f5da75ff7c434.tar.gz | |
Merge pull request #19047 from seiko2plus/issue_19017
BUG, SIMD: Fix NumPy build on ppc64le(IBM/Power) for old versions of GCC(<=6)
| -rw-r--r-- | numpy/core/src/common/simd/vsx/arithmetic.h | 2 | ||||
| -rw-r--r-- | numpy/core/src/common/simd/vsx/operators.h | 18 |
2 files changed, 15 insertions, 5 deletions
diff --git a/numpy/core/src/common/simd/vsx/arithmetic.h b/numpy/core/src/common/simd/vsx/arithmetic.h index 123fcaf92..eaca53620 100644 --- a/numpy/core/src/common/simd/vsx/arithmetic.h +++ b/numpy/core/src/common/simd/vsx/arithmetic.h @@ -222,7 +222,7 @@ NPY_FINLINE npyv_u64 npyv_divc_u64(npyv_u64 a, const npyv_u64x3 divisor) // divide each signed 64-bit element by a precomputed divisor (round towards zero) NPY_FINLINE npyv_s64 npyv_divc_s64(npyv_s64 a, const npyv_s64x3 divisor) { - npyv_b64 overflow = vec_and(vec_cmpeq(a, npyv_setall_s64(-1LL << 63)), (npyv_b64)divisor.val[1]); + npyv_b64 overflow = npyv_and_b64(vec_cmpeq(a, npyv_setall_s64(-1LL << 63)), (npyv_b64)divisor.val[1]); npyv_s64 d = vec_sel(divisor.val[0], npyv_setall_s64(1), overflow); return vec_div(a, d); } diff --git a/numpy/core/src/common/simd/vsx/operators.h b/numpy/core/src/common/simd/vsx/operators.h index 230610129..23c5d0dbe 100644 --- a/numpy/core/src/common/simd/vsx/operators.h +++ b/numpy/core/src/common/simd/vsx/operators.h @@ -44,7 +44,16 @@ /*************************** * Logical ***************************/ +#define NPYV_IMPL_VSX_BIN_CAST(INTRIN, SFX, CAST) \ + NPY_FINLINE npyv_##SFX npyv_##INTRIN##_##SFX(npyv_##SFX a, npyv_##SFX b) \ + { return (npyv_##SFX)vec_##INTRIN((CAST)a, (CAST)b); } +// Up to GCC 6 logical intrinsics don't support bool long long +#if defined(__GNUC__) && __GNUC__ <= 6 + #define NPYV_IMPL_VSX_BIN_B64(INTRIN) NPYV_IMPL_VSX_BIN_CAST(INTRIN, b64, npyv_u64) +#else + #define NPYV_IMPL_VSX_BIN_B64(INTRIN) NPYV_IMPL_VSX_BIN_CAST(INTRIN, b64, npyv_b64) +#endif // AND #define npyv_and_u8 vec_and #define npyv_and_s8 vec_and @@ -59,7 +68,7 @@ #define npyv_and_b8 vec_and #define npyv_and_b16 vec_and #define npyv_and_b32 vec_and -#define npyv_and_b64 vec_and +NPYV_IMPL_VSX_BIN_B64(and) // OR #define npyv_or_u8 vec_or @@ -75,7 +84,7 @@ #define npyv_or_b8 vec_or #define npyv_or_b16 vec_or #define npyv_or_b32 vec_or -#define npyv_or_b64 vec_or +NPYV_IMPL_VSX_BIN_B64(or) // XOR #define npyv_xor_u8 vec_xor @@ -91,7 +100,7 @@ #define npyv_xor_b8 vec_xor #define npyv_xor_b16 vec_xor #define npyv_xor_b32 vec_xor -#define npyv_xor_b64 vec_xor +NPYV_IMPL_VSX_BIN_B64(xor) // NOT // note: we implement npyv_not_b*(boolen types) for internal use*/ @@ -141,7 +150,8 @@ NPY_FINLINE npyv_f64 npyv_not_f64(npyv_f64 a) #define npyv_cmpeq_f64 vec_cmpeq // Int Not Equal -#ifdef NPY_HAVE_VSX3 +#if defined(NPY_HAVE_VSX3) && (!defined(__GNUC__) || defined(vec_cmpne)) + // vec_cmpne supported by gcc since version 7 #define npyv_cmpneq_u8 vec_cmpne #define npyv_cmpneq_s8 vec_cmpne #define npyv_cmpneq_u16 vec_cmpne |