summaryrefslogtreecommitdiff
path: root/doc/source/reference/simd/simd-optimizations-tables-diff.inc
diff options
context:
space:
mode:
authorSayed Adel <seiko@imavr.com>2020-07-13 05:28:10 +0200
committerSayed Adel <seiko@imavr.com>2020-07-14 09:13:59 +0200
commitf817de8f058bd7503bbc94e153279e926bf15603 (patch)
tree6b0614c882a3ff14d23807e3b9c93ccb74e0de24 /doc/source/reference/simd/simd-optimizations-tables-diff.inc
parent151c0aae81c16627cad79e9e81424c2221b94970 (diff)
downloadnumpy-f817de8f058bd7503bbc94e153279e926bf15603.tar.gz
DOC: improve SIMD features tables
- improve the tables generator(style/simplify) - show the differences between the compilers - add an explanation about interrelated CPU features
Diffstat (limited to 'doc/source/reference/simd/simd-optimizations-tables-diff.inc')
-rw-r--r--doc/source/reference/simd/simd-optimizations-tables-diff.inc37
1 files changed, 37 insertions, 0 deletions
diff --git a/doc/source/reference/simd/simd-optimizations-tables-diff.inc b/doc/source/reference/simd/simd-optimizations-tables-diff.inc
new file mode 100644
index 000000000..41fa96703
--- /dev/null
+++ b/doc/source/reference/simd/simd-optimizations-tables-diff.inc
@@ -0,0 +1,37 @@
+.. generated via source/reference/simd/simd-optimizations.py
+
+x86::Intel Compiler - CPU feature names
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+.. table::
+ :align: left
+
+ =========== ==================================================================================================================
+ Name Implies
+ =========== ==================================================================================================================
+ ``FMA3`` ``SSE`` ``SSE2`` ``SSE3`` ``SSSE3`` ``SSE41`` ``POPCNT`` ``SSE42`` ``AVX`` ``F16C`` **AVX2**
+ ``AVX2`` ``SSE`` ``SSE2`` ``SSE3`` ``SSSE3`` ``SSE41`` ``POPCNT`` ``SSE42`` ``AVX`` ``F16C`` **FMA3**
+ ``AVX512F`` ``SSE`` ``SSE2`` ``SSE3`` ``SSSE3`` ``SSE41`` ``POPCNT`` ``SSE42`` ``AVX`` ``F16C`` ``FMA3`` ``AVX2`` **AVX512CD**
+ =========== ==================================================================================================================
+
+.. note::
+ The following features aren't supported by x86::Intel Compiler:
+ **XOP FMA4**
+
+x86::Microsoft Visual C/C++ - CPU feature names
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+.. table::
+ :align: left
+
+ ============ =================================================================================================================================
+ Name Implies
+ ============ =================================================================================================================================
+ ``FMA3`` ``SSE`` ``SSE2`` ``SSE3`` ``SSSE3`` ``SSE41`` ``POPCNT`` ``SSE42`` ``AVX`` ``F16C`` **AVX2**
+ ``AVX2`` ``SSE`` ``SSE2`` ``SSE3`` ``SSSE3`` ``SSE41`` ``POPCNT`` ``SSE42`` ``AVX`` ``F16C`` **FMA3**
+ ``AVX512F`` ``SSE`` ``SSE2`` ``SSE3`` ``SSSE3`` ``SSE41`` ``POPCNT`` ``SSE42`` ``AVX`` ``F16C`` ``FMA3`` ``AVX2`` **AVX512CD** **AVX512_SKX**
+ ``AVX512CD`` ``SSE`` ``SSE2`` ``SSE3`` ``SSSE3`` ``SSE41`` ``POPCNT`` ``SSE42`` ``AVX`` ``F16C`` ``FMA3`` ``AVX2`` ``AVX512F`` **AVX512_SKX**
+ ============ =================================================================================================================================
+
+.. note::
+ The following features aren't supported by x86::Microsoft Visual C/C++:
+ **AVX512_KNL AVX512_KNM**
+