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| author | Charles Harris <charlesr.harris@gmail.com> | 2018-04-01 11:31:23 -0600 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-04-01 11:31:23 -0600 |
| commit | cf7b9b58ca58bdee45f31416fd92b99f74b0aa1e (patch) | |
| tree | 26b0b96a72d30b5249d358cd71535627b5e488c5 /numpy/core | |
| parent | 20cb312563b2e7c0b180db8dffbcd71d7dfd0bee (diff) | |
| parent | c0d9c97eeab5c799c699608a64c4af31f8ec731b (diff) | |
| download | numpy-cf7b9b58ca58bdee45f31416fd92b99f74b0aa1e.tar.gz | |
Merge pull request #10833 from aurel32/riscv64
ENH: Add support for the 64-bit RISC-V architecture
Diffstat (limited to 'numpy/core')
| -rw-r--r-- | numpy/core/include/numpy/npy_cpu.h | 3 | ||||
| -rw-r--r-- | numpy/core/include/numpy/npy_endian.h | 3 |
2 files changed, 5 insertions, 1 deletions
diff --git a/numpy/core/include/numpy/npy_cpu.h b/numpy/core/include/numpy/npy_cpu.h index 84653ea18..106ffa450 100644 --- a/numpy/core/include/numpy/npy_cpu.h +++ b/numpy/core/include/numpy/npy_cpu.h @@ -17,6 +17,7 @@ * NPY_CPU_SH_BE * NPY_CPU_ARCEL * NPY_CPU_ARCEB + * NPY_CPU_RISCV64 */ #ifndef _NPY_CPUARCH_H_ #define _NPY_CPUARCH_H_ @@ -82,6 +83,8 @@ #define NPY_CPU_ARCEL #elif defined(__arc__) && defined(__BIG_ENDIAN__) #define NPY_CPU_ARCEB +#elif defined(__riscv) && defined(__riscv_xlen) && __riscv_xlen == 64 + #define NPY_CPU_RISCV64 #else #error Unknown CPU, please report this to numpy maintainers with \ information about your platform (OS, CPU and compiler) diff --git a/numpy/core/include/numpy/npy_endian.h b/numpy/core/include/numpy/npy_endian.h index 1a42121db..649bdb0a6 100644 --- a/numpy/core/include/numpy/npy_endian.h +++ b/numpy/core/include/numpy/npy_endian.h @@ -46,7 +46,8 @@ || defined(NPY_CPU_SH_LE) \ || defined(NPY_CPU_MIPSEL) \ || defined(NPY_CPU_PPC64LE) \ - || defined(NPY_CPU_ARCEL) + || defined(NPY_CPU_ARCEL) \ + || defined(NPY_CPU_RISCV64) #define NPY_BYTE_ORDER NPY_LITTLE_ENDIAN #elif defined(NPY_CPU_PPC) \ || defined(NPY_CPU_SPARC) \ |