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* Bug: Fix compilation of halffloat with gcc 13.1Sayed Adel2023-05-042-1/+2
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* Merge pull request #22137 from Micky774/enable_simdMatti Picus2023-05-032-51/+96
|\ | | | | ENH allow for specifying CPU features to enable via `NPY_ENABLE_CPU_FEATURES` environment variable
| * ENH: add NPY_ENABLE_CPU_FEATURES to allow limiting set of enabled featuresMeekail Zain2023-04-082-51/+96
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* | Merge pull request #23298 from seiko2plus/cpp_half_supportSebastian Berg2023-04-257-27/+776
|\ \ | |/ |/| ENH: Extend the functionlty of C++ type `np::Half`
| * ENH: Extend the functionlty of C++ type `np::Half`Sayed Adel2023-04-057-27/+776
| | | | | | | | | | | | | | | | | | | | - optimize float/double conversions on x86, requires for now raising up the baseline features to `f16c` at least during the build. - optimize float/double conversions on ppc64le, requires for now raising up the baseline features to `VSX3` at least during the build. - Brings `np::Half` to npymath
* | BUG: fix loading and storing big arrays on s390xAleksei Nikiforov2023-03-301-7/+7
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* MAINT: move npy_dtype_info definition back to descriptor.hNathan Goldbaum2023-03-201-1/+0
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* ENH: allow using dtype classes in array creation functionsNathan Goldbaum2023-03-172-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This enables writing np.array(some_object, dtype=type(np.dtype('i'))). This is a follow-on from https://github.com/numpy/numpy/pull/23154, see that PR for more details. I had to add a new include to `ctors.h` to bring in the definition of the `npy_dtype_info` struct. Since `ctors.h` is included in many other files inside numpy, I found that I needed to modify fewer includes across numpy if I moved the definition of `npy_dtype_info` to `common.h` from `descriptor.h`. The new includes of `common.h` are needed to support later includes of `ctors.h` in those files. If anyone has an alternate place to put `npy_dtype_info` that would cause less churn of includes I'd love to hear about it. I spent a bunch of time tweaking the reference counts. I'm reasonably confident this is correct but not 100%, an additional careful pass over the reference count logic from a reviewer would be very appreciated. I could have made `_PyArray_FromAny` and `_PyArray_CheckFromAny` take just a `npy_dtype_info` struct, but I found it made the reference count logic more complicated, since `PyArray_FromAny` and `PyArray_CheckFromAny` steal the reference to the descriptor they are passed and I needed to conserve that behavior. Also both functions support passing in a `NULL` pointer for the descriptor and I needed to maintain that behavior as well. The change to `ucsnarrow.h` fixes a preexisting conflict with the prototype in `ucsnarrow.c` that triggered a compiler error while I was working on this.
* Merge pull request #23153 from seiko2plus/removes_old_cpu_dispatcherCharles Harris2023-02-227-54/+66
|\ | | | | SIMD: Get rid of attribute-based CPU dispatching
| * SIMD: Suppress VSX ambiguous warningsSayed Adel2023-02-213-0/+13
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| * MAINT, SIMD: fix c++ build when VSX intrinsics are in the scopeSayed Adel2023-02-202-22/+16
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| * MAINT, SIMD: fix c++ build when AVX2 intrinsics are in the scopeSayed Adel2023-02-201-8/+8
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| * MAINT, SIMD: fix c++ build when SSE intrinsics are in the scopeSayed Adel2023-02-201-24/+29
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* | BUG: use a _invalid_parameter_handler around _fdopen to prevent crashes when ↵Matti Picus2023-02-201-0/+22
|/ | | | call fails
* Merge pull request #22051 from r-devulap/spr-supportMatti Picus2023-02-192-0/+10
|\ | | | | BLD: Add compile and runtime checks for AVX512_SPR
| * BLD: Add compile and runtime checks for AVX512FP16Raghuveer Devulapalli2023-02-022-0/+10
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* | Merge pull request #22315 from r-devulap/avxsortMatti Picus2023-02-155-0/+183
|\ \ | | | | | | ENH: Vectorize quicksort for 16-bit and 64-bit dtype using AVX512
| * | ENH, SIMD: include npy_cpu_dipatch.h by npy_config.hSayed Adel2023-02-071-0/+1
| | | | | | | | | | | | To guarantee of having #defs NPY_HAVE_[CPU features] in the scope
| * | ENH: Towards modern C++Sayed Adel2023-02-074-0/+182
| |/ | | | | | | | | | | This patch initializes new C++ headers and also brings new namespace `np::` to break away from the current approach of using C++ which tends not to be drawn into modernity.
* | Fix typos found by copdespellDimitri Papadopoulos2023-02-114-9/+9
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* | Merge pull request #21056 from seiko2plus/replace_raw_arithmfpMatti Picus2023-01-3117-91/+2057
|\ \ | |/ |/| ENH: re-implement SIMD kernels of complex operations
| * ENH, SIMD: Implment intrinsic for mask divisionSayed Adel2023-01-292-0/+47
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| * ENH, SIMD: Implment intrinsic for FMA multiply add(odd) and subtract(even)Sayed Adel2023-01-295-0/+72
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| * ENH, SIMD: Add special intrinsics for better non-contiguous/partial memory ↵Sayed Adel2023-01-295-66/+1418
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | access for complex load/store summarized as follows: 64-bit contiguous partial load/store over 32-bit lane npyv_load2_till_u32, npyv_load2_till_s32, npyv_load2_till_f32 npyv_load2_tillz_u32, npyv_load2_tillz_s32, npyv_load2_tillz_f32 npyv_store2_till_u32, npyv_store2_till_s32, npyv_store2_till_f32 128-bit contiguous partial load/store over 64-bit lane npyv_load2_till_u64, npyv_load2_till_s64, npyv_load2_till_f64 npyv_load2_tillz_u64, npyv_load2_tillz_s64, npyv_load2_tillz_f64 npyv_store2_till_u64, npyv_store2_till_s64, npyv_store2_till_f64 64-bit non-contiguous load/store over 32-bit stride npyv_loadn2_u32, npyv_loadn2_s32, npyv_loadn2_f32 npyv_storen2_u32, npyv_storen2_s32, npyv_storen2_f32 128-bit non-contiguous load/store over 64-bit stride npyv_loadn2_u64, npyv_loadn2_s64, npyv_loadn2_f64 npyv_storen2_u64, npyv_storen2_s64, npyv_storen2_f64 64-bit non-contiguous partial load/store over 32-bit stride npyv_loadn2_till_u32, npyv_loadn2_till_s32, npyv_loadn2_till_f32 npyv_loadn2_tillz_u32, npyv_loadn2_tillz_s32, npyv_loadn2_tillz_f32 npyv_storen2_till_u32, npyv_storen2_till_s32, npyv_storen2_till_f32 128-bit non-contiguous partial load/store over 64-bit stride npyv_loadn2_till_u64, npyv_loadn2_till_s64, npyv_loadn2_till_f64 npyv_loadn2_tillz_u64, npyv_loadn2_tillz_s64, npyv_loadn2_tillz_f64 npyv_storen2_till_u64, npyv_storen2_till_s64, npyv_storen2_till_f64 2 channels de-interlave/interleave contiguous load/store for all data types npyv_load_##sfx##x2, npyv_store_##sfx##x2
| * ENH: Implement intrinsics for shuffle over 128-bit lane and unzipSayed Adel2023-01-295-25/+520
| | | | | | | | | | shuffle intrinsics support 32-bit/64-bit vector data types, unzip(deinterleave) intrinsics supports all data types.
* | MAINT: Allow export/import of bools in dlpackSebastian Berg2023-01-271-17/+136
|/ | | | | Updates the header file and accept as well as export boolean now that the header includes a definition for it.
* replace __builtin_s390_vflls with npyv_doublee as beforePradipta Ghosh2023-01-241-2/+2
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* BUG: Fix for npyv_s32 npyv__trunc_s32_f32 (VXE)Pradipta Ghosh2023-01-241-1/+2
| | | | | | np.sin(), np.cos() are giving erroneous result for float32 (VXE) This PR is fixing `npyv_s32 npyv__trunc_s32_f32(npyv_f32 a)` to resolve the issue.
* BLD, SIMD: Pad asm to avoid C99 complains on CLANGSayed Adel2023-01-161-3/+3
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* BUG, SIMD: Fix spurious invalid exception for sin/cos on arm64/clangSayed Adel2023-01-061-2/+27
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* Merge pull request #22777 from pkubaj/patch-1Sayed Adel2022-12-311-2/+14
|\ | | | | ENH: Properly support FreeBSD/powerpc64
| * ENH: Detect CPU features on FreeBSD/powerpc64*pkubaj2022-12-301-2/+14
| | | | | | | | | | | | | | | | | | | | 1. FreeBSD uses elf_aux_info() instead of getauxval. 2. Switch to using compiler macros for detecting POWER platform FreeBSD sets the machine name (what uname -m prints) on all powerpc* to just powerpc. To identify actual architecture, uname -p should be used, but this is not present in uname() function. Thus, the only way to correctly detect platform is to use what uname prints and also check compiler defines.
* | ENH, SIMD: Discard non-signaling comparison intrinsicsSayed Adel2022-12-1511-125/+9
| | | | | | | | | | | | | | | | | | | | Providing non-signaling comparison intrinsics that guarantee no FP invalid exception in case of qNaN sounds great but it cost unacceptable extra intrinsics on ppc64le(VSX) and x86(SSE). Therefore, an integer definition #NPY_SIMD_CMPSIGNAL has been provided instead to differenate between SIMD extensions that support only supports signaling comparison.
* | BUG, SIMD: Fix invalid value encountered in rint/trunc/ceil/floor on armhf/neonSayed Adel2022-12-141-68/+81
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* | BUG, SIMD: Fix invalid value encountered in rint/trunc/ceil/floor on x86/SSE2Sayed Adel2022-12-141-48/+134
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* | BUG, SIMD: Fix invalid value encountered in cos/sin on aarch64 & ppc64leSayed Adel2022-12-141-1/+1
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* | ENH, SIMD: Add ordered comparison intrinsics guarantees non-signalingSayed Adel2022-12-145-1/+126
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* BUG, SIMD: Fix rounding large numbers >= 2^52 on SSE2Sayed Adel2022-12-071-10/+11
| | | | | | | | | | | | | Before SSE41, there were no native instructions for rounding operations on double precision. We usually emulate it by assuming that the `MXCR` register is set to rounding, adding a large number `2^52` to `X` and then subtracting it back to eliminate any excess precision as long as `|X|` is less than `2^52` otherwise returns `X.` The current emulated intrinics `npyv_[rint,floor, ceil, trunc]_f64` was not checking whether `|x|` equal or large `2^52` which leads to losing accuracy on large numbers.
* MAINT: remove remaining `NPY_INLINE` usagesRalf Gommers2022-11-271-4/+4
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* MAINT: replace `NPY_INLINE` with `inline`Ralf Gommers2022-11-2510-36/+36
| | | | Closes gh-22100
* BUG: fix issue with broken assert statement in `templ_common.h.src`Ralf Gommers2022-11-121-2/+3
| | | | | assert() only takes one argument. This was recently introduced, in commit 4156ae260 (gh-21793)
* MAINT: Fix typos found by codespellDimitri Papadopoulos2022-10-071-1/+1
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* Merge pull request #22325 from seiko2plus/npyv_speedup_neon_vec_initSebastian Berg2022-09-261-80/+88
|\ | | | | SIMD: Improve the performance of NEON vector initializer
| * SIMD: Improve the performance of NEON vector initializerSayed Adel2022-09-251-80/+88
| | | | | | | | | | | | Using load over stack has a bad impact on the compiler static analysis compared with direct compiler initlizer via curly brace which is supported by both gcc and clang.
* | SIMD: Add new intrinsics to check true cross all vector lanesSayed Adel2022-09-1912-113/+455
| | | | | | | | | | npyv_any_##SFX: returns true if any of the elements is not equal to zero npyv_all_##SFX: returns true if all elements are not equal to zero
* | ENH, SIMD: Implement new universal intrinsic for max/min operationsSayed Adel2022-09-1711-82/+742
|/ | | | | | | | | | | | | | | | | | | | | | max/min that reverse IEC 60559's NaN beahvior(propagates NaNs) for float data types npyv_maxn_##SFX npyv_minn_##SFX max/min reduction for all float and integer vector data types npyv_reduce_max_##SFX npyv_reduce_min_##SFX max/min reduction supports IEC 60559 for float data types npyv_reduce_maxp_##SFX npyv_reduce_minp_##SFX max/min reduction reverse IEC 60559's NaN beahvior(propagates NaNs) for float data types npyv_reduce_maxn_##SFX npyv_reduce_minn_##SFX also, this patch implements new intrinsics to extract the first vector lane: npyv_extract0_##SFX npyv_extract0_##SFX
* ENH: Added support for SVML vectorization of power and arctan2Matthew Sterrett2022-09-091-2/+4
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* TASK: rename macros (from review)mattip2022-08-211-14/+14
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* BUILD: convert HAVE_ macros to BLOCK_, cleanupmattip2022-08-211-16/+16
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* strtoull and strtoll are mandatorymattip2022-08-211-15/+0
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