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| author | Matthäus G. Chajdas <dev@anteru.net> | 2021-01-30 14:33:17 +0100 |
|---|---|---|
| committer | Matthäus G. Chajdas <dev@anteru.net> | 2021-01-30 14:33:17 +0100 |
| commit | dab1998b313697ab94f391e63ea5a2ef7f46f073 (patch) | |
| tree | 1f2c9cbf4ca25c53be25937ff0a0e1645064f8ca /tests/examplefiles/amdgpu | |
| parent | fc0d85490c8b64de8f60d70042ad7919470a0059 (diff) | |
| download | pygments-git-dab1998b313697ab94f391e63ea5a2ef7f46f073.tar.gz | |
Add expected output for the AMDGPU example.
Diffstat (limited to 'tests/examplefiles/amdgpu')
| -rw-r--r-- | tests/examplefiles/amdgpu/amdgpu.isa | 10 | ||||
| -rw-r--r-- | tests/examplefiles/amdgpu/amdgpu.isa.output | 130 |
2 files changed, 140 insertions, 0 deletions
diff --git a/tests/examplefiles/amdgpu/amdgpu.isa b/tests/examplefiles/amdgpu/amdgpu.isa new file mode 100644 index 00000000..fdab33cc --- /dev/null +++ b/tests/examplefiles/amdgpu/amdgpu.isa @@ -0,0 +1,10 @@ +s_load_dwordx2 s[4:5], s[0:1], 0x10 +s_load_dwordx4 s[0:3], s[0:1], 0x00 +v_lshlrev_b32 v0, 2, v0 +s_waitcnt lgkmcnt(0) +v_add_u32 v1, vcc, s2, v0 +v_mov_b32 v2, s3 +v_addc_u32 v2, vcc, v2, 0, vcc +v_add_u32 v3, vcc, s0, v0 +v_mov_b32 v4, s1 +v_addc_u32 v4, vcc, v4, 0, vcc
\ No newline at end of file diff --git a/tests/examplefiles/amdgpu/amdgpu.isa.output b/tests/examplefiles/amdgpu/amdgpu.isa.output new file mode 100644 index 00000000..d8f1c0f5 --- /dev/null +++ b/tests/examplefiles/amdgpu/amdgpu.isa.output @@ -0,0 +1,130 @@ +'s_load_dwordx2' Keyword +' ' Text.Whitespace +'s' Name.Variable +'[' Text +'4:5' Name.Attribute +']' Text +',' Text +' ' Text.Whitespace +'s' Name.Variable +'[' Text +'0:1' Name.Attribute +']' Text +',' Text +' ' Text.Whitespace +'0x10' Literal.Number.Integer +'\n' Text.Whitespace + +'s_load_dwordx4' Keyword +' ' Text.Whitespace +'s' Name.Variable +'[' Text +'0:3' Name.Attribute +']' Text +',' Text +' ' Text.Whitespace +'s' Name.Variable +'[' Text +'0:1' Name.Attribute +']' Text +',' Text +' ' Text.Whitespace +'0x00' Literal.Number.Integer +'\n' Text.Whitespace + +'v_lshlrev_b32' Keyword +' ' Text.Whitespace +'v0' Name.Variable +',' Text +' ' Text.Whitespace +'2' Literal.Number.Integer +',' Text +' ' Text.Whitespace +'v0' Name.Variable +'\n' Text.Whitespace + +'s_waitcnt' Keyword +' ' Text.Whitespace +'lgkmcnt' Name.Attribute +'(' Text +'0' Literal.Number.Integer +')' Text +'\n' Text.Whitespace + +'v_add_u32' Keyword +' ' Text.Whitespace +'v1' Name.Variable +',' Text +' ' Text.Whitespace +'vcc' Name.Variable +',' Text +' ' Text.Whitespace +'s2' Name.Variable +',' Text +' ' Text.Whitespace +'v0' Name.Variable +'\n' Text.Whitespace + +'v_mov_b32' Keyword +' ' Text.Whitespace +'v2' Name.Variable +',' Text +' ' Text.Whitespace +'s3' Name.Variable +'\n' Text.Whitespace + +'v_addc_u32' Keyword +' ' Text.Whitespace +'v2' Name.Variable +',' Text +' ' Text.Whitespace +'vcc' Name.Variable +',' Text +' ' Text.Whitespace +'v2' Name.Variable +',' Text +' ' Text.Whitespace +'0' Literal.Number.Integer +',' Text +' ' Text.Whitespace +'vcc' Name.Variable +'\n' Text.Whitespace + +'v_add_u32' Keyword +' ' Text.Whitespace +'v3' Name.Variable +',' Text +' ' Text.Whitespace +'vcc' Name.Variable +',' Text +' ' Text.Whitespace +'s0' Name.Variable +',' Text +' ' Text.Whitespace +'v0' Name.Variable +'\n' Text.Whitespace + +'v_mov_b32' Keyword +' ' Text.Whitespace +'v4' Name.Variable +',' Text +' ' Text.Whitespace +'s1' Name.Variable +'\n' Text.Whitespace + +'v_addc_u32' Keyword +' ' Text.Whitespace +'v4' Name.Variable +',' Text +' ' Text.Whitespace +'vcc' Name.Variable +',' Text +' ' Text.Whitespace +'v4' Name.Variable +',' Text +' ' Text.Whitespace +'0' Literal.Number.Integer +',' Text +' ' Text.Whitespace +'vcc' Name.Variable +'\n' Text.Whitespace |