Imported WebKit commit 356d83016b090995d08ad568f2d2c243aa55e831 (http://svn.webkit.org/repository/webkit/trunk@126147)

New snapshot including various build fixes for newer Qt 5

1 files changed, 77 insertions, 77 deletions

diff --git a/Source/JavaScriptCore/assembler/ARMAssembler.h b/Source/JavaScriptCore/assembler/ARMAssembler.h
index ac918f31e..38d0c5e6d 100644
--- a/Source/JavaScriptCore/assembler/ARMAssembler.h
+++ b/Source/JavaScriptCore/assembler/ARMAssembler.h
@@ -268,355 +268,355 @@ namespace JSC {
                                | (sm >> 1) | ((sm & 0x1) << 5));
         }
 
-        void and_r(int rd, int rn, ARMWord op2, Condition cc = AL)
+        void bitAnd(int rd, int rn, ARMWord op2, Condition cc = AL)
         {
             emitInstruction(toARMWord(cc) | AND, rd, rn, op2);
         }
 
-        void ands_r(int rd, int rn, ARMWord op2, Condition cc = AL)
+        void bitAnds(int rd, int rn, ARMWord op2, Condition cc = AL)
         {
             emitInstruction(toARMWord(cc) | AND | SetConditionalCodes, rd, rn, op2);
         }
 
-        void eor_r(int rd, int rn, ARMWord op2, Condition cc = AL)
+        void eor(int rd, int rn, ARMWord op2, Condition cc = AL)
         {
             emitInstruction(toARMWord(cc) | EOR, rd, rn, op2);
         }
 
-        void eors_r(int rd, int rn, ARMWord op2, Condition cc = AL)
+        void eors(int rd, int rn, ARMWord op2, Condition cc = AL)
         {
             emitInstruction(toARMWord(cc) | EOR | SetConditionalCodes, rd, rn, op2);
         }
 
-        void sub_r(int rd, int rn, ARMWord op2, Condition cc = AL)
+        void sub(int rd, int rn, ARMWord op2, Condition cc = AL)
         {
             emitInstruction(toARMWord(cc) | SUB, rd, rn, op2);
         }
 
-        void subs_r(int rd, int rn, ARMWord op2, Condition cc = AL)
+        void subs(int rd, int rn, ARMWord op2, Condition cc = AL)
         {
             emitInstruction(toARMWord(cc) | SUB | SetConditionalCodes, rd, rn, op2);
         }
 
-        void rsb_r(int rd, int rn, ARMWord op2, Condition cc = AL)
+        void rsb(int rd, int rn, ARMWord op2, Condition cc = AL)
         {
             emitInstruction(toARMWord(cc) | RSB, rd, rn, op2);
         }
 
-        void rsbs_r(int rd, int rn, ARMWord op2, Condition cc = AL)
+        void rsbs(int rd, int rn, ARMWord op2, Condition cc = AL)
         {
             emitInstruction(toARMWord(cc) | RSB | SetConditionalCodes, rd, rn, op2);
         }
 
-        void add_r(int rd, int rn, ARMWord op2, Condition cc = AL)
+        void add(int rd, int rn, ARMWord op2, Condition cc = AL)
         {
             emitInstruction(toARMWord(cc) | ADD, rd, rn, op2);
         }
 
-        void adds_r(int rd, int rn, ARMWord op2, Condition cc = AL)
+        void adds(int rd, int rn, ARMWord op2, Condition cc = AL)
         {
             emitInstruction(toARMWord(cc) | ADD | SetConditionalCodes, rd, rn, op2);
         }
 
-        void adc_r(int rd, int rn, ARMWord op2, Condition cc = AL)
+        void adc(int rd, int rn, ARMWord op2, Condition cc = AL)
         {
             emitInstruction(toARMWord(cc) | ADC, rd, rn, op2);
         }
 
-        void adcs_r(int rd, int rn, ARMWord op2, Condition cc = AL)
+        void adcs(int rd, int rn, ARMWord op2, Condition cc = AL)
         {
             emitInstruction(toARMWord(cc) | ADC | SetConditionalCodes, rd, rn, op2);
         }
 
-        void sbc_r(int rd, int rn, ARMWord op2, Condition cc = AL)
+        void sbc(int rd, int rn, ARMWord op2, Condition cc = AL)
         {
             emitInstruction(toARMWord(cc) | SBC, rd, rn, op2);
         }
 
-        void sbcs_r(int rd, int rn, ARMWord op2, Condition cc = AL)
+        void sbcs(int rd, int rn, ARMWord op2, Condition cc = AL)
         {
             emitInstruction(toARMWord(cc) | SBC | SetConditionalCodes, rd, rn, op2);
         }
 
-        void rsc_r(int rd, int rn, ARMWord op2, Condition cc = AL)
+        void rsc(int rd, int rn, ARMWord op2, Condition cc = AL)
         {
             emitInstruction(toARMWord(cc) | RSC, rd, rn, op2);
         }
 
-        void rscs_r(int rd, int rn, ARMWord op2, Condition cc = AL)
+        void rscs(int rd, int rn, ARMWord op2, Condition cc = AL)
         {
             emitInstruction(toARMWord(cc) | RSC | SetConditionalCodes, rd, rn, op2);
         }
 
-        void tst_r(int rn, ARMWord op2, Condition cc = AL)
+        void tst(int rn, ARMWord op2, Condition cc = AL)
         {
             emitInstruction(toARMWord(cc) | TST | SetConditionalCodes, 0, rn, op2);
         }
 
-        void teq_r(int rn, ARMWord op2, Condition cc = AL)
+        void teq(int rn, ARMWord op2, Condition cc = AL)
         {
             emitInstruction(toARMWord(cc) | TEQ | SetConditionalCodes, 0, rn, op2);
         }
 
-        void cmp_r(int rn, ARMWord op2, Condition cc = AL)
+        void cmp(int rn, ARMWord op2, Condition cc = AL)
         {
             emitInstruction(toARMWord(cc) | CMP | SetConditionalCodes, 0, rn, op2);
         }
 
-        void cmn_r(int rn, ARMWord op2, Condition cc = AL)
+        void cmn(int rn, ARMWord op2, Condition cc = AL)
         {
             emitInstruction(toARMWord(cc) | CMN | SetConditionalCodes, 0, rn, op2);
         }
 
-        void orr_r(int rd, int rn, ARMWord op2, Condition cc = AL)
+        void orr(int rd, int rn, ARMWord op2, Condition cc = AL)
         {
             emitInstruction(toARMWord(cc) | ORR, rd, rn, op2);
         }
 
-        void orrs_r(int rd, int rn, ARMWord op2, Condition cc = AL)
+        void orrs(int rd, int rn, ARMWord op2, Condition cc = AL)
         {
             emitInstruction(toARMWord(cc) | ORR | SetConditionalCodes, rd, rn, op2);
         }
 
-        void mov_r(int rd, ARMWord op2, Condition cc = AL)
+        void mov(int rd, ARMWord op2, Condition cc = AL)
         {
             emitInstruction(toARMWord(cc) | MOV, rd, ARMRegisters::r0, op2);
         }
 
 #if WTF_ARM_ARCH_AT_LEAST(7)
-        void movw_r(int rd, ARMWord op2, Condition cc = AL)
+        void movw(int rd, ARMWord op2, Condition cc = AL)
         {
             ASSERT((op2 | 0xf0fff) == 0xf0fff);
             m_buffer.putInt(toARMWord(cc) | MOVW | RD(rd) | op2);
         }
 
-        void movt_r(int rd, ARMWord op2, Condition cc = AL)
+        void movt(int rd, ARMWord op2, Condition cc = AL)
         {
             ASSERT((op2 | 0xf0fff) == 0xf0fff);
             m_buffer.putInt(toARMWord(cc) | MOVT | RD(rd) | op2);
         }
 #endif
 
-        void movs_r(int rd, ARMWord op2, Condition cc = AL)
+        void movs(int rd, ARMWord op2, Condition cc = AL)
         {
             emitInstruction(toARMWord(cc) | MOV | SetConditionalCodes, rd, ARMRegisters::r0, op2);
         }
 
-        void bic_r(int rd, int rn, ARMWord op2, Condition cc = AL)
+        void bic(int rd, int rn, ARMWord op2, Condition cc = AL)
         {
             emitInstruction(toARMWord(cc) | BIC, rd, rn, op2);
         }
 
-        void bics_r(int rd, int rn, ARMWord op2, Condition cc = AL)
+        void bics(int rd, int rn, ARMWord op2, Condition cc = AL)
         {
             emitInstruction(toARMWord(cc) | BIC | SetConditionalCodes, rd, rn, op2);
         }
 
-        void mvn_r(int rd, ARMWord op2, Condition cc = AL)
+        void mvn(int rd, ARMWord op2, Condition cc = AL)
         {
             emitInstruction(toARMWord(cc) | MVN, rd, ARMRegisters::r0, op2);
         }
 
-        void mvns_r(int rd, ARMWord op2, Condition cc = AL)
+        void mvns(int rd, ARMWord op2, Condition cc = AL)
         {
             emitInstruction(toARMWord(cc) | MVN | SetConditionalCodes, rd, ARMRegisters::r0, op2);
         }
 
-        void mul_r(int rd, int rn, int rm, Condition cc = AL)
+        void mul(int rd, int rn, int rm, Condition cc = AL)
         {
             m_buffer.putInt(toARMWord(cc) | MUL | RN(rd) | RS(rn) | RM(rm));
         }
 
-        void muls_r(int rd, int rn, int rm, Condition cc = AL)
+        void muls(int rd, int rn, int rm, Condition cc = AL)
         {
             m_buffer.putInt(toARMWord(cc) | MUL | SetConditionalCodes | RN(rd) | RS(rn) | RM(rm));
         }
 
-        void mull_r(int rdhi, int rdlo, int rn, int rm, Condition cc = AL)
+        void mull(int rdhi, int rdlo, int rn, int rm, Condition cc = AL)
         {
             m_buffer.putInt(toARMWord(cc) | MULL | RN(rdhi) | RD(rdlo) | RS(rn) | RM(rm));
         }
 
-        void vmov_f64_r(int dd, int dm, Condition cc = AL)
+        void vmov_f64(int dd, int dm, Condition cc = AL)
         {
             emitDoublePrecisionInstruction(toARMWord(cc) | VMOV_F64, dd, 0, dm);
         }
 
-        void vadd_f64_r(int dd, int dn, int dm, Condition cc = AL)
+        void vadd_f64(int dd, int dn, int dm, Condition cc = AL)
         {
             emitDoublePrecisionInstruction(toARMWord(cc) | VADD_F64, dd, dn, dm);
         }
 
-        void vdiv_f64_r(int dd, int dn, int dm, Condition cc = AL)
+        void vdiv_f64(int dd, int dn, int dm, Condition cc = AL)
         {
             emitDoublePrecisionInstruction(toARMWord(cc) | VDIV_F64, dd, dn, dm);
         }
 
-        void vsub_f64_r(int dd, int dn, int dm, Condition cc = AL)
+        void vsub_f64(int dd, int dn, int dm, Condition cc = AL)
         {
             emitDoublePrecisionInstruction(toARMWord(cc) | VSUB_F64, dd, dn, dm);
         }
 
-        void vmul_f64_r(int dd, int dn, int dm, Condition cc = AL)
+        void vmul_f64(int dd, int dn, int dm, Condition cc = AL)
         {
             emitDoublePrecisionInstruction(toARMWord(cc) | VMUL_F64, dd, dn, dm);
         }
 
-        void vcmp_f64_r(int dd, int dm, Condition cc = AL)
+        void vcmp_f64(int dd, int dm, Condition cc = AL)
         {
             emitDoublePrecisionInstruction(toARMWord(cc) | VCMP_F64, dd, 0, dm);
         }
 
-        void vsqrt_f64_r(int dd, int dm, Condition cc = AL)
+        void vsqrt_f64(int dd, int dm, Condition cc = AL)
         {
             emitDoublePrecisionInstruction(toARMWord(cc) | VSQRT_F64, dd, 0, dm);
         }
 
-        void vabs_f64_r(int dd, int dm, Condition cc = AL)
+        void vabs_f64(int dd, int dm, Condition cc = AL)
         {
             emitDoublePrecisionInstruction(toARMWord(cc) | VABS_F64, dd, 0, dm);
         }
 
-        void vneg_f64_r(int dd, int dm, Condition cc = AL)
+        void vneg_f64(int dd, int dm, Condition cc = AL)
         {
             emitDoublePrecisionInstruction(toARMWord(cc) | VNEG_F64, dd, 0, dm);
         }
 
-        void ldr_imm(int rd, ARMWord imm, Condition cc = AL)
+        void ldrImmediate(int rd, ARMWord imm, Condition cc = AL)
         {
             m_buffer.putIntWithConstantInt(toARMWord(cc) | LoadUint32 | DataTransferUp | RN(ARMRegisters::pc) | RD(rd), imm, true);
         }
 
-        void ldr_un_imm(int rd, ARMWord imm, Condition cc = AL)
+        void ldrUniqueImmediate(int rd, ARMWord imm, Condition cc = AL)
         {
             m_buffer.putIntWithConstantInt(toARMWord(cc) | LoadUint32 | DataTransferUp | RN(ARMRegisters::pc) | RD(rd), imm);
         }
 
-        void dtr_u(DataTransferTypeA transferType, int rd, int rb, ARMWord op2, Condition cc = AL)
+        void dtrUp(DataTransferTypeA transferType, int rd, int rb, ARMWord op2, Condition cc = AL)
         {
             emitInstruction(toARMWord(cc) | transferType | DataTransferUp, rd, rb, op2);
         }
 
-        void dtr_ur(DataTransferTypeA transferType, int rd, int rb, int rm, Condition cc = AL)
+        void dtrUpRegister(DataTransferTypeA transferType, int rd, int rb, int rm, Condition cc = AL)
         {
             emitInstruction(toARMWord(cc) | transferType | DataTransferUp | Op2IsRegisterArgument, rd, rb, rm);
         }
 
-        void dtr_d(DataTransferTypeA transferType, int rd, int rb, ARMWord op2, Condition cc = AL)
+        void dtrDown(DataTransferTypeA transferType, int rd, int rb, ARMWord op2, Condition cc = AL)
         {
             emitInstruction(toARMWord(cc) | transferType, rd, rb, op2);
         }
 
-        void dtr_dr(DataTransferTypeA transferType, int rd, int rb, int rm, Condition cc = AL)
+        void dtrDownRegister(DataTransferTypeA transferType, int rd, int rb, int rm, Condition cc = AL)
         {
             emitInstruction(toARMWord(cc) | transferType | Op2IsRegisterArgument, rd, rb, rm);
         }
 
-        void dtrh_u(DataTransferTypeB transferType, int rd, int rb, ARMWord op2, Condition cc = AL)
+        void halfDtrUp(DataTransferTypeB transferType, int rd, int rb, ARMWord op2, Condition cc = AL)
         {
             emitInstruction(toARMWord(cc) | transferType | DataTransferUp, rd, rb, op2);
         }
 
-        void dtrh_ur(DataTransferTypeB transferType, int rd, int rn, int rm, Condition cc = AL)
+        void halfDtrUpRegister(DataTransferTypeB transferType, int rd, int rn, int rm, Condition cc = AL)
         {
             emitInstruction(toARMWord(cc) | transferType | DataTransferUp, rd, rn, rm);
         }
 
-        void dtrh_d(DataTransferTypeB transferType, int rd, int rb, ARMWord op2, Condition cc = AL)
+        void halfDtrDown(DataTransferTypeB transferType, int rd, int rb, ARMWord op2, Condition cc = AL)
         {
             emitInstruction(toARMWord(cc) | transferType, rd, rb, op2);
         }
 
-        void dtrh_dr(DataTransferTypeB transferType, int rd, int rn, int rm, Condition cc = AL)
+        void halfDtrDownRegister(DataTransferTypeB transferType, int rd, int rn, int rm, Condition cc = AL)
         {
             emitInstruction(toARMWord(cc) | transferType, rd, rn, rm);
         }
 
-        void fdtr_u(DataTransferTypeFloat type, int rd, int rb, ARMWord op2, Condition cc = AL)
+        void doubleDtrUp(DataTransferTypeFloat type, int rd, int rb, ARMWord op2, Condition cc = AL)
         {
             ASSERT(op2 <= 0xff && rd <= 15);
             /* Only d0-d15 and s0, s2, s4 ... s30 are supported. */
             m_buffer.putInt(toARMWord(cc) | DataTransferUp | type | (rd << 12) | RN(rb) | op2);
         }
 
-        void fdtr_d(DataTransferTypeFloat type, int rd, int rb, ARMWord op2, Condition cc = AL)
+        void doubleDtrDown(DataTransferTypeFloat type, int rd, int rb, ARMWord op2, Condition cc = AL)
         {
             ASSERT(op2 <= 0xff && rd <= 15);
             /* Only d0-d15 and s0, s2, s4 ... s30 are supported. */
             m_buffer.putInt(toARMWord(cc) | type | (rd << 12) | RN(rb) | op2);
         }
 
-        void push_r(int reg, Condition cc = AL)
+        void push(int reg, Condition cc = AL)
         {
             ASSERT(ARMWord(reg) <= 0xf);
             m_buffer.putInt(toARMWord(cc) | StoreUint32 | DataTransferWriteBack | RN(ARMRegisters::sp) | RD(reg) | 0x4);
         }
 
-        void pop_r(int reg, Condition cc = AL)
+        void pop(int reg, Condition cc = AL)
         {
             ASSERT(ARMWord(reg) <= 0xf);
             m_buffer.putInt(toARMWord(cc) | (LoadUint32 ^ DataTransferPostUpdate) | DataTransferUp | RN(ARMRegisters::sp) | RD(reg) | 0x4);
         }
 
-        inline void poke_r(int reg, Condition cc = AL)
+        inline void poke(int reg, Condition cc = AL)
         {
-            dtr_d(StoreUint32, ARMRegisters::sp, 0, reg, cc);
+            dtrDown(StoreUint32, ARMRegisters::sp, 0, reg, cc);
         }
 
-        inline void peek_r(int reg, Condition cc = AL)
+        inline void peek(int reg, Condition cc = AL)
         {
-            dtr_u(LoadUint32, reg, ARMRegisters::sp, 0, cc);
+            dtrUp(LoadUint32, reg, ARMRegisters::sp, 0, cc);
         }
 
-        void vmov_vfp64_r(int sm, int rt, int rt2, Condition cc = AL)
+        void vmov_vfp64(int sm, int rt, int rt2, Condition cc = AL)
         {
             ASSERT(rt != rt2);
             m_buffer.putInt(toARMWord(cc) | VMOV_VFP64 | RN(rt2) | RD(rt) | (sm & 0xf) | ((sm & 0x10) << (5 - 4)));
         }
 
-        void vmov_arm64_r(int rt, int rt2, int sm, Condition cc = AL)
+        void vmov_arm64(int rt, int rt2, int sm, Condition cc = AL)
         {
             ASSERT(rt != rt2);
             m_buffer.putInt(toARMWord(cc) | VMOV_ARM64 | RN(rt2) | RD(rt) | (sm & 0xf) | ((sm & 0x10) << (5 - 4)));
         }
 
-        void vmov_vfp32_r(int sn, int rt, Condition cc = AL)
+        void vmov_vfp32(int sn, int rt, Condition cc = AL)
         {
             ASSERT(rt <= 15);
             emitSinglePrecisionInstruction(toARMWord(cc) | VMOV_VFP32, rt << 1, sn, 0);
         }
 
-        void vmov_arm32_r(int rt, int sn, Condition cc = AL)
+        void vmov_arm32(int rt, int sn, Condition cc = AL)
         {
             ASSERT(rt <= 15);
             emitSinglePrecisionInstruction(toARMWord(cc) | VMOV_ARM32, rt << 1, sn, 0);
         }
 
-        void vcvt_f64_s32_r(int dd, int sm, Condition cc = AL)
+        void vcvt_f64_s32(int dd, int sm, Condition cc = AL)
         {
             ASSERT(!(sm & 0x1)); // sm must be divisible by 2
             emitDoublePrecisionInstruction(toARMWord(cc) | VCVT_F64_S32, dd, 0, (sm >> 1));
         }
 
-        void vcvt_s32_f64_r(int sd, int dm, Condition cc = AL)
+        void vcvt_s32_f64(int sd, int dm, Condition cc = AL)
         {
             ASSERT(!(sd & 0x1)); // sd must be divisible by 2
             emitDoublePrecisionInstruction(toARMWord(cc) | VCVT_S32_F64, (sd >> 1), 0, dm);
         }
 
-        void vcvt_u32_f64_r(int sd, int dm, Condition cc = AL)
+        void vcvt_u32_f64(int sd, int dm, Condition cc = AL)
         {
             ASSERT(!(sd & 0x1)); // sd must be divisible by 2
             emitDoublePrecisionInstruction(toARMWord(cc) | VCVT_U32_F64, (sd >> 1), 0, dm);
         }
 
-        void vcvt_f64_f32_r(int dd, int sm, Condition cc = AL)
+        void vcvt_f64_f32(int dd, int sm, Condition cc = AL)
         {
             ASSERT(dd <= 15 && sm <= 15);
             emitDoublePrecisionInstruction(toARMWord(cc) | VCVT_F64_F32, dd, 0, sm);
         }
 
-        void vcvt_f32_f64_r(int dd, int sm, Condition cc = AL)
+        void vcvt_f32_f64(int dd, int sm, Condition cc = AL)
         {
             ASSERT(dd <= 15 && sm <= 15);
             emitDoublePrecisionInstruction(toARMWord(cc) | VCVT_F32_F64, dd, 0, sm);
@@ -627,7 +627,7 @@ namespace JSC {
             m_buffer.putInt(toARMWord(cc) | VMRS_APSR);
         }
 
-        void clz_r(int rd, int rm, Condition cc = AL)
+        void clz(int rd, int rm, Condition cc = AL)
         {
             m_buffer.putInt(toARMWord(cc) | CLZ | RD(rd) | RM(rm));
         }
@@ -674,21 +674,21 @@ namespace JSC {
             return reg | (value << 7) | 0x40;
         }
 
-        static ARMWord lsl_r(int reg, int shiftReg)
+        static ARMWord lslRegister(int reg, int shiftReg)
         {
             ASSERT(reg <= ARMRegisters::pc);
             ASSERT(shiftReg <= ARMRegisters::pc);
             return reg | (shiftReg << 8) | 0x10;
         }
 
-        static ARMWord lsr_r(int reg, int shiftReg)
+        static ARMWord lsrRegister(int reg, int shiftReg)
         {
             ASSERT(reg <= ARMRegisters::pc);
             ASSERT(shiftReg <= ARMRegisters::pc);
             return reg | (shiftReg << 8) | 0x30;
         }
 
-        static ARMWord asr_r(int reg, int shiftReg)
+        static ARMWord asrRegister(int reg, int shiftReg)
         {
             ASSERT(reg <= ARMRegisters::pc);
             ASSERT(shiftReg <= ARMRegisters::pc);
@@ -742,7 +742,7 @@ namespace JSC {
         AssemblerLabel align(int alignment)
         {
             while (!m_buffer.isAligned(alignment))
-                mov_r(ARMRegisters::r0, ARMRegisters::r0);
+                mov(ARMRegisters::r0, ARMRegisters::r0);
 
             return label();
         }
@@ -751,7 +751,7 @@ namespace JSC {
         {
             ensureSpace(sizeof(ARMWord), sizeof(ARMWord));
             m_jumps.append(m_buffer.codeSize() | (useConstantPool & 0x1));
-            ldr_un_imm(rd, InvalidBranchTarget, cc);
+            ldrUniqueImmediate(rd, InvalidBranchTarget, cc);
             return m_buffer.label();
         }
 
@@ -767,12 +767,12 @@ namespace JSC {
         // DFG assembly helpers for moving data between fp and registers.
         void vmov(RegisterID rd1, RegisterID rd2, FPRegisterID rn)
         {
-            vmov_arm64_r(rd1, rd2, rn);
+            vmov_arm64(rd1, rd2, rn);
         }
 
         void vmov(FPRegisterID rd, RegisterID rn1, RegisterID rn2)
         {
-            vmov_vfp64_r(rd, rn1, rn2);
+            vmov_vfp64(rd, rn1, rn2);
         }
 
         // Patching helpers