Merge remote-tracking branch 'origin/5.212' into dev

Change-Id: I006cd9023fadc5407bbaa2ddfda45cb8e88b548b

3 files changed, 80 insertions, 45 deletions

diff --git a/Source/JavaScriptCore/assembler/AbstractMacroAssembler.h b/Source/JavaScriptCore/assembler/AbstractMacroAssembler.h
index 1e2d295c9..cbea00e30 100644
--- a/Source/JavaScriptCore/assembler/AbstractMacroAssembler.h
+++ b/Source/JavaScriptCore/assembler/AbstractMacroAssembler.h
@@ -58,6 +58,15 @@ inline bool isARM64()
 #endif
 }
 
+inline bool isMIPS()
+{
+#if CPU(MIPS)
+    return true;
+#else
+    return false;
+#endif
+}
+
 inline bool isX86()
 {
 #if CPU(X86_64) || CPU(X86)
@@ -86,6 +95,11 @@ inline bool optimizeForARM64()
     return isARM64() && Options::useArchitectureSpecificOptimizations();
 }
 
+inline bool optimizeForMIPS()
+{
+    return isMIPS() && Options::useArchitectureSpecificOptimizations();
+}
+
 inline bool optimizeForX86()
 {
     return isX86() && Options::useArchitectureSpecificOptimizations();
diff --git a/Source/JavaScriptCore/assembler/MIPSAssembler.h b/Source/JavaScriptCore/assembler/MIPSAssembler.h
index dc518433e..9fc679086 100644
--- a/Source/JavaScriptCore/assembler/MIPSAssembler.h
+++ b/Source/JavaScriptCore/assembler/MIPSAssembler.h
@@ -733,35 +733,6 @@ public:
     // writable region of memory; to modify the code in an execute-only execuable
     // pool the 'repatch' and 'relink' methods should be used.
 
-    static size_t linkDirectJump(void* code, void* to)
-    {
-        MIPSWord* insn = reinterpret_cast<MIPSWord*>(reinterpret_cast<intptr_t>(code));
-        size_t ops = 0;
-        int32_t slotAddr = reinterpret_cast<int>(insn) + 4;
-        int32_t toAddr = reinterpret_cast<int>(to);
-
-        if ((slotAddr & 0xf0000000) != (toAddr & 0xf0000000)) {
-            // lui
-            *insn = 0x3c000000 | (MIPSRegisters::t9 << OP_SH_RT) | ((toAddr >> 16) & 0xffff);
-            ++insn;
-            // ori
-            *insn = 0x34000000 | (MIPSRegisters::t9 << OP_SH_RT) | (MIPSRegisters::t9 << OP_SH_RS) | (toAddr & 0xffff);
-            ++insn;
-            // jr
-            *insn = 0x00000008 | (MIPSRegisters::t9 << OP_SH_RS);
-            ++insn;
-            ops = 4 * sizeof(MIPSWord);
-        } else {
-            // j
-            *insn = 0x08000000 | ((toAddr & 0x0fffffff) >> 2);
-            ++insn;
-            ops = 2 * sizeof(MIPSWord);
-        }
-        // nop
-        *insn = 0x00000000;
-        return ops;
-    }
-
     void linkJump(AssemblerLabel from, AssemblerLabel to)
     {
         ASSERT(to.isSet());
@@ -881,34 +852,42 @@ public:
 
     static ptrdiff_t maxJumpReplacementSize()
     {
-        return sizeof(MIPSWord) * 4;
+        return sizeof(MIPSWord) * 2;
     }
 
     static void revertJumpToMove(void* instructionStart, RegisterID rt, int imm)
     {
         MIPSWord* insn = static_cast<MIPSWord*>(instructionStart);
-        size_t codeSize = 2 * sizeof(MIPSWord);
 
         // lui
         *insn = 0x3c000000 | (rt << OP_SH_RT) | ((imm >> 16) & 0xffff);
         ++insn;
         // ori
         *insn = 0x34000000 | (rt << OP_SH_RS) | (rt << OP_SH_RT) | (imm & 0xffff);
-        ++insn;
-        // if jr $t9
-        if (*insn == 0x03200008) {
-            *insn = 0x00000000;
-            codeSize += sizeof(MIPSWord);
-        }
-        cacheFlush(insn, codeSize);
+        cacheFlush(insn, 2 * sizeof(MIPSWord));
+    }
+
+    static bool canJumpWithJ(void* instructionStart, void* to)
+    {
+        intptr_t slotAddr = reinterpret_cast<intptr_t>(instructionStart) + 4;
+        intptr_t toAddr = reinterpret_cast<intptr_t>(to);
+        return (slotAddr & 0xf0000000) == (toAddr & 0xf0000000);
     }
 
     static void replaceWithJump(void* instructionStart, void* to)
     {
         ASSERT(!(bitwise_cast<uintptr_t>(instructionStart) & 3));
         ASSERT(!(bitwise_cast<uintptr_t>(to) & 3));
-        size_t ops = linkDirectJump(instructionStart, to);
-        cacheFlush(instructionStart, ops);
+        ASSERT(canJumpWithJ(instructionStart, to));
+        MIPSWord* insn = reinterpret_cast<MIPSWord*>(instructionStart);
+        int32_t toAddr = reinterpret_cast<int32_t>(to);
+
+        // j <to>
+        *insn = 0x08000000 | ((toAddr & 0x0fffffff) >> 2);
+        ++insn;
+        // nop
+        *insn = 0x00000000;
+        cacheFlush(instructionStart, 2 * sizeof(MIPSWord));
     }
 
     static void replaceWithLoad(void* instructionStart)
diff --git a/Source/JavaScriptCore/assembler/MacroAssemblerMIPS.h b/Source/JavaScriptCore/assembler/MacroAssemblerMIPS.h
index a1e67e262..d43ffd22a 100644
--- a/Source/JavaScriptCore/assembler/MacroAssemblerMIPS.h
+++ b/Source/JavaScriptCore/assembler/MacroAssemblerMIPS.h
@@ -816,7 +816,53 @@ public:
 
     void load16Unaligned(BaseIndex address, RegisterID dest)
     {
-        load16(address, dest);
+        if (address.offset >= -32768 && address.offset <= 32767 && !m_fixedWidth) {
+            /*
+                sll     addrtemp, address.index, address.scale
+                addu    addrtemp, addrtemp, address.base
+                lbu     immTemp, address.offset+x(addrtemp) (x=0 for LE, x=1 for BE)
+                lbu     dest, address.offset+x(addrtemp)    (x=1 for LE, x=0 for BE)
+                sll     dest, dest, 8
+                or      dest, dest, immTemp
+            */
+            m_assembler.sll(addrTempRegister, address.index, address.scale);
+            m_assembler.addu(addrTempRegister, addrTempRegister, address.base);
+#if CPU(BIG_ENDIAN)
+            m_assembler.lbu(immTempRegister, addrTempRegister, address.offset + 1);
+            m_assembler.lbu(dest, addrTempRegister, address.offset);
+#else
+            m_assembler.lbu(immTempRegister, addrTempRegister, address.offset);
+            m_assembler.lbu(dest, addrTempRegister, address.offset + 1);
+#endif
+            m_assembler.sll(dest, dest, 8);
+            m_assembler.orInsn(dest, dest, immTempRegister);
+        } else {
+            /*
+                sll     addrTemp, address.index, address.scale
+                addu    addrTemp, addrTemp, address.base
+                lui     immTemp, address.offset >> 16
+                ori     immTemp, immTemp, address.offset & 0xffff
+                addu    addrTemp, addrTemp, immTemp
+                lbu     immTemp, x(addrtemp) (x=0 for LE, x=1 for BE)
+                lbu     dest, x(addrtemp)    (x=1 for LE, x=0 for BE)
+                sll     dest, dest, 8
+                or      dest, dest, immTemp
+            */
+            m_assembler.sll(addrTempRegister, address.index, address.scale);
+            m_assembler.addu(addrTempRegister, addrTempRegister, address.base);
+            m_assembler.lui(immTempRegister, address.offset >> 16);
+            m_assembler.ori(immTempRegister, immTempRegister, address.offset);
+            m_assembler.addu(addrTempRegister, addrTempRegister, immTempRegister);
+#if CPU(BIG_ENDIAN)
+            m_assembler.lbu(immTempRegister, addrTempRegister, 1);
+            m_assembler.lbu(dest, addrTempRegister, 0);
+#else
+            m_assembler.lbu(immTempRegister, addrTempRegister, 0);
+            m_assembler.lbu(dest, addrTempRegister, 1);
+#endif
+            m_assembler.sll(dest, dest, 8);
+            m_assembler.orInsn(dest, dest, immTempRegister);
+        }
     }
 
     void load32WithUnalignedHalfWords(BaseIndex address, RegisterID dest)
@@ -2645,8 +2691,6 @@ public:
 
     Jump branchEqual(RegisterID rs, RegisterID rt)
     {
-        m_assembler.nop();
-        m_assembler.nop();
         m_assembler.appendJump();
         m_assembler.beq(rs, rt, 0);
         m_assembler.nop();
@@ -2656,8 +2700,6 @@ public:
 
     Jump branchNotEqual(RegisterID rs, RegisterID rt)
     {
-        m_assembler.nop();
-        m_assembler.nop();
         m_assembler.appendJump();
         m_assembler.bne(rs, rt, 0);
         m_assembler.nop();