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| author | Liang Qi <liang.qi@qt.io> | 2017-07-04 15:29:25 +0200 |
|---|---|---|
| committer | Liang Qi <liang.qi@qt.io> | 2017-07-04 15:30:15 +0200 |
| commit | db2ecc45564609f940ff564e777f76a1a4b734d4 (patch) | |
| tree | d4756dffb486a2a1c64f13402bafd0327b7ddbb3 /Source/JavaScriptCore/disassembler | |
| parent | 8231f9776c2e4028937411bd2a0886aa72c97831 (diff) | |
| parent | d10511e0a3f655ab2b1dfebfd9c17ade151a7cfe (diff) | |
| download | qtwebkit-db2ecc45564609f940ff564e777f76a1a4b734d4.tar.gz | |
Merge remote-tracking branch 'origin/5.212' into dev
Change-Id: I006cd9023fadc5407bbaa2ddfda45cb8e88b548b
Diffstat (limited to 'Source/JavaScriptCore/disassembler')
18 files changed, 5054 insertions, 3402 deletions
diff --git a/Source/JavaScriptCore/disassembler/udis86/differences.txt b/Source/JavaScriptCore/disassembler/udis86/differences.txt index dc225b6ff..c3dabf6f0 100644 --- a/Source/JavaScriptCore/disassembler/udis86/differences.txt +++ b/Source/JavaScriptCore/disassembler/udis86/differences.txt @@ -5,20 +5,5 @@ here: - assert() has been changed to ASSERT() -- Mass rename of udis86_input.h inp_ prefixed functions and macros to ud_inp_ to - avoid namespace pollution. - -- Removal of KERNEL checks. - -- Added #include of udis86_extern.h in udis86_decode.c. - -- Removed s_ie__pause and s_ie__nop from udis86_decode.c, since they weren't used. - -- Made udis86_syn.h use WTF_ATTRIBUTE_PRINTF. This required making a bunch of little - fixes to make the compiler's format string warnings go away. - -- Made the code in udis86_syn.h use vsnprintf() instead of vsprintf(). - - Fixed udis86_syn-att.c's jump destination printing to work correctly in 64-bit mode. -- Add --outputDir option to itab.py. diff --git a/Source/JavaScriptCore/disassembler/udis86/itab.py b/Source/JavaScriptCore/disassembler/udis86/itab.py deleted file mode 100644 index 3d50ad061..000000000 --- a/Source/JavaScriptCore/disassembler/udis86/itab.py +++ /dev/null @@ -1,360 +0,0 @@ -# udis86 - scripts/itab.py -# -# Copyright (c) 2009 Vivek Thampi -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without modification, -# are permitted provided that the following conditions are met: -# -# * Redistributions of source code must retain the above copyright notice, -# this list of conditions and the following disclaimer. -# * Redistributions in binary form must reproduce the above copyright notice, -# this list of conditions and the following disclaimer in the documentation -# and/or other materials provided with the distribution. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -# ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -from optparse import OptionParser -import os -import sys - -sys.path.append( '../scripts' ); - -import ud_optable -import ud_opcode - -class UdItabGenerator( ud_opcode.UdOpcodeTables ): - - OperandDict = { - "Ap" : [ "OP_A" , "SZ_P" ], - "E" : [ "OP_E" , "SZ_NA" ], - "Eb" : [ "OP_E" , "SZ_B" ], - "Ew" : [ "OP_E" , "SZ_W" ], - "Ev" : [ "OP_E" , "SZ_V" ], - "Ed" : [ "OP_E" , "SZ_D" ], - "Eq" : [ "OP_E" , "SZ_Q" ], - "Ez" : [ "OP_E" , "SZ_Z" ], - "Ex" : [ "OP_E" , "SZ_MDQ" ], - "Ep" : [ "OP_E" , "SZ_P" ], - "G" : [ "OP_G" , "SZ_NA" ], - "Gb" : [ "OP_G" , "SZ_B" ], - "Gw" : [ "OP_G" , "SZ_W" ], - "Gv" : [ "OP_G" , "SZ_V" ], - "Gy" : [ "OP_G" , "SZ_MDQ" ], - "Gy" : [ "OP_G" , "SZ_MDQ" ], - "Gd" : [ "OP_G" , "SZ_D" ], - "Gq" : [ "OP_G" , "SZ_Q" ], - "Gx" : [ "OP_G" , "SZ_MDQ" ], - "Gz" : [ "OP_G" , "SZ_Z" ], - "M" : [ "OP_M" , "SZ_NA" ], - "Mb" : [ "OP_M" , "SZ_B" ], - "Mw" : [ "OP_M" , "SZ_W" ], - "Ms" : [ "OP_M" , "SZ_W" ], - "Md" : [ "OP_M" , "SZ_D" ], - "Mq" : [ "OP_M" , "SZ_Q" ], - "Mt" : [ "OP_M" , "SZ_T" ], - "Mo" : [ "OP_M" , "SZ_O" ], - "MwRv" : [ "OP_MR" , "SZ_WV" ], - "MdRy" : [ "OP_MR" , "SZ_DY" ], - "MbRv" : [ "OP_MR" , "SZ_BV" ], - "I1" : [ "OP_I1" , "SZ_NA" ], - "I3" : [ "OP_I3" , "SZ_NA" ], - "Ib" : [ "OP_I" , "SZ_B" ], - "Isb" : [ "OP_I" , "SZ_SB" ], - "Iw" : [ "OP_I" , "SZ_W" ], - "Iv" : [ "OP_I" , "SZ_V" ], - "Iz" : [ "OP_I" , "SZ_Z" ], - "Jv" : [ "OP_J" , "SZ_V" ], - "Jz" : [ "OP_J" , "SZ_Z" ], - "Jb" : [ "OP_J" , "SZ_B" ], - "R" : [ "OP_R" , "SZ_RDQ" ], - "C" : [ "OP_C" , "SZ_NA" ], - "D" : [ "OP_D" , "SZ_NA" ], - "S" : [ "OP_S" , "SZ_NA" ], - "Ob" : [ "OP_O" , "SZ_B" ], - "Ow" : [ "OP_O" , "SZ_W" ], - "Ov" : [ "OP_O" , "SZ_V" ], - "V" : [ "OP_V" , "SZ_O" ], - "W" : [ "OP_W" , "SZ_O" ], - "Wsd" : [ "OP_W" , "SZ_O" ], - "Wss" : [ "OP_W" , "SZ_O" ], - "P" : [ "OP_P" , "SZ_Q" ], - "Q" : [ "OP_Q" , "SZ_Q" ], - "VR" : [ "OP_VR" , "SZ_O" ], - "PR" : [ "OP_PR" , "SZ_Q" ], - "AL" : [ "OP_AL" , "SZ_NA" ], - "CL" : [ "OP_CL" , "SZ_NA" ], - "DL" : [ "OP_DL" , "SZ_NA" ], - "BL" : [ "OP_BL" , "SZ_NA" ], - "AH" : [ "OP_AH" , "SZ_NA" ], - "CH" : [ "OP_CH" , "SZ_NA" ], - "DH" : [ "OP_DH" , "SZ_NA" ], - "BH" : [ "OP_BH" , "SZ_NA" ], - "AX" : [ "OP_AX" , "SZ_NA" ], - "CX" : [ "OP_CX" , "SZ_NA" ], - "DX" : [ "OP_DX" , "SZ_NA" ], - "BX" : [ "OP_BX" , "SZ_NA" ], - "SI" : [ "OP_SI" , "SZ_NA" ], - "DI" : [ "OP_DI" , "SZ_NA" ], - "SP" : [ "OP_SP" , "SZ_NA" ], - "BP" : [ "OP_BP" , "SZ_NA" ], - "eAX" : [ "OP_eAX" , "SZ_NA" ], - "eCX" : [ "OP_eCX" , "SZ_NA" ], - "eDX" : [ "OP_eDX" , "SZ_NA" ], - "eBX" : [ "OP_eBX" , "SZ_NA" ], - "eSI" : [ "OP_eSI" , "SZ_NA" ], - "eDI" : [ "OP_eDI" , "SZ_NA" ], - "eSP" : [ "OP_eSP" , "SZ_NA" ], - "eBP" : [ "OP_eBP" , "SZ_NA" ], - "rAX" : [ "OP_rAX" , "SZ_NA" ], - "rCX" : [ "OP_rCX" , "SZ_NA" ], - "rBX" : [ "OP_rBX" , "SZ_NA" ], - "rDX" : [ "OP_rDX" , "SZ_NA" ], - "rSI" : [ "OP_rSI" , "SZ_NA" ], - "rDI" : [ "OP_rDI" , "SZ_NA" ], - "rSP" : [ "OP_rSP" , "SZ_NA" ], - "rBP" : [ "OP_rBP" , "SZ_NA" ], - "ES" : [ "OP_ES" , "SZ_NA" ], - "CS" : [ "OP_CS" , "SZ_NA" ], - "DS" : [ "OP_DS" , "SZ_NA" ], - "SS" : [ "OP_SS" , "SZ_NA" ], - "GS" : [ "OP_GS" , "SZ_NA" ], - "FS" : [ "OP_FS" , "SZ_NA" ], - "ST0" : [ "OP_ST0" , "SZ_NA" ], - "ST1" : [ "OP_ST1" , "SZ_NA" ], - "ST2" : [ "OP_ST2" , "SZ_NA" ], - "ST3" : [ "OP_ST3" , "SZ_NA" ], - "ST4" : [ "OP_ST4" , "SZ_NA" ], - "ST5" : [ "OP_ST5" , "SZ_NA" ], - "ST6" : [ "OP_ST6" , "SZ_NA" ], - "ST7" : [ "OP_ST7" , "SZ_NA" ], - "NONE" : [ "OP_NONE" , "SZ_NA" ], - "ALr8b" : [ "OP_ALr8b" , "SZ_NA" ], - "CLr9b" : [ "OP_CLr9b" , "SZ_NA" ], - "DLr10b" : [ "OP_DLr10b" , "SZ_NA" ], - "BLr11b" : [ "OP_BLr11b" , "SZ_NA" ], - "AHr12b" : [ "OP_AHr12b" , "SZ_NA" ], - "CHr13b" : [ "OP_CHr13b" , "SZ_NA" ], - "DHr14b" : [ "OP_DHr14b" , "SZ_NA" ], - "BHr15b" : [ "OP_BHr15b" , "SZ_NA" ], - "rAXr8" : [ "OP_rAXr8" , "SZ_NA" ], - "rCXr9" : [ "OP_rCXr9" , "SZ_NA" ], - "rDXr10" : [ "OP_rDXr10" , "SZ_NA" ], - "rBXr11" : [ "OP_rBXr11" , "SZ_NA" ], - "rSPr12" : [ "OP_rSPr12" , "SZ_NA" ], - "rBPr13" : [ "OP_rBPr13" , "SZ_NA" ], - "rSIr14" : [ "OP_rSIr14" , "SZ_NA" ], - "rDIr15" : [ "OP_rDIr15" , "SZ_NA" ], - "jWP" : [ "OP_J" , "SZ_WP" ], - "jDP" : [ "OP_J" , "SZ_DP" ], - - } - - # - # opcode prefix dictionary - # - PrefixDict = { - "aso" : "P_aso", - "oso" : "P_oso", - "rexw" : "P_rexw", - "rexb" : "P_rexb", - "rexx" : "P_rexx", - "rexr" : "P_rexr", - "seg" : "P_seg", - "inv64" : "P_inv64", - "def64" : "P_def64", - "depM" : "P_depM", - "cast1" : "P_c1", - "cast2" : "P_c2", - "cast3" : "P_c3", - "cast" : "P_cast", - "sext" : "P_sext" - } - - InvalidEntryIdx = 0 - InvalidEntry = { 'type' : 'invalid', - 'mnemonic' : 'invalid', - 'operands' : '', - 'prefixes' : '', - 'meta' : '' } - - Itab = [] # instruction table - ItabIdx = 1 # instruction table index - GtabIdx = 0 # group table index - GtabMeta = [] - - ItabLookup = {} - - MnemonicAliases = ( "invalid", "3dnow", "none", "db", "pause" ) - - def __init__( self, outputDir ): - # first itab entry (0) is Invalid - self.Itab.append( self.InvalidEntry ) - self.MnemonicsTable.extend( self.MnemonicAliases ) - self.outputDir = outputDir - - def toGroupId( self, id ): - return 0x8000 | id - - def genLookupTable( self, table, scope = '' ): - idxArray = [ ] - ( tabIdx, self.GtabIdx ) = ( self.GtabIdx, self.GtabIdx + 1 ) - self.GtabMeta.append( { 'type' : table[ 'type' ], 'meta' : table[ 'meta' ] } ) - - for _idx in range( self.sizeOfTable( table[ 'type' ] ) ): - idx = "%02x" % _idx - - e = self.InvalidEntry - i = self.InvalidEntryIdx - - if idx in table[ 'entries' ].keys(): - e = table[ 'entries' ][ idx ] - - # leaf node (insn) - if e[ 'type' ] == 'insn': - ( i, self.ItabIdx ) = ( self.ItabIdx, self.ItabIdx + 1 ) - self.Itab.append( e ) - elif e[ 'type' ] != 'invalid': - i = self.genLookupTable( e, 'static' ) - - idxArray.append( i ) - - name = "ud_itab__%s" % tabIdx - self.ItabLookup[ tabIdx ] = name - - self.ItabC.write( "\n" ); - if len( scope ): - self.ItabC.write( scope + ' ' ) - self.ItabC.write( "const uint16_t %s[] = {\n" % name ) - for i in range( len( idxArray ) ): - if i > 0 and i % 4 == 0: - self.ItabC.write( "\n" ) - if ( i%4 == 0 ): - self.ItabC.write( " /* %2x */" % i) - if idxArray[ i ] >= 0x8000: - self.ItabC.write( "%12s," % ("GROUP(%d)" % ( ~0x8000 & idxArray[ i ] ))) - else: - self.ItabC.write( "%12d," % ( idxArray[ i ] )) - self.ItabC.write( "\n" ) - self.ItabC.write( "};\n" ) - - return self.toGroupId( tabIdx ) - - def genLookupTableList( self ): - self.ItabC.write( "\n\n" ); - self.ItabC.write( "struct ud_lookup_table_list_entry ud_lookup_table_list[] = {\n" ) - for i in range( len( self.GtabMeta ) ): - f0 = self.ItabLookup[ i ] + "," - f1 = ( self.nameOfTable( self.GtabMeta[ i ][ 'type' ] ) ) + "," - f2 = "\"%s\"" % self.GtabMeta[ i ][ 'meta' ] - self.ItabC.write( " /* %03d */ { %s %s %s },\n" % ( i, f0, f1, f2 ) ) - self.ItabC.write( "};" ) - - def genInsnTable( self ): - self.ItabC.write( "struct ud_itab_entry ud_itab[] = {\n" ); - idx = 0 - for e in self.Itab: - opr_c = [ "O_NONE", "O_NONE", "O_NONE" ] - pfx_c = [] - opr = e[ 'operands' ] - for i in range(len(opr)): - if not (opr[i] in self.OperandDict.keys()): - print("error: invalid operand declaration: %s\n" % opr[i]) - opr_c[i] = "O_" + opr[i] - opr = "%s %s %s" % (opr_c[0] + ",", opr_c[1] + ",", opr_c[2]) - - for p in e['prefixes']: - if not ( p in self.PrefixDict.keys() ): - print("error: invalid prefix specification: %s \n" % pfx) - pfx_c.append( self.PrefixDict[p] ) - if len(e['prefixes']) == 0: - pfx_c.append( "P_none" ) - pfx = "|".join( pfx_c ) - - self.ItabC.write( " /* %04d */ { UD_I%s %s, %s },\n" \ - % ( idx, e[ 'mnemonic' ] + ',', opr, pfx ) ) - idx += 1 - self.ItabC.write( "};\n" ) - - self.ItabC.write( "\n\n" ); - self.ItabC.write( "const char * ud_mnemonics_str[] = {\n" ) - self.ItabC.write( ",\n ".join( [ "\"%s\"" % m for m in self.MnemonicsTable ] ) ) - self.ItabC.write( "\n};\n" ) - - - def genItabH( self ): - self.ItabH = open( os.path.join(self.outputDir, "udis86_itab.h"), "w" ) - - # Generate Table Type Enumeration - self.ItabH.write( "#ifndef UD_ITAB_H\n" ) - self.ItabH.write( "#define UD_ITAB_H\n\n" ) - - # table type enumeration - self.ItabH.write( "/* ud_table_type -- lookup table types (see lookup.c) */\n" ) - self.ItabH.write( "enum ud_table_type {\n " ) - enum = [ self.TableInfo[ k ][ 'name' ] for k in self.TableInfo.keys() ] - self.ItabH.write( ",\n ".join( enum ) ) - self.ItabH.write( "\n};\n\n" ); - - # mnemonic enumeration - self.ItabH.write( "/* ud_mnemonic -- mnemonic constants */\n" ) - enum = "enum ud_mnemonic_code {\n " - enum += ",\n ".join( [ "UD_I%s" % m for m in self.MnemonicsTable ] ) - enum += "\n} UD_ATTR_PACKED;\n" - self.ItabH.write( enum ) - self.ItabH.write( "\n" ) - - self.ItabH.write("\n/* itab entry operand definitions */\n"); - operands = self.OperandDict.keys() - operands.sort() - for o in operands: - self.ItabH.write("#define O_%-7s { %-12s %-8s }\n" % - (o, self.OperandDict[o][0] + ",", self.OperandDict[o][1])); - self.ItabH.write("\n\n"); - - self.ItabH.write( "extern const char * ud_mnemonics_str[];\n" ) - - self.ItabH.write( "#define GROUP(n) (0x8000 | (n))" ) - - self.ItabH.write( "\n#endif /* UD_ITAB_H */\n" ) - - self.ItabH.close() - - - def genItabC( self ): - self.ItabC = open( os.path.join(self.outputDir, "udis86_itab.c"), "w" ) - self.ItabC.write( "/* itab.c -- generated by itab.py, do no edit" ) - self.ItabC.write( " */\n" ); - self.ItabC.write( "#include \"udis86_decode.h\"\n\n" ); - - self.genLookupTable( self.OpcodeTable0 ) - self.genLookupTableList() - self.genInsnTable() - - self.ItabC.close() - - def genItab( self ): - self.genItabC() - self.genItabH() - -def main(): - parser = OptionParser() - parser.add_option("--outputDir", dest="outputDir", default="") - options, args = parser.parse_args() - generator = UdItabGenerator(os.path.normpath(options.outputDir)) - optableXmlParser = ud_optable.UdOptableXmlParser() - optableXmlParser.parse( args[ 0 ], generator.addInsnDef ) - - generator.genItab() - -if __name__ == '__main__': - main() diff --git a/Source/JavaScriptCore/disassembler/udis86/optable.xml b/Source/JavaScriptCore/disassembler/udis86/optable.xml index 14b4ac593..3bda8587e 100644 --- a/Source/JavaScriptCore/disassembler/udis86/optable.xml +++ b/Source/JavaScriptCore/disassembler/udis86/optable.xml @@ -2,37 +2,132 @@ <?xml-stylesheet href="optable.xsl" type="text/xsl"?> <x86optable> + <!-- + The most important elements of each instruction definition are the + pfx (prefix), opc (opcode), and opr (operand) elements. Each is a + CDATA element consisting of blank-separated words. Upper and lower + case are equivalent. + + <pfx></pfx> + + pfx describes the set of valid prefixes that can precede the main + opcode without turning it into a different instruction. These may + be: + + aso accepts address size override + oso accepts operand size override + seg accepts a segment override + rexw, rexr, rexx, rexb + uses the indicated REX bit + vexl accepts the vex.L prefix bit, in other words, the vexl + bit can be used in the decoding of the avx instruction. + + <opr></opr> + + [T][s] + + Size Suffix + =========== + + x - If vex.L = 1 => m256/YMM + vex.L = 0 => m128/XMM + + opc words may be actual byte values (two hex digits), or may be one of + the following: + /sse=66,f3,f2 - required prefix (always first, and always + followed by 0f) + /3dnow=00-ff - this is a 3DNow opcode (only in a definition of the + form 0f 0f 3dnow=<byte>) + /a=16,32,64 - has this address size + /m=16,32,64,!64 - applicable only when the CPU is in this mode + /o=16,32,64 - has this operand size + /mod=11,!11 - has ModR/M with 11 or not-11 in the Mod field + /reg=0-7 - has ModR/M with this value in the reg field + /rm=0-7 - has ModR/M with this value in the R/M field (only with + /mod=11) + /x87=00-3f - X87 opcode with this value in the low 6 bits of the + following "ModR/M" byte (only with /mod=11 and no other modifiers) + + opr words follow the Intel documentation somewhat, and specify the + location and the size of the operand. The OperandDict table in + ud_itab.py maps these words to named OP_ and SZ_ constants for the + location and size respectively. These constants are defined in + decode.h, q.v. for details. + + The mode element affects instruction semantics but not decoding: + inv64 - invalid in 64-bit mode + def64 - default operand size is 64 bits in 64-bit mode + + cpuid + + The cpuid element maybe applied to an instruction or a specific + definition of the instruction. One ore more strings define the + cpuid features that the instruction (or a definition belongs to) + + Values are: sse, sse2, sse3, sse4, sse4.1, sse4.2, avx + + AVX Instructions + + AVX instructions can be described in two ways. One, the explicit + form, and the other that promotes an existing sse instruction + definition to its avx form. + + If an instruction is defined to be in cpuid=avx, but is defined in + the legacy form (using /sse= extensions), then the opcode generator + will infer that as two definitions, one the see instruction and the + other, an inferred avx instruction. + + In generating the sse definition from the above, the following + transformations happen, + + - /vexw and /vexl extensions (if any) are removed + - The operands H and L are removed. Operands specified on + the right to removed operands are shifted to the left + position. + - The vexl prefix is removed. + - "avx" is removed form the cpuid definition. + + In generating the avx definition from the above, the following + transformations happen, + + - c4 is inserted in the 0th position of the opcode string + - /sse extension is removed + - A new /vex extension is constructed using /sse, 0f, 38 and + 3a opcodes (if any). + - Operands V, W, H, and U are marked explicitly to have the + size suffix "x" + + If the above transformations do not generate the required + definitions, the instructions will need to be defined separately. + --> + <instruction> <mnemonic>aaa</mnemonic> <def> - <opc>37</opc> - <mode>inv64</mode> + <opc>37 /m=!64</opc> </def> </instruction> <instruction> <mnemonic>aad</mnemonic> <def> - <opc>d5</opc> + <opc>d5 /m=!64</opc> <opr>Ib</opr> - <mode>inv64</mode> </def> </instruction> <instruction> <mnemonic>aam</mnemonic> <def> - <opc>d4</opc> + <opc>d4 /m=!64</opc> <opr>Ib</opr> - <mode>inv64</mode> </def> </instruction> <instruction> <mnemonic>aas</mnemonic> <def> - <opc>3f</opc> - <mode>inv64</mode> + <opc>3f /m=!64</opc> </def> </instruction> @@ -65,8 +160,7 @@ <def> <pfx>oso rexw</pfx> <opc>15</opc> - <opr>rAX Iz</opr> - <syn>sext</syn> + <opr>rAX sIz</opr> </def> <def> <pfx>aso rexr rexx rexb</pfx> @@ -75,21 +169,19 @@ </def> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>82 /reg=2</opc> + <opc>82 /reg=2 /m=!64</opc> <opr>Eb Ib</opr> <mode>inv64</mode> </def> <def> <pfx>aso oso rexw rexr rexx rexb</pfx> <opc>81 /reg=2</opc> - <opr>Ev Iz</opr> - <syn>sext</syn> + <opr>Ev sIz</opr> </def> <def> <pfx>aso oso rexw rexr rexx rexb</pfx> <opc>83 /reg=2</opc> - <opr>Ev Ib</opr> - <syn>sext</syn> + <opr>Ev sIb</opr> </def> </instruction> @@ -122,8 +214,7 @@ <def> <pfx>oso rexw</pfx> <opc>05</opc> - <opr>rAX Iz</opr> - <syn>sext</syn> + <opr>rAX sIz</opr> </def> <def> <pfx>aso rexr rexx rexb</pfx> @@ -132,43 +223,39 @@ </def> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>82 /reg=0</opc> + <opc>82 /reg=0 /m=!64</opc> <opr>Eb Ib</opr> <mode>inv64</mode> </def> <def> <pfx>aso oso rexw rexr rexx rexb</pfx> <opc>81 /reg=0</opc> - <opr>Ev Iz</opr> - <syn>sext</syn> + <opr>Ev sIz</opr> </def> <def> <pfx>aso oso rexw rexr rexx rexb</pfx> <opc>83 /reg=0</opc> - <opr>Ev Ib</opr> - <syn>sext</syn> + <opr>Ev sIb</opr> </def> </instruction> - <!-- - SSE2 - --> - <instruction> <mnemonic>addpd</mnemonic> <def> - <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 58</opc> - <opr>V W</opr> + <pfx>aso rexr rexx rexb vexl</pfx> + <opc>/sse=66 0f 58</opc> + <opr>V H W</opr> + <cpuid>sse2 avx</cpuid> </def> </instruction> <instruction> <mnemonic>addps</mnemonic> <def> - <pfx>aso rexr rexx rexb</pfx> + <pfx>aso rexr rexx rexb vexl</pfx> <opc>0f 58</opc> - <opr>V W</opr> + <opr>V H W</opr> + <cpuid>sse avx</cpuid> </def> </instruction> @@ -176,8 +263,9 @@ <mnemonic>addsd</mnemonic> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>ssef2 0f 58</opc> - <opr>V W</opr> + <opc>/sse=f2 0f 58</opc> + <opr>V H W</opr> + <cpuid>sse2 avx</cpuid> </def> </instruction> @@ -185,12 +273,94 @@ <mnemonic>addss</mnemonic> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>ssef3 0f 58</opc> + <opc>/sse=f3 0f 58</opc> + <opr>V H W</opr> + <cpuid>sse avx</cpuid> + </def> + </instruction> + + <instruction> + <mnemonic>addsubpd</mnemonic> + <def> + <pfx>aso rexr rexx rexb</pfx> + <opc>/sse=66 0f d0</opc> + <opr>V H W</opr> + <cpuid>sse3 avx</cpuid> + </def> + </instruction> + + <instruction> + <mnemonic>addsubps</mnemonic> + <def> + <pfx>aso rexr rexx rexb</pfx> + <opc>/sse=f2 0f d0</opc> + <opr>V H W</opr> + <cpuid>sse3 avx</cpuid> + </def> + </instruction> + + <instruction> + <mnemonic>aesdec</mnemonic> + <def> + <pfx>aso rexr rexx rexb</pfx> + <opc>/sse=66 0f 38 de</opc> + <opr>V H W</opr> + <cpuid>aesni avx</cpuid> + </def> + </instruction> + + <instruction> + <mnemonic>aesdeclast</mnemonic> + <def> + <pfx>aso rexr rexx rexb</pfx> + <opc>/sse=66 0f 38 df</opc> <opr>V W</opr> + <cpuid>aesni avx</cpuid> </def> </instruction> - <instruction> + <instruction> + <mnemonic>aesenc</mnemonic> + <cpuid>aesni</cpuid> + <def> + <pfx>aso rexr rexx rexb</pfx> + <opc>/sse=66 0f 38 dc</opc> + <opr>V W</opr> + <cpuid>aesni avx</cpuid> + </def> + </instruction> + + <instruction> + <mnemonic>aesenclast</mnemonic> + <cpuid>aesni avx</cpuid> + <def> + <pfx>aso rexr rexx rexb</pfx> + <opc>/sse=66 0f 38 dd</opc> + <opr>V H W</opr> + </def> + </instruction> + + <instruction> + <mnemonic>aesimc</mnemonic> + <def> + <pfx>aso rexr rexx rexb</pfx> + <opc>/sse=66 0f 38 db</opc> + <opr>V W</opr> + <cpuid>aesni avx</cpuid> + </def> + </instruction> + + <instruction> + <mnemonic>aeskeygenassist</mnemonic> + <def> + <pfx>aso rexr rexx rexb</pfx> + <opc>/sse=66 0f 3a df</opc> + <opr>V W Ib</opr> + <cpuid>aesni avx</cpuid> + </def> + </instruction> + + <instruction> <mnemonic>and</mnemonic> <def> <pfx>aso rexr rexx rexb</pfx> @@ -219,8 +389,7 @@ <def> <pfx>oso rexw</pfx> <opc>25</opc> - <opr>rAX Iz</opr> - <syn>sext</syn> + <opr>rAX sIz</opr> </def> <def> <pfx>aso rexw rexr rexx rexb</pfx> @@ -229,30 +398,29 @@ </def> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>82 /reg=4</opc> + <opc>82 /reg=4 /m=!64</opc> <opr>Eb Ib</opr> <mode>inv64</mode> </def> <def> <pfx>aso oso rexw rexr rexx rexb</pfx> <opc>81 /reg=4</opc> - <opr>Ev Iz</opr> - <syn>sext</syn> + <opr>Ev sIz</opr> </def> <def> <pfx>aso oso rexw rexr rexx rexb</pfx> <opc>83 /reg=4</opc> - <opr>Ev Ib</opr> - <syn>sext</syn> + <opr>Ev sIb</opr> </def> </instruction> <instruction> <mnemonic>andpd</mnemonic> <def> - <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 54</opc> - <opr>V W</opr> + <pfx>aso rexr rexx rexb vexl</pfx> + <opc>/sse=66 0f 54</opc> + <opr>V H W</opr> + <cpuid>sse2 avx</cpuid> </def> </instruction> @@ -261,7 +429,8 @@ <def> <pfx>aso rexr rexx rexb</pfx> <opc>0f 54</opc> - <opr>V W</opr> + <opr>V H W</opr> + <cpuid>sse avx</cpuid> </def> </instruction> @@ -269,8 +438,9 @@ <mnemonic>andnpd</mnemonic> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 55</opc> - <opr>V W</opr> + <opc>/sse=66 0f 55</opc> + <opr>V H W</opr> + <cpuid>sse2 avx</cpuid> </def> </instruction> @@ -279,7 +449,8 @@ <def> <pfx>aso rexr rexx rexb</pfx> <opc>0f 55</opc> - <opr>V W</opr> + <opr>V H W</opr> + <cpuid>sse2 avx</cpuid> </def> </instruction> @@ -287,15 +458,8 @@ <mnemonic>arpl</mnemonic> <def> <pfx>aso</pfx> - <opc>63 /m=16</opc> - <opr>Ew Gw</opr> - <mode>inv64</mode> - </def> - <def> - <pfx>aso</pfx> - <opc>63 /m=32</opc> + <opc>63 /m=!64</opc> <opr>Ew Gw</opr> - <mode>inv64</mode> </def> </instruction> @@ -304,150 +468,27 @@ <def> <pfx>aso oso rexw rexx rexr rexb</pfx> <opc>63 /m=64</opc> - <opr>Gv Ed</opr> - </def> - </instruction> - - <instruction> - <mnemonic>bound</mnemonic> - <def> - <pfx>aso oso</pfx> - <opc>62</opc> - <opr>Gv M</opr> - <mode>inv64</mode> - </def> - </instruction> - - <instruction> - <mnemonic>bsf</mnemonic> - <def> - <pfx>aso oso rexw rexr rexx rexb</pfx> - <opc>0f bc</opc> - <opr>Gv Ev</opr> - </def> - </instruction> - - <instruction> - <mnemonic>bsr</mnemonic> - <def> - <pfx>aso oso rexw rexr rexx rexb</pfx> - <opc>0f bd</opc> - <opr>Gv Ev</opr> - </def> - </instruction> - - <instruction> - <mnemonic>bswap</mnemonic> - <def> - <pfx>oso rexw rexb</pfx> - <opc>0f c8</opc> - <opr>rAXr8</opr> - </def> - <def> - <pfx>oso rexw rexb</pfx> - <opc>0f c9</opc> - <opr>rCXr9</opr> - </def> - <def> - <pfx>oso rexw rexb</pfx> - <opc>0f ca</opc> - <opr>rDXr10</opr> - </def> - <def> - <pfx>oso rexw rexb</pfx> - <opc>0f cb</opc> - <opr>rBXr11</opr> - </def> - <def> - <pfx>oso rexw rexb</pfx> - <opc>0f cc</opc> - <opr>rSPr12</opr> - </def> - <def> - <pfx>oso rexw rexb</pfx> - <opc>0f cd</opc> - <opr>rBPr13</opr> - </def> - <def> - <pfx>oso rexw rexb</pfx> - <opc>0f ce</opc> - <opr>rSIr14</opr> - </def> - <def> - <pfx>oso rexw rexb</pfx> - <opc>0f cf</opc> - <opr>rDIr15</opr> - </def> - </instruction> - - <instruction> - <mnemonic>bt</mnemonic> - <def> - <pfx>aso oso rexw rexr rexx rexb</pfx> - <opc>0f ba /reg=4</opc> - <opr>Ev Ib</opr> - </def> - <def> - <pfx>aso oso rexw rexr rexx rexb</pfx> - <opc>0f a3</opc> - <opr>Ev Gv</opr> - </def> - </instruction> - - <instruction> - <mnemonic>btc</mnemonic> - <def> - <pfx>aso oso rexw rexr rexx rexb</pfx> - <opc>0f bb</opc> - <opr>Ev Gv</opr> - </def> - <def> - <pfx>aso oso rexw rexr rexx rexb</pfx> - <opc>0f ba /reg=7</opc> - <opr>Ev Ib</opr> - </def> - </instruction> - - <instruction> - <mnemonic>btr</mnemonic> - <def> - <pfx>aso oso rexw rexr rexx rexb</pfx> - <opc>0f b3</opc> - <opr>Ev Gv</opr> - </def> - <def> - <pfx>aso oso rexw rexr rexx rexb</pfx> - <opc>0f ba /reg=6</opc> - <opr>Ev Ib</opr> + <opr>Gq Ed</opr> </def> </instruction> <instruction> - <mnemonic>bts</mnemonic> - <def> - <pfx>aso oso rexw rexr rexx rexb</pfx> - <opc>0f ab</opc> - <opr>Ev Gv</opr> - </def> + <mnemonic>call</mnemonic> <def> <pfx>aso oso rexw rexr rexx rexb</pfx> - <opc>0f ba /reg=5</opc> - <opr>Ev Ib</opr> + <opc>ff /reg=2 /m=!64</opc> + <opr>Ev</opr> </def> - </instruction> - - <instruction> - <mnemonic>call</mnemonic> <def> <pfx>aso oso rexw rexr rexx rexb</pfx> - <opc>ff /reg=2</opc> - <opr>Ev</opr> + <opc>ff /reg=2 /m=64</opc> + <opr>Eq</opr> <mode>def64</mode> </def> <def> <pfx>aso oso rexw rexr rexx rexb</pfx> <opc>ff /reg=3</opc> - <opr>Ep</opr> + <opr>Fv</opr> </def> <def> <pfx>oso</pfx> @@ -457,9 +498,8 @@ </def> <def> <pfx>oso</pfx> - <opc>9a</opc> - <opr>Ap</opr> - <mode>inv64</mode> + <opc>9a /m=!64</opc> + <opr>Av</opr> </def> </instruction> @@ -712,7 +752,7 @@ <def> <pfx>oso rexw</pfx> <opc>3d</opc> - <opr>rAX Iz</opr> + <opr>rAX sIz</opr> </def> <def> <pfx>aso rexr rexx rexb</pfx> @@ -721,43 +761,46 @@ </def> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>82 /reg=7</opc> + <opc>82 /reg=7 /m=!64</opc> <opr>Eb Ib</opr> <mode>inv64</mode> </def> <def> <pfx>aso oso rexw rexr rexx rexb</pfx> <opc>81 /reg=7</opc> - <opr>Ev Iz</opr> + <opr>Ev sIz</opr> </def> <def> <pfx>aso oso rexw rexr rexx rexb</pfx> <opc>83 /reg=7</opc> - <opr>Ev Ib</opr> + <opr>Ev sIb</opr> </def> </instruction> <instruction> <mnemonic>cmppd</mnemonic> <def> - <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f c2</opc> - <opr>V W Ib</opr> + <pfx>aso rexr rexx rexb vexl</pfx> + <opc>/sse=66 0f c2</opc> + <opr>V H W Ib</opr> + <cpuid>sse2 avx</cpuid> </def> </instruction> <instruction> <mnemonic>cmpps</mnemonic> <def> - <pfx>aso rexr rexx rexb</pfx> + <pfx>aso rexr rexx rexb vexl</pfx> <opc>0f c2</opc> - <opr>V W Ib</opr> + <opr>V H W Ib</opr> + <cpuid>sse2 avx</cpuid> </def> </instruction> <instruction> <mnemonic>cmpsb</mnemonic> <def> + <pfx>repz seg</pfx> <opc>a6</opc> </def> </instruction> @@ -765,7 +808,7 @@ <instruction> <mnemonic>cmpsw</mnemonic> <def> - <pfx>oso rexw</pfx> + <pfx>repz oso rexw seg</pfx> <opc>a7 /o=16</opc> </def> </instruction> @@ -773,20 +816,21 @@ <instruction> <mnemonic>cmpsd</mnemonic> <def> - <pfx>oso rexw</pfx> + <pfx>repz oso rexw seg</pfx> <opc>a7 /o=32</opc> </def> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>ssef2 0f c2</opc> - <opr>V W Ib</opr> + <opc>/sse=f2 0f c2</opc> + <opr>V H W Ib</opr> + <cpuid>sse2 avx</cpuid> </def> </instruction> <instruction> <mnemonic>cmpsq</mnemonic> <def> - <pfx>oso rexw</pfx> + <pfx>repz oso rexw seg</pfx> <opc>a7 /o=64</opc> </def> </instruction> @@ -795,8 +839,9 @@ <mnemonic>cmpss</mnemonic> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>ssef3 0f c2</opc> - <opr>V W Ib</opr> + <opc>/sse=f3 0f c2</opc> + <opr>V H W Ib</opr> + <cpuid>sse2 avx</cpuid> </def> </instruction> @@ -818,7 +863,21 @@ <mnemonic>cmpxchg8b</mnemonic> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>0f c7 /reg=1</opc> + <opc>0f c7 /mod=!11 /reg=1 /o=16</opc> + <opr>M</opr> + </def> + <def> + <pfx>aso rexr rexx rexb</pfx> + <opc>0f c7 /mod=!11 /reg=1 /o=32</opc> + <opr>M</opr> + </def> + </instruction> + + <instruction> + <mnemonic>cmpxchg16b</mnemonic> + <def> + <pfx>aso rexr rexx rexb</pfx> + <opc>0f c7 /mod=!11 /reg=1 /o=64</opc> <opr>M</opr> </def> </instruction> @@ -827,8 +886,9 @@ <mnemonic>comisd</mnemonic> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 2f</opc> - <opr>V W</opr> + <opc>/sse=66 0f 2f</opc> + <opr>Vsd Wsd</opr> + <cpuid>sse2 avx</cpuid> </def> </instruction> @@ -838,6 +898,7 @@ <pfx>aso rexr rexx rexb</pfx> <opc>0f 2f</opc> <opr>V W</opr> + <cpuid>sse2 avx</cpuid> </def> </instruction> @@ -851,9 +912,10 @@ <instruction> <mnemonic>cvtdq2pd</mnemonic> <def> - <pfx>aso rexr rexx rexb</pfx> - <opc>ssef3 0f e6</opc> - <opr>V W</opr> + <pfx>aso rexr rexx rexb vexl</pfx> + <opc>/sse=f3 0f e6</opc> + <opr>V Wdq</opr> + <cpuid>sse2 avx</cpuid> </def> </instruction> @@ -863,15 +925,17 @@ <pfx>aso rexr rexx rexb</pfx> <opc>0f 5b</opc> <opr>V W</opr> + <cpuid>sse2 avx</cpuid> </def> </instruction> <instruction> <mnemonic>cvtpd2dq</mnemonic> <def> - <pfx>aso rexr rexx rexb</pfx> - <opc>ssef2 0f e6</opc> - <opr>V W</opr> + <pfx>aso rexr rexx rexb vexl</pfx> + <opc>/sse=f2 0f e6</opc> + <opr>Vdq W</opr> + <cpuid>sse2 avx</cpuid> </def> </instruction> @@ -879,7 +943,7 @@ <mnemonic>cvtpd2pi</mnemonic> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 2d</opc> + <opc>/sse=66 0f 2d</opc> <opr>P W</opr> </def> </instruction> @@ -887,9 +951,10 @@ <instruction> <mnemonic>cvtpd2ps</mnemonic> <def> - <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 5a</opc> - <opr>V W</opr> + <pfx>aso rexr rexx rexb vexl</pfx> + <opc>/sse=66 0f 5a</opc> + <opr>Vdq W</opr> + <cpuid>sse2 avx</cpuid> </def> </instruction> @@ -906,7 +971,7 @@ <mnemonic>cvtpi2pd</mnemonic> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 2a</opc> + <opc>/sse=66 0f 2a</opc> <opr>V Q</opr> </def> </instruction> @@ -914,27 +979,29 @@ <instruction> <mnemonic>cvtps2dq</mnemonic> <def> - <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 5b</opc> + <pfx>aso rexr rexx rexb vexl</pfx> + <opc>/sse=66 0f 5b</opc> <opr>V W</opr> + <cpuid>sse2 avx</cpuid> </def> </instruction> <instruction> - <mnemonic>cvtps2pi</mnemonic> + <mnemonic>cvtps2pd</mnemonic> <def> - <pfx>aso rexr rexx rexb</pfx> - <opc>0f 2d</opc> - <opr>P W</opr> + <pfx>aso rexr rexx rexb vexl</pfx> + <opc>0f 5a</opc> + <opr>V Wdq</opr> + <cpuid>sse2 avx</cpuid> </def> </instruction> <instruction> - <mnemonic>cvtps2pd</mnemonic> + <mnemonic>cvtps2pi</mnemonic> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>0f 5a</opc> - <opr>V W</opr> + <opc>0f 2d</opc> + <opr>P MqU</opr> </def> </instruction> @@ -942,8 +1009,9 @@ <mnemonic>cvtsd2si</mnemonic> <def> <pfx>aso rexw rexr rexx rexb</pfx> - <opc>ssef2 0f 2d</opc> - <opr>Gy W</opr> + <opc>/sse=f2 0f 2d</opc> + <opr>Gy MqU</opr> + <cpuid>sse2 avx</cpuid> </def> </instruction> @@ -951,26 +1019,29 @@ <mnemonic>cvtsd2ss</mnemonic> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>ssef2 0f 5a</opc> - <opr>V W</opr> + <opc>/sse=f2 0f 5a</opc> + <opr>V H W</opr> + <cpuid>sse2 avx</cpuid> </def> </instruction> <instruction> - <mnemonic>cvtsi2ss</mnemonic> + <mnemonic>cvtsi2sd</mnemonic> <def> <pfx>aso rexw rexr rexx rexb</pfx> - <opc>ssef3 0f 2a</opc> - <opr>V Ex</opr> + <opc>/sse=f2 0f 2a</opc> + <opr>V H Ey</opr> + <cpuid>sse2 avx</cpuid> </def> </instruction> <instruction> - <mnemonic>cvtss2si</mnemonic> + <mnemonic>cvtsi2ss</mnemonic> <def> <pfx>aso rexw rexr rexx rexb</pfx> - <opc>ssef3 0f 2d</opc> - <opr>Gy W</opr> + <opc>/sse=f3 0f 2a</opc> + <opr>V H Ey</opr> + <cpuid>sse avx</cpuid> </def> </instruction> @@ -978,35 +1049,48 @@ <mnemonic>cvtss2sd</mnemonic> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>ssef3 0f 5a</opc> - <opr>V W</opr> + <opc>/sse=f3 0f 5a</opc> + <opr>V H W</opr> + <cpuid>sse2 avx</cpuid> </def> </instruction> <instruction> - <mnemonic>cvttpd2pi</mnemonic> + <mnemonic>cvtss2si</mnemonic> <def> - <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 2c</opc> - <opr>P W</opr> + <pfx>aso rexw rexr rexx rexb</pfx> + <opc>/sse=f3 0f 2d</opc> + <opr>Gy MdU</opr> + <cpuid>sse avx</cpuid> </def> </instruction> <instruction> <mnemonic>cvttpd2dq</mnemonic> <def> + <pfx>aso rexr rexx rexb vexl</pfx> + <opc>/sse=66 0f e6</opc> + <opr>Vdq W</opr> + <cpuid>sse2 avx</cpuid> + </def> + </instruction> + + <instruction> + <mnemonic>cvttpd2pi</mnemonic> + <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f e6</opc> - <opr>V W</opr> + <opc>/sse=66 0f 2c</opc> + <opr>P W</opr> </def> </instruction> <instruction> <mnemonic>cvttps2dq</mnemonic> <def> - <pfx>aso rexr rexx rexb</pfx> - <opc>ssef3 0f 5b</opc> + <pfx>aso rexr rexx rexb vexl</pfx> + <opc>/sse=f3 0f 5b</opc> <opr>V W</opr> + <cpuid>sse2 avx</cpuid> </def> </instruction> @@ -1023,17 +1107,9 @@ <mnemonic>cvttsd2si</mnemonic> <def> <pfx>aso rexw rexr rexx rexb</pfx> - <opc>ssef2 0f 2c</opc> - <opr>Gy Wsd</opr> - </def> - </instruction> - - <instruction> - <mnemonic>cvtsi2sd</mnemonic> - <def> - <pfx>aso rexw rexr rexx rexb</pfx> - <opc>ssef2 0f 2a</opc> - <opr>V Ex</opr> + <opc>/sse=f2 0f 2c</opc> + <opr>Gy MqU</opr> + <cpuid>sse2 avx</cpuid> </def> </instruction> @@ -1041,8 +1117,9 @@ <mnemonic>cvttss2si</mnemonic> <def> <pfx>aso rexw rexr rexx rexb</pfx> - <opc>ssef3 0f 2c</opc> - <opr>Gy Wsd</opr> + <opc>/sse=f3 0f 2c</opc> + <opr>Gy MdU</opr> + <cpuid>sse2 avx</cpuid> </def> </instruction> @@ -1073,7 +1150,7 @@ <instruction> <mnemonic>daa</mnemonic> <def> - <opc>27</opc> + <opc>27 /m=!64</opc> <mode>inv64</mode> </def> </instruction> @@ -1081,7 +1158,7 @@ <instruction> <mnemonic>das</mnemonic> <def> - <opc>2f</opc> + <opc>2f /m=!64</opc> <mode>inv64</mode> </def> </instruction> @@ -1091,42 +1168,42 @@ <def> <pfx>oso</pfx> <opc>48</opc> - <opr>eAX</opr> + <opr>R0z</opr> </def> <def> <pfx>oso</pfx> <opc>49</opc> - <opr>eCX</opr> + <opr>R1z</opr> </def> <def> <pfx>oso</pfx> <opc>4a</opc> - <opr>eDX</opr> + <opr>R2z</opr> </def> <def> <pfx>oso</pfx> <opc>4b</opc> - <opr>eBX</opr> + <opr>R3z</opr> </def> <def> <pfx>oso</pfx> <opc>4c</opc> - <opr>eSP</opr> + <opr>R4z</opr> </def> <def> <pfx>oso</pfx> <opc>4d</opc> - <opr>eBP</opr> + <opr>R5z</opr> </def> <def> <pfx>oso</pfx> <opc>4e</opc> - <opr>eSI</opr> + <opr>R6z</opr> </def> <def> <pfx>oso</pfx> <opc>4f</opc> - <opr>eDI</opr> + <opr>R7z</opr> </def> <def> <pfx>aso rexw rexr rexx rexb</pfx> @@ -1157,9 +1234,10 @@ <instruction> <mnemonic>divpd</mnemonic> <def> - <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 5e</opc> - <opr>V W</opr> + <pfx>aso rexr rexx rexb vexl</pfx> + <opc>/sse=66 0f 5e</opc> + <opr>V H W</opr> + <cpuid>sse2 avx</cpuid> </def> </instruction> @@ -1168,7 +1246,8 @@ <def> <pfx>aso rexr rexx rexb</pfx> <opc>0f 5e</opc> - <opr>V W</opr> + <opr>V H W</opr> + <cpuid>sse avx</cpuid> </def> </instruction> @@ -1176,8 +1255,9 @@ <mnemonic>divsd</mnemonic> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>ssef2 0f 5e</opc> - <opr>V W</opr> + <opc>/sse=f2 0f 5e</opc> + <opr>V H MqU</opr> + <cpuid>sse2 avx</cpuid> </def> </instruction> @@ -1185,8 +1265,29 @@ <mnemonic>divss</mnemonic> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>ssef3 0f 5e</opc> - <opr>V W</opr> + <opc>/sse=f3 0f 5e</opc> + <opr>V H MdU</opr> + <cpuid>sse avx</cpuid> + </def> + </instruction> + + <instruction> + <mnemonic>dppd</mnemonic> + <def> + <pfx>aso rexr rexx rexb</pfx> + <opc>/sse=66 0f 3a 41</opc> + <opr>V H W Ib</opr> + <cpuid>sse4.1 avx</cpuid> + </def> + </instruction> + + <instruction> + <mnemonic>dpps</mnemonic> + <def> + <pfx>aso rexr rexx rexb vexl</pfx> + <opc>/sse=66 0f 3a 40</opc> + <opr>V H W Ib</opr> + <cpuid>sse4.1 avx</cpuid> </def> </instruction> @@ -1202,13 +1303,23 @@ <def> <opc>c8</opc> <opr>Iw Ib</opr> - <mode>def64 depM</mode> + <mode>def64</mode> + </def> + </instruction> + + <instruction> + <mnemonic>extractps</mnemonic> + <def> + <pfx>aso rexr rexw rexx rexb</pfx> + <opc>/sse=66 0f 3a 17</opc> + <opr>MdRy V Ib</opr> + <cpuid>sse4.1 avx</cpuid> </def> </instruction> <instruction> <mnemonic>f2xm1</mnemonic> - <class>X87</class> + <cpuid>X87</cpuid> <def> <opc>d9 /mod=11 /x87=30</opc> </def> @@ -1216,7 +1327,7 @@ <instruction> <mnemonic>fabs</mnemonic> - <class>X87</class> + <cpuid>X87</cpuid> <def> <opc>d9 /mod=11 /x87=21</opc> </def> @@ -1224,7 +1335,7 @@ <instruction> <mnemonic>fadd</mnemonic> - <class>X87</class> + <cpuid>X87</cpuid> <def> <pfx>aso rexr rexx rexb</pfx> <opc>dc /mod=!11 /reg=0</opc> @@ -1303,7 +1414,7 @@ <instruction> <mnemonic>faddp</mnemonic> - <class>X87</class> + <cpuid>X87</cpuid> <def> <opc>de /mod=11 /x87=00</opc> <opr>ST0 ST0</opr> @@ -1340,7 +1451,7 @@ <instruction> <mnemonic>fbld</mnemonic> - <class>X87</class> + <cpuid>X87</cpuid> <def> <pfx>aso rexr rexx rexb</pfx> <opc>df /mod=!11 /reg=4</opc> @@ -1350,7 +1461,7 @@ <instruction> <mnemonic>fbstp</mnemonic> - <class>X87</class> + <cpuid>X87</cpuid> <def> <pfx>aso rexr rexx rexb</pfx> <opc>df /mod=!11 /reg=6</opc> @@ -1360,7 +1471,7 @@ <instruction> <mnemonic>fchs</mnemonic> - <class>X87</class> + <cpuid>X87</cpuid> <def> <opc>d9 /mod=11 /x87=20</opc> </def> @@ -1368,7 +1479,7 @@ <instruction> <mnemonic>fclex</mnemonic> - <class>X87</class> + <cpuid>X87</cpuid> <def> <opc>db /mod=11 /x87=22</opc> </def> @@ -1376,7 +1487,7 @@ <instruction> <mnemonic>fcmovb</mnemonic> - <class>X87</class> + <cpuid>X87</cpuid> <def> <opc>da /mod=11 /x87=00</opc> <opr>ST0 ST0</opr> @@ -1413,7 +1524,7 @@ <instruction> <mnemonic>fcmove</mnemonic> - <class>X87</class> + <cpuid>X87</cpuid> <def> <opc>da /mod=11 /x87=08</opc> <opr>ST0 ST0</opr> @@ -1450,7 +1561,7 @@ <instruction> <mnemonic>fcmovbe</mnemonic> - <class>X87</class> + <cpuid>X87</cpuid> <def> <opc>da /mod=11 /x87=10</opc> <opr>ST0 ST0</opr> @@ -1487,7 +1598,7 @@ <instruction> <mnemonic>fcmovu</mnemonic> - <class>X87</class> + <cpuid>X87</cpuid> <def> <opc>da /mod=11 /x87=18</opc> <opr>ST0 ST0</opr> @@ -1524,7 +1635,7 @@ <instruction> <mnemonic>fcmovnb</mnemonic> - <class>X87</class> + <cpuid>X87</cpuid> <def> <opc>db /mod=11 /x87=00</opc> <opr>ST0 ST0</opr> @@ -1561,7 +1672,7 @@ <instruction> <mnemonic>fcmovne</mnemonic> - <class>X87</class> + <cpuid>X87</cpuid> <def> <opc>db /mod=11 /x87=08</opc> <opr>ST0 ST0</opr> @@ -1598,7 +1709,7 @@ <instruction> <mnemonic>fcmovnbe</mnemonic> - <class>X87</class> + <cpuid>X87</cpuid> <def> <opc>db /mod=11 /x87=10</opc> <opr>ST0 ST0</opr> @@ -1635,7 +1746,7 @@ <instruction> <mnemonic>fcmovnu</mnemonic> - <class>X87</class> + <cpuid>X87</cpuid> <def> <opc>db /mod=11 /x87=18</opc> <opr>ST0 ST0</opr> @@ -1672,7 +1783,7 @@ <instruction> <mnemonic>fucomi</mnemonic> - <class>X87</class> + <cpuid>X87</cpuid> <def> <opc>db /mod=11 /x87=28</opc> <opr>ST0 ST0</opr> @@ -1709,7 +1820,7 @@ <instruction> <mnemonic>fcom</mnemonic> - <class>X87</class> + <cpuid>X87</cpuid> <def> <pfx>aso rexr rexx rexb</pfx> <opc>d8 /mod=!11 /reg=2</opc> @@ -1756,7 +1867,7 @@ <instruction> <mnemonic>fcom2</mnemonic> - <class>X87 UNDOC</class> + <cpuid>X87 UNDOC</cpuid> <def> <opc>dc /mod=11 /x87=10</opc> <opr>ST0</opr> @@ -1793,7 +1904,7 @@ <instruction> <mnemonic>fcomp3</mnemonic> - <class>X87 UNDOC</class> + <cpuid>X87 UNDOC</cpuid> <def> <opc>dc /mod=11 /x87=18</opc> <opr>ST0</opr> @@ -1830,7 +1941,7 @@ <instruction> <mnemonic>fcomi</mnemonic> - <class>X87</class> + <cpuid>X87</cpuid> <def> <opc>db /mod=11 /x87=30</opc> <opr>ST0 ST0</opr> @@ -1867,7 +1978,7 @@ <instruction> <mnemonic>fucomip</mnemonic> - <class>X87</class> + <cpuid>X87</cpuid> <def> <opc>df /mod=11 /x87=28</opc> <opr>ST0 ST0</opr> @@ -1904,7 +2015,7 @@ <instruction> <mnemonic>fcomip</mnemonic> - <class>X87</class> + <cpuid>X87</cpuid> <def> <opc>df /mod=11 /x87=30</opc> <opr>ST0 ST0</opr> @@ -1941,7 +2052,7 @@ <instruction> <mnemonic>fcomp</mnemonic> - <class>X87</class> + <cpuid>X87</cpuid> <def> <pfx>aso rexr rexx rexb</pfx> <opc>d8 /mod=!11 /reg=3</opc> @@ -1988,7 +2099,7 @@ <instruction> <mnemonic>fcomp5</mnemonic> - <class>X87 UNDOC</class> + <cpuid>X87 UNDOC</cpuid> <def> <opc>de /mod=11 /x87=10</opc> <opr>ST0</opr> @@ -2025,7 +2136,7 @@ <instruction> <mnemonic>fcompp</mnemonic> - <class>X87</class> + <cpuid>X87</cpuid> <def> <opc>de /mod=11 /x87=19</opc> </def> @@ -2033,7 +2144,7 @@ <instruction> <mnemonic>fcos</mnemonic> - <class>X87</class> + <cpuid>X87</cpuid> <def> <opc>d9 /mod=11 /x87=3f</opc> </def> @@ -2041,7 +2152,7 @@ <instruction> <mnemonic>fdecstp</mnemonic> - <class>X87</class> + <cpuid>X87</cpuid> <def> <opc>d9 /mod=11 /x87=36</opc> </def> @@ -2049,7 +2160,7 @@ <instruction> <mnemonic>fdiv</mnemonic> - <class>X87</class> + <cpuid>X87</cpuid> <def> <pfx>aso rexr rexx rexb</pfx> <opc>dc /mod=!11 /reg=6</opc> @@ -2128,7 +2239,7 @@ <instruction> <mnemonic>fdivp</mnemonic> - <class>X87</class> + <cpuid>X87</cpuid> <def> <opc>de /mod=11 /x87=38</opc> <opr>ST0 ST0</opr> @@ -2165,7 +2276,7 @@ <instruction> <mnemonic>fdivr</mnemonic> - <class>X87</class> + <cpuid>X87</cpuid> <def> <pfx>aso rexr rexx rexb</pfx> <opc>dc /mod=!11 /reg=7</opc> @@ -2244,7 +2355,7 @@ <instruction> <mnemonic>fdivrp</mnemonic> - <class>X87</class> + <cpuid>X87</cpuid> <def> <opc>de /mod=11 /x87=30</opc> <opr>ST0 ST0</opr> @@ -2288,7 +2399,7 @@ <instruction> <mnemonic>ffree</mnemonic> - <class>X87</class> + <cpuid>X87</cpuid> <def> <opc>dd /mod=11 /x87=00</opc> <opr>ST0</opr> @@ -2325,7 +2436,7 @@ <instruction> <mnemonic>ffreep</mnemonic> - <class>X87</class> + <cpuid>X87</cpuid> <def> <opc>df /mod=11 /x87=00</opc> <opr>ST0</opr> @@ -2362,7 +2473,7 @@ <instruction> <mnemonic>ficom</mnemonic> - <class>X87</class> + <cpuid>X87</cpuid> <def> <pfx>aso rexr rexx rexb</pfx> <opc>de /mod=!11 /reg=2</opc> @@ -2377,7 +2488,7 @@ <instruction> <mnemonic>ficomp</mnemonic> - <class>X87</class> + <cpuid>X87</cpuid> <def> <pfx>aso rexr rexx rexb</pfx> <opc>de /mod=!11 /reg=3</opc> @@ -2392,7 +2503,7 @@ <instruction> <mnemonic>fild</mnemonic> - <class>X87</class> + <cpuid>X87</cpuid> <def> <pfx>aso rexr rexx rexb</pfx> <opc>df /mod=!11 /reg=0</opc> @@ -2411,8 +2522,8 @@ </instruction> <instruction> - <mnemonic>fncstp</mnemonic> - <class>X87</class> + <mnemonic>fincstp</mnemonic> + <cpuid>X87</cpuid> <def> <opc>d9 /mod=11 /x87=37</opc> </def> @@ -2420,7 +2531,7 @@ <instruction> <mnemonic>fninit</mnemonic> - <class>X87</class> + <cpuid>X87</cpuid> <def> <opc>db /mod=11 /x87=23</opc> </def> @@ -2428,7 +2539,7 @@ <instruction> <mnemonic>fiadd</mnemonic> - <class>X87</class> + <cpuid>X87</cpuid> <def> <pfx>aso rexr rexx rexb</pfx> <opc>da /mod=!11 /reg=0</opc> @@ -2443,7 +2554,7 @@ <instruction> <mnemonic>fidivr</mnemonic> - <class>X87</class> + <cpuid>X87</cpuid> <def> <pfx>aso rexr rexx rexb</pfx> <opc>da /mod=!11 /reg=7</opc> @@ -2458,7 +2569,7 @@ <instruction> <mnemonic>fidiv</mnemonic> - <class>X87</class> + <cpuid>X87</cpuid> <def> <pfx>aso rexr rexx rexb</pfx> <opc>da /mod=!11 /reg=6</opc> @@ -2473,7 +2584,7 @@ <instruction> <mnemonic>fisub</mnemonic> - <class>X87</class> + <cpuid>X87</cpuid> <def> <pfx>aso rexr rexx rexb</pfx> <opc>da /mod=!11 /reg=4</opc> @@ -2488,7 +2599,7 @@ <instruction> <mnemonic>fisubr</mnemonic> - <class>X87</class> + <cpuid>X87</cpuid> <def> <pfx>aso rexr rexx rexb</pfx> <opc>da /mod=!11 /reg=5</opc> @@ -2503,7 +2614,7 @@ <instruction> <mnemonic>fist</mnemonic> - <class>X87</class> + <cpuid>X87</cpuid> <def> <pfx>aso rexr rexx rexb</pfx> <opc>df /mod=!11 /reg=2</opc> @@ -2518,7 +2629,7 @@ <instruction> <mnemonic>fistp</mnemonic> - <class>X87</class> + <cpuid>X87</cpuid> <def> <pfx>aso rexr rexx rexb</pfx> <opc>df /mod=!11 /reg=3</opc> @@ -2538,7 +2649,7 @@ <instruction> <mnemonic>fisttp</mnemonic> - <class>X87</class> + <cpuid>X87</cpuid> <def> <pfx>aso rexr rexx rexb</pfx> <opc>db /mod=!11 /reg=1</opc> @@ -2558,7 +2669,7 @@ <instruction> <mnemonic>fld</mnemonic> - <class>X87</class> + <cpuid>X87</cpuid> <def> <pfx>aso rexr rexx rexb</pfx> <opc>db /mod=!11 /reg=5</opc> @@ -2610,7 +2721,7 @@ <instruction> <mnemonic>fld1</mnemonic> - <class>X87</class> + <cpuid>X87</cpuid> <def> <opc>d9 /mod=11 /x87=28</opc> </def> @@ -2618,7 +2729,7 @@ <instruction> <mnemonic>fldl2t</mnemonic> - <class>X87</class> + <cpuid>X87</cpuid> <def> <opc>d9 /mod=11 /x87=29</opc> </def> @@ -2626,15 +2737,15 @@ <instruction> <mnemonic>fldl2e</mnemonic> - <class>X87</class> + <cpuid>X87</cpuid> <def> <opc>d9 /mod=11 /x87=2a</opc> </def> </instruction> <instruction> - <mnemonic>fldlpi</mnemonic> - <class>X87</class> + <mnemonic>fldpi</mnemonic> + <cpuid>X87</cpuid> <def> <opc>d9 /mod=11 /x87=2b</opc> </def> @@ -2642,7 +2753,7 @@ <instruction> <mnemonic>fldlg2</mnemonic> - <class>X87</class> + <cpuid>X87</cpuid> <def> <opc>d9 /mod=11 /x87=2c</opc> </def> @@ -2650,7 +2761,7 @@ <instruction> <mnemonic>fldln2</mnemonic> - <class>X87</class> + <cpuid>X87</cpuid> <def> <opc>d9 /mod=11 /x87=2d</opc> </def> @@ -2658,7 +2769,7 @@ <instruction> <mnemonic>fldz</mnemonic> - <class>X87</class> + <cpuid>X87</cpuid> <def> <opc>d9 /mod=11 /x87=2e</opc> </def> @@ -2666,7 +2777,7 @@ <instruction> <mnemonic>fldcw</mnemonic> - <class>X87</class> + <cpuid>X87</cpuid> <def> <pfx>aso rexr rexx rexb</pfx> <opc>d9 /mod=!11 /reg=5</opc> @@ -2676,7 +2787,7 @@ <instruction> <mnemonic>fldenv</mnemonic> - <class>X87</class> + <cpuid>X87</cpuid> <def> <pfx>aso rexr rexx rexb</pfx> <opc>d9 /mod=!11 /reg=4</opc> @@ -2686,7 +2797,7 @@ <instruction> <mnemonic>fmul</mnemonic> - <class>X87</class> + <cpuid>X87</cpuid> <def> <pfx>aso rexr rexx rexb</pfx> <opc>dc /mod=!11 /reg=1</opc> @@ -2765,7 +2876,7 @@ <instruction> <mnemonic>fmulp</mnemonic> - <class>X87</class> + <cpuid>X87</cpuid> <def> <opc>de /mod=11 /x87=08</opc> <opr>ST0 ST0</opr> @@ -2802,7 +2913,7 @@ <instruction> <mnemonic>fimul</mnemonic> - <class>X87</class> + <cpuid>X87</cpuid> <def> <pfx>aso rexr rexx rexb</pfx> <opc>da /mod=!11 /reg=1</opc> @@ -2817,15 +2928,39 @@ <instruction> <mnemonic>fnop</mnemonic> - <class>X87</class> + <cpuid>X87</cpuid> <def> <opc>d9 /mod=11 /x87=10</opc> </def> </instruction> + + <instruction> + <mnemonic>fndisi</mnemonic> + <cpuid>X87</cpuid> + <def> + <opc>db /mod=11 /x87=21</opc> + </def> + </instruction> + + <instruction> + <mnemonic>fneni</mnemonic> + <cpuid>X87</cpuid> + <def> + <opc>db /mod=11 /x87=20</opc> + </def> + </instruction> + + <instruction> + <mnemonic>fnsetpm</mnemonic> + <cpuid>X87</cpuid> + <def> + <opc>db /mod=11 /x87=24</opc> + </def> + </instruction> <instruction> <mnemonic>fpatan</mnemonic> - <class>X87</class> + <cpuid>X87</cpuid> <def> <opc>d9 /mod=11 /x87=33</opc> </def> @@ -2833,7 +2968,7 @@ <instruction> <mnemonic>fprem</mnemonic> - <class>X87</class> + <cpuid>X87</cpuid> <def> <opc>d9 /mod=11 /x87=38</opc> </def> @@ -2841,7 +2976,7 @@ <instruction> <mnemonic>fprem1</mnemonic> - <class>X87</class> + <cpuid>X87</cpuid> <def> <opc>d9 /mod=11 /x87=35</opc> </def> @@ -2849,7 +2984,7 @@ <instruction> <mnemonic>fptan</mnemonic> - <class>X87</class> + <cpuid>X87</cpuid> <def> <opc>d9 /mod=11 /x87=32</opc> </def> @@ -2857,7 +2992,7 @@ <instruction> <mnemonic>frndint</mnemonic> - <class>X87</class> + <cpuid>X87</cpuid> <def> <opc>d9 /mod=11 /x87=3c</opc> </def> @@ -2865,17 +3000,25 @@ <instruction> <mnemonic>frstor</mnemonic> - <class>X87</class> + <cpuid>X87</cpuid> <def> <pfx>aso rexr rexx rexb</pfx> <opc>dd /mod=!11 /reg=4</opc> <opr>M</opr> </def> </instruction> + + <instruction> + <mnemonic>frstpm</mnemonic> + <cpuid>X87</cpuid> + <def> + <opc>db /mod=11 /x87=25</opc> + </def> + </instruction> <instruction> <mnemonic>fnsave</mnemonic> - <class>X87</class> + <cpuid>X87</cpuid> <def> <pfx>aso rexr rexx rexb</pfx> <opc>dd /mod=!11 /reg=6</opc> @@ -2885,7 +3028,7 @@ <instruction> <mnemonic>fscale</mnemonic> - <class>X87</class> + <cpuid>X87</cpuid> <def> <opc>d9 /mod=11 /x87=3d</opc> </def> @@ -2893,7 +3036,7 @@ <instruction> <mnemonic>fsin</mnemonic> - <class>X87</class> + <cpuid>X87</cpuid> <def> <opc>d9 /mod=11 /x87=3e</opc> </def> @@ -2901,7 +3044,7 @@ <instruction> <mnemonic>fsincos</mnemonic> - <class>X87</class> + <cpuid>X87</cpuid> <def> <opc>d9 /mod=11 /x87=3b</opc> </def> @@ -2909,7 +3052,7 @@ <instruction> <mnemonic>fsqrt</mnemonic> - <class>X87</class> + <cpuid>X87</cpuid> <def> <opc>d9 /mod=11 /x87=3a</opc> </def> @@ -2917,7 +3060,7 @@ <instruction> <mnemonic>fstp</mnemonic> - <class>X87</class> + <cpuid>X87</cpuid> <def> <pfx>aso rexr rexx rexb</pfx> <opc>db /mod=!11 /reg=7</opc> @@ -3077,7 +3220,7 @@ <instruction> <mnemonic>fst</mnemonic> - <class>X87</class> + <cpuid>X87</cpuid> <def> <pfx>aso rexr rexx rexb</pfx> <opc>d9 /mod=!11 /reg=2</opc> @@ -3124,7 +3267,7 @@ <instruction> <mnemonic>fnstcw</mnemonic> - <class>X87</class> + <cpuid>X87</cpuid> <def> <pfx>aso rexr rexx rexb</pfx> <opc>d9 /mod=!11 /reg=7</opc> @@ -3134,7 +3277,7 @@ <instruction> <mnemonic>fnstenv</mnemonic> - <class>X87</class> + <cpuid>X87</cpuid> <def> <pfx>aso rexr rexx rexb</pfx> <opc>d9 /mod=!11 /reg=6</opc> @@ -3144,7 +3287,7 @@ <instruction> <mnemonic>fnstsw</mnemonic> - <class>X87</class> + <cpuid>X87</cpuid> <def> <pfx>aso rexr rexx rexb</pfx> <opc>dd /mod=!11 /reg=7</opc> @@ -3158,7 +3301,7 @@ <instruction> <mnemonic>fsub</mnemonic> - <class>X87</class> + <cpuid>X87</cpuid> <def> <pfx>aso rexr rexx rexb</pfx> <opc>d8 /mod=!11 /reg=4</opc> @@ -3237,7 +3380,7 @@ <instruction> <mnemonic>fsubp</mnemonic> - <class>X87</class> + <cpuid>X87</cpuid> <def> <opc>de /mod=11 /x87=28</opc> <opr>ST0 ST0</opr> @@ -3274,7 +3417,7 @@ <instruction> <mnemonic>fsubr</mnemonic> - <class>X87</class> + <cpuid>X87</cpuid> <def> <pfx>aso rexr rexx rexb</pfx> <opc>dc /mod=!11 /reg=5</opc> @@ -3353,7 +3496,7 @@ <instruction> <mnemonic>fsubrp</mnemonic> - <class>X87</class> + <cpuid>X87</cpuid> <def> <opc>de /mod=11 /x87=20</opc> <opr>ST0 ST0</opr> @@ -3390,7 +3533,7 @@ <instruction> <mnemonic>ftst</mnemonic> - <class>X87</class> + <cpuid>X87</cpuid> <def> <opc>d9 /mod=11 /x87=24</opc> </def> @@ -3398,7 +3541,7 @@ <instruction> <mnemonic>fucom</mnemonic> - <class>X87</class> + <cpuid>X87</cpuid> <def> <opc>dd /mod=11 /x87=20</opc> <opr>ST0</opr> @@ -3435,7 +3578,7 @@ <instruction> <mnemonic>fucomp</mnemonic> - <class>X87</class> + <cpuid>X87</cpuid> <def> <opc>dd /mod=11 /x87=28</opc> <opr>ST0</opr> @@ -3472,7 +3615,7 @@ <instruction> <mnemonic>fucompp</mnemonic> - <class>X87</class> + <cpuid>X87</cpuid> <def> <opc>da /mod=11 /x87=29</opc> </def> @@ -3480,7 +3623,7 @@ <instruction> <mnemonic>fxam</mnemonic> - <class>X87</class> + <cpuid>X87</cpuid> <def> <opc>d9 /mod=11 /x87=25</opc> </def> @@ -3488,7 +3631,7 @@ <instruction> <mnemonic>fxch</mnemonic> - <class>X87</class> + <cpuid>X87</cpuid> <def> <opc>d9 /mod=11 /x87=08</opc> <opr>ST0 ST0</opr> @@ -3525,7 +3668,7 @@ <instruction> <mnemonic>fxch4</mnemonic> - <class>X87</class> + <cpuid>X87</cpuid> <def> <opc>dd /mod=11 /x87=08</opc> <opr>ST0</opr> @@ -3562,7 +3705,7 @@ <instruction> <mnemonic>fxch7</mnemonic> - <class>X87</class> + <cpuid>X87</cpuid> <def> <opc>df /mod=11 /x87=08</opc> <opr>ST0</opr> @@ -3601,7 +3744,7 @@ <mnemonic>fxrstor</mnemonic> <def> <pfx>aso rexw rexr rexx rexb</pfx> - <opc>0f ae /mod=11 /reg=1</opc> + <opc>0f ae /mod=!11 /reg=1</opc> <opr>M</opr> </def> </instruction> @@ -3610,14 +3753,14 @@ <mnemonic>fxsave</mnemonic> <def> <pfx>aso rexw rexr rexx rexb</pfx> - <opc>0f ae /mod=11 /reg=0</opc> + <opc>0f ae /mod=!11 /reg=0</opc> <opr>M</opr> </def> </instruction> <instruction> - <mnemonic>fpxtract</mnemonic> - <class>X87</class> + <mnemonic>fxtract</mnemonic> + <cpuid>X87</cpuid> <def> <opc>d9 /mod=11 /x87=34</opc> </def> @@ -3625,7 +3768,7 @@ <instruction> <mnemonic>fyl2x</mnemonic> - <class>X87</class> + <cpuid>X87</cpuid> <def> <opc>d9 /mod=11 /x87=31</opc> </def> @@ -3633,7 +3776,7 @@ <instruction> <mnemonic>fyl2xp1</mnemonic> - <class>X87</class> + <cpuid>X87</cpuid> <def> <opc>d9 /mod=11 /x87=39</opc> </def> @@ -3703,13 +3846,11 @@ <pfx>aso oso rexw rexr rexx rexb</pfx> <opc>69</opc> <opr>Gv Ev Iz</opr> - <syn>sext</syn> </def> <def> <pfx>aso oso rexw rexr rexx rexb</pfx> <opc>6b</opc> - <opr>Gv Ev Ib</opr> - <syn>sext</syn> + <opr>Gv Ev sIb</opr> </def> </instruction> @@ -3718,42 +3859,42 @@ <def> <pfx>oso</pfx> <opc>40</opc> - <opr>eAX</opr> + <opr>R0z</opr> </def> <def> <pfx>oso</pfx> <opc>41</opc> - <opr>eCX</opr> + <opr>R1z</opr> </def> <def> <pfx>oso</pfx> <opc>42</opc> - <opr>eDX</opr> + <opr>R2z</opr> </def> <def> <pfx>oso</pfx> <opc>43</opc> - <opr>eBX</opr> + <opr>R3z</opr> </def> <def> <pfx>oso</pfx> <opc>44</opc> - <opr>eSP</opr> + <opr>R4z</opr> </def> <def> <pfx>oso</pfx> <opc>45</opc> - <opr>eBP</opr> + <opr>R5z</opr> </def> <def> <pfx>oso</pfx> <opc>46</opc> - <opr>eSI</opr> + <opr>R6z</opr> </def> <def> <pfx>oso</pfx> <opc>47</opc> - <opr>eDI</opr> + <opr>R7z</opr> </def> <def> <pfx>aso oso rexw rexr rexx rexb</pfx> @@ -3770,6 +3911,7 @@ <instruction> <mnemonic>insb</mnemonic> <def> + <pfx>rep seg</pfx> <opc>6c</opc> </def> </instruction> @@ -3777,7 +3919,7 @@ <instruction> <mnemonic>insw</mnemonic> <def> - <pfx>oso</pfx> + <pfx>rep oso seg</pfx> <opc>6d /o=16</opc> </def> </instruction> @@ -3785,7 +3927,7 @@ <instruction> <mnemonic>insd</mnemonic> <def> - <pfx>oso</pfx> + <pfx>rep oso seg</pfx> <opc>6d /o=32</opc> </def> </instruction> @@ -3815,7 +3957,7 @@ <instruction> <mnemonic>into</mnemonic> <def> - <opc>ce</opc> + <opc>ce /m=!64</opc> <mode>inv64</mode> </def> </instruction> @@ -3831,11 +3973,11 @@ <mnemonic>invept</mnemonic> <vendor>intel</vendor> <def> - <opc>sse66 0f 38 80 /m=32</opc> + <opc>/sse=66 0f 38 80 /m=32</opc> <opr>Gd Mo</opr> </def> <def> - <opc>sse66 0f 38 80 /m=64</opc> + <opc>/sse=66 0f 38 80 /m=64</opc> <opr>Gq Mo</opr> </def> </instruction> @@ -3861,11 +4003,11 @@ <mnemonic>invvpid</mnemonic> <vendor>intel</vendor> <def> - <opc>sse66 0f 38 81 /m=32</opc> + <opc>/sse=66 0f 38 81 /m=32</opc> <opr>Gd Mo</opr> </def> <def> - <opc>sse66 0f 38 81 /m=64</opc> + <opc>/sse=66 0f 38 81 /m=64</opc> <opr>Gq Mo</opr> </def> </instruction> @@ -3904,7 +4046,7 @@ <pfx>oso</pfx> <opc>0f 80</opc> <opr>Jz</opr> - <mode>def64 depM</mode> + <mode>def64</mode> </def> </instruction> @@ -3918,7 +4060,7 @@ <pfx>oso</pfx> <opc>0f 81</opc> <opr>Jz</opr> - <mode>def64 depM</mode> + <mode>def64</mode> </def> </instruction> @@ -3932,7 +4074,7 @@ <pfx>oso</pfx> <opc>0f 82</opc> <opr>Jz</opr> - <mode>def64 depM</mode> + <mode>def64</mode> </def> </instruction> @@ -3946,7 +4088,7 @@ <pfx>oso</pfx> <opc>0f 83</opc> <opr>Jz</opr> - <mode>def64 depM</mode> + <mode>def64</mode> </def> </instruction> @@ -3960,7 +4102,7 @@ <pfx>oso</pfx> <opc>0f 84</opc> <opr>Jz</opr> - <mode>def64 depM</mode> + <mode>def64</mode> </def> </instruction> @@ -3974,7 +4116,7 @@ <pfx>oso</pfx> <opc>0f 85</opc> <opr>Jz</opr> - <mode>def64 depM</mode> + <mode>def64</mode> </def> </instruction> @@ -3988,7 +4130,7 @@ <pfx>oso</pfx> <opc>0f 86</opc> <opr>Jz</opr> - <mode>def64 depM</mode> + <mode>def64</mode> </def> </instruction> @@ -4002,7 +4144,7 @@ <pfx>oso</pfx> <opc>0f 87</opc> <opr>Jz</opr> - <mode>def64 depM</mode> + <mode>def64</mode> </def> </instruction> @@ -4016,7 +4158,7 @@ <pfx>oso</pfx> <opc>0f 88</opc> <opr>Jz</opr> - <mode>def64 depM</mode> + <mode>def64</mode> </def> </instruction> @@ -4030,7 +4172,7 @@ <pfx>oso</pfx> <opc>0f 89</opc> <opr>Jz</opr> - <mode>def64 depM</mode> + <mode>def64</mode> </def> </instruction> @@ -4044,7 +4186,7 @@ <pfx>oso</pfx> <opc>0f 8a</opc> <opr>Jz</opr> - <mode>def64 depM</mode> + <mode>def64</mode> </def> </instruction> @@ -4058,7 +4200,7 @@ <pfx>oso</pfx> <opc>0f 8b</opc> <opr>Jz</opr> - <mode>def64 depM</mode> + <mode>def64</mode> </def> </instruction> @@ -4072,7 +4214,7 @@ <pfx>oso</pfx> <opc>0f 8c</opc> <opr>Jz</opr> - <mode>def64 depM</mode> + <mode>def64</mode> </def> </instruction> @@ -4086,7 +4228,7 @@ <pfx>oso</pfx> <opc>0f 8d</opc> <opr>Jz</opr> - <mode>def64 depM</mode> + <mode>def64</mode> </def> </instruction> @@ -4100,7 +4242,7 @@ <pfx>oso</pfx> <opc>0f 8e</opc> <opr>Jz</opr> - <mode>def64 depM</mode> + <mode>def64</mode> </def> </instruction> @@ -4114,7 +4256,7 @@ <pfx>oso</pfx> <opc>0f 8f</opc> <opr>Jz</opr> - <mode>def64 depM</mode> + <mode>def64</mode> </def> </instruction> @@ -4151,28 +4293,28 @@ <pfx>aso oso rexw rexr rexx rexb</pfx> <opc>ff /reg=4</opc> <opr>Ev</opr> - <mode>def64 depM</mode> + <mode>def64</mode> </def> <def> <pfx>aso oso rexw rexr rexx rexb</pfx> <opc>ff /reg=5</opc> - <opr>Ep</opr> + <opr>Fv</opr> </def> <def> <pfx>oso</pfx> <opc>e9</opc> <opr>Jz</opr> - <mode>def64 depM</mode> - <syn>cast</syn> + <mode>def64</mode> </def> <def> - <opc>ea</opc> - <opr>Ap</opr> - <mode>inv64</mode> + <pfx>oso</pfx> + <opc>ea /m=!64</opc> + <opr>Av</opr> </def> <def> <opc>eb</opc> <opr>Jb</opr> + <mode>def64</mode> </def> </instruction> @@ -4193,19 +4335,10 @@ </instruction> <instruction> - <mnemonic>lddqu</mnemonic> - <def> - <pfx>aso rexr rexx rexb</pfx> - <opc>ssef2 0f f0</opc> - <opr>V M</opr> - </def> - </instruction> - - <instruction> <mnemonic>ldmxcsr</mnemonic> <def> <pfx>aso rexw rexr rexx rexb</pfx> - <opc>0f ae /reg=2 /mod=11</opc> + <opc>0f ae /reg=2 /mod=!11</opc> <opr>Md</opr> </def> </instruction> @@ -4214,9 +4347,8 @@ <mnemonic>lds</mnemonic> <def> <pfx>aso oso</pfx> - <opc>c5</opc> + <opc>c5 /vex=none /m=!64</opc> <opr>Gv M</opr> - <mode>inv64</mode> </def> </instruction> @@ -4233,9 +4365,8 @@ <mnemonic>les</mnemonic> <def> <pfx>aso oso</pfx> - <opc>c4</opc> + <opc>c4 /m=!64</opc> <opr>Gv M</opr> - <mode>inv64</mode> </def> </instruction> @@ -4271,7 +4402,7 @@ <def> <pfx>aso oso rexw rexr rexx rexb</pfx> <opc>0f b2</opc> - <opr>Gz M</opr> + <opr>Gv M</opr> </def> </instruction> @@ -4335,6 +4466,11 @@ <opc>0f 01 /reg=6 /mod=!11</opc> <opr>Ew</opr> </def> + <def> + <pfx>aso rexr rexx rexb</pfx> + <opc>0f 01 /reg=6 /mod=11</opc> + <opr>Ew</opr> + </def> </instruction> <instruction> @@ -4347,7 +4483,7 @@ <instruction> <mnemonic>lodsb</mnemonic> <def> - <pfx>seg</pfx> + <pfx>rep seg</pfx> <opc>ac</opc> </def> </instruction> @@ -4355,7 +4491,7 @@ <instruction> <mnemonic>lodsw</mnemonic> <def> - <pfx>seg oso rexw</pfx> + <pfx>rep seg oso rexw</pfx> <opc>ad /o=16</opc> </def> </instruction> @@ -4363,7 +4499,7 @@ <instruction> <mnemonic>lodsd</mnemonic> <def> - <pfx>seg oso rexw</pfx> + <pfx>rep seg oso rexw</pfx> <opc>ad /o=32</opc> </def> </instruction> @@ -4371,13 +4507,13 @@ <instruction> <mnemonic>lodsq</mnemonic> <def> - <pfx>seg oso rexw</pfx> + <pfx>rep seg oso rexw</pfx> <opc>ad /o=64</opc> </def> </instruction> <instruction> - <mnemonic>loopnz</mnemonic> + <mnemonic>loopne</mnemonic> <def> <opc>e0</opc> <opr>Jb</opr> @@ -4422,26 +4558,28 @@ <mnemonic>maskmovq</mnemonic> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>0f f7</opc> - <opr>P PR</opr> + <opc>0f f7 /mod=11</opc> + <opr>P N</opr> </def> </instruction> <instruction> <mnemonic>maxpd</mnemonic> <def> - <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 5f</opc> - <opr>V W</opr> + <pfx>aso rexr rexx rexb vexl</pfx> + <opc>/sse=66 0f 5f</opc> + <opr>V H W</opr> + <cpuid>sse2 avx</cpuid> </def> </instruction> <instruction> <mnemonic>maxps</mnemonic> <def> - <pfx>aso rexr rexx rexb</pfx> + <pfx>aso rexr rexx rexb vexl</pfx> <opc>0f 5f</opc> - <opr>V W</opr> + <opr>V H W</opr> + <cpuid>sse avx</cpuid> </def> </instruction> @@ -4449,8 +4587,9 @@ <mnemonic>maxsd</mnemonic> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>ssef2 0f 5f</opc> - <opr>V W</opr> + <opc>/sse=f2 0f 5f</opc> + <opr>V H W</opr> + <cpuid>sse2 avx</cpuid> </def> </instruction> @@ -4458,8 +4597,9 @@ <mnemonic>maxss</mnemonic> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>ssef3 0f 5f</opc> - <opr>V W</opr> + <opc>/sse=f3 0f 5f</opc> + <opr>V H W</opr> + <cpuid>sse avx</cpuid> </def> </instruction> @@ -4494,9 +4634,10 @@ <instruction> <mnemonic>minpd</mnemonic> <def> - <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 5d</opc> - <opr>V W</opr> + <pfx>aso rexr rexx rexb vexl</pfx> + <opc>/sse=66 0f 5d</opc> + <opr>V H W</opr> + <cpuid>sse2 avx</cpuid> </def> </instruction> @@ -4505,7 +4646,8 @@ <def> <pfx>aso rexr rexx rexb</pfx> <opc>0f 5d</opc> - <opr>V W</opr> + <opr>V H W</opr> + <cpuid>sse2 avx</cpuid> </def> </instruction> @@ -4513,8 +4655,9 @@ <mnemonic>minsd</mnemonic> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>ssef2 0f 5d</opc> - <opr>V W</opr> + <opc>/sse=f2 0f 5d</opc> + <opr>V H MqU</opr> + <cpuid>sse2 avx</cpuid> </def> </instruction> @@ -4522,8 +4665,9 @@ <mnemonic>minss</mnemonic> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>ssef3 0f 5d</opc> - <opr>V W</opr> + <opc>/sse=f3 0f 5d</opc> + <opr>V H MdU</opr> + <cpuid>sse avx</cpuid> </def> </instruction> @@ -4551,7 +4695,7 @@ <def> <pfx>aso oso rexw rexr rexx rexb</pfx> <opc>c7 /reg=0</opc> - <opr>Ev Iz</opr> + <opr>Ev sIz</opr> </def> <def> <pfx>aso rexr rexx rexb</pfx> @@ -4574,14 +4718,14 @@ <opr>Gv Ev</opr> </def> <def> - <pfx>aso oso rexr rexx rexb</pfx> + <pfx>aso oso rexw rexr rexx rexb</pfx> <opc>8c</opc> - <opr>Ev S</opr> + <opr>MwRv S</opr> </def> <def> - <pfx>aso oso rexr rexx rexb</pfx> + <pfx>aso oso rexw rexr rexx rexb</pfx> <opc>8e</opc> - <opr>S Ev</opr> + <opr>S MwRv</opr> </def> <def> <opc>a0</opc> @@ -4604,100 +4748,100 @@ <def> <pfx>rexb</pfx> <opc>b0</opc> - <opr>ALr8b Ib</opr> + <opr>R0b Ib</opr> </def> <def> <pfx>rexb</pfx> <opc>b1</opc> - <opr>CLr9b Ib</opr> + <opr>R1b Ib</opr> </def> <def> <pfx>rexb</pfx> <opc>b2</opc> - <opr>DLr10b Ib</opr> + <opr>R2b Ib</opr> </def> <def> <pfx>rexb</pfx> <opc>b3</opc> - <opr>BLr11b Ib</opr> + <opr>R3b Ib</opr> </def> <def> <pfx>rexb</pfx> <opc>b4</opc> - <opr>AHr12b Ib</opr> + <opr>R4b Ib</opr> </def> <def> <pfx>rexb</pfx> <opc>b5</opc> - <opr>CHr13b Ib</opr> + <opr>R5b Ib</opr> </def> <def> <pfx>rexb</pfx> <opc>b6</opc> - <opr>DHr14b Ib</opr> + <opr>R6b Ib</opr> </def> <def> <pfx>rexb</pfx> <opc>b7</opc> - <opr>BHr15b Ib</opr> + <opr>R7b Ib</opr> </def> <def> <pfx>oso rexw rexb</pfx> <opc>b8</opc> - <opr>rAXr8 Iv</opr> + <opr>R0v Iv</opr> </def> <def> <pfx>oso rexw rexb</pfx> <opc>b9</opc> - <opr>rCXr9 Iv</opr> + <opr>R1v Iv</opr> </def> <def> <pfx>oso rexw rexb</pfx> <opc>ba</opc> - <opr>rDXr10 Iv</opr> + <opr>R2v Iv</opr> </def> <def> <pfx>oso rexw rexb</pfx> <opc>bb</opc> - <opr>rBXr11 Iv</opr> + <opr>R3v Iv</opr> </def> <def> <pfx>oso rexw rexb</pfx> <opc>bc</opc> - <opr>rSPr12 Iv</opr> + <opr>R4v Iv</opr> </def> <def> <pfx>oso rexw rexb</pfx> <opc>bd</opc> - <opr>rBPr13 Iv</opr> + <opr>R5v Iv</opr> </def> <def> <pfx>oso rexw rexb</pfx> <opc>be</opc> - <opr>rSIr14 Iv</opr> + <opr>R6v Iv</opr> </def> <def> <pfx>oso rexw rexb</pfx> <opc>bf</opc> - <opr>rDIr15 Iv</opr> + <opr>R7v Iv</opr> </def> <def> - <pfx>rexr</pfx> + <pfx>rexr rexw rexb</pfx> <opc>0f 20</opc> <opr>R C</opr> </def> <def> - <pfx>rexr</pfx> + <pfx>rexr rexw rexb</pfx> <opc>0f 21</opc> <opr>R D</opr> </def> <def> - <pfx>rexr</pfx> + <pfx>rexr rexw rexb</pfx> <opc>0f 22</opc> <opr>C R</opr> </def> <def> - <pfx>rexr</pfx> + <pfx>rexr rexw rexb</pfx> <opc>0f 23</opc> <opr>D R</opr> </def> @@ -4706,28 +4850,32 @@ <instruction> <mnemonic>movapd</mnemonic> <def> - <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 28</opc> + <pfx>aso rexr rexx rexb vexl</pfx> + <opc>/sse=66 0f 28</opc> <opr>V W</opr> + <cpuid>sse2 avx</cpuid> </def> <def> - <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 29</opc> + <pfx>aso rexr rexx rexb vexl</pfx> + <opc>/sse=66 0f 29</opc> <opr>W V</opr> + <cpuid>sse2 avx</cpuid> </def> </instruction> <instruction> <mnemonic>movaps</mnemonic> <def> - <pfx>aso rexr rexx rexb</pfx> + <pfx>aso rexr rexx rexb vexl</pfx> <opc>0f 28</opc> <opr>V W</opr> + <cpuid>sse avx</cpuid> </def> <def> - <pfx>aso rexr rexx rexb</pfx> + <pfx>aso rexr rexx rexb vexl</pfx> <opc>0f 29</opc> <opr>W V</opr> + <cpuid>sse avx</cpuid> </def> </instruction> @@ -4735,23 +4883,52 @@ <mnemonic>movd</mnemonic> <def> <pfx>aso rexw rexr rexx rexb</pfx> - <opc>sse66 0f 6e</opc> - <opr>V Ex</opr> + <opc>0f 6e /o=16</opc> + <opr>P Ey</opr> + <cpuid>mmx</cpuid> </def> <def> - <pfx>aso rexr rexx rexb</pfx> - <opc>0f 6e</opc> - <opr>P Ex</opr> + <pfx>aso rexw rexr rexx rexb</pfx> + <opc>0f 6e /o=32</opc> + <opr>P Ey</opr> + <cpuid>mmx</cpuid> </def> + <def> <pfx>aso rexw rexr rexx rexb</pfx> - <opc>sse66 0f 7e</opc> - <opr>Ex V</opr> + <opc>/sse=66 0f 6e /o=16</opc> + <opr>V Ey</opr> + <cpuid>sse2 avx</cpuid> </def> <def> - <pfx>aso rexr rexx rexb</pfx> - <opc>0f 7e</opc> - <opr>Ex P</opr> + <pfx>aso rexw rexr rexx rexb</pfx> + <opc>/sse=66 0f 6e /o=32</opc> + <opr>V Ey</opr> + <cpuid>sse2 avx</cpuid> + </def> + <def> + <pfx>aso rexw rexr rexx rexb</pfx> + <opc>0f 7e /o=16</opc> + <opr>Ey P</opr> + <cpuid>mmx</cpuid> + </def> + <def> + <pfx>aso rexw rexr rexx rexb</pfx> + <opc>0f 7e /o=32</opc> + <opr>Ey P</opr> + <cpuid>mmx</cpuid> + </def> + <def> + <pfx>aso rexw rexr rexx rexb</pfx> + <opc>/sse=66 0f 7e /o=16</opc> + <opr>Ey V</opr> + <cpuid>sse2 avx</cpuid> + </def> + <def> + <pfx>aso rexw rexr rexx rexb</pfx> + <opc>/sse=66 0f 7e /o=32</opc> + <opr>Ey V</opr> + <cpuid>sse2 avx</cpuid> </def> </instruction> @@ -4759,13 +4936,15 @@ <mnemonic>movhpd</mnemonic> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 16 /mod=!11</opc> - <opr>V M</opr> + <opc>/sse=66 0f 16 /mod=!11</opc> + <opr>V H M</opr> + <cpuid>sse2 avx</cpuid> </def> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 17</opc> + <opc>/sse=66 0f 17</opc> <opr>M V</opr> + <cpuid>sse2 avx</cpuid> </def> </instruction> @@ -4774,12 +4953,14 @@ <def> <pfx>aso rexr rexx rexb</pfx> <opc>0f 16 /mod=!11</opc> - <opr>V M</opr> + <opr>V H M</opr> + <cpuid>sse avx</cpuid> </def> <def> <pfx>aso rexr rexx rexb</pfx> <opc>0f 17</opc> <opr>M V</opr> + <cpuid>sse avx</cpuid> </def> </instruction> @@ -4788,7 +4969,8 @@ <def> <pfx>aso rexr rexx rexb</pfx> <opc>0f 16 /mod=11</opc> - <opr>V VR</opr> + <opr>V H U</opr> + <cpuid>sse avx</cpuid> </def> </instruction> @@ -4796,14 +4978,15 @@ <mnemonic>movlpd</mnemonic> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 12 /mod=!11</opc> + <opc>/sse=66 0f 12 /mod=!11</opc> <opr>V M</opr> </def> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 13</opc> + <opc>/sse=66 0f 13</opc> <opr>M V</opr> </def> + <cpuid>sse2 avx</cpuid> </instruction> <instruction> @@ -4818,6 +5001,7 @@ <opc>0f 13</opc> <opr>M V</opr> </def> + <cpuid>sse avx</cpuid> </instruction> <instruction> @@ -4825,16 +5009,18 @@ <def> <pfx>aso rexr rexx rexb</pfx> <opc>0f 12 /mod=11</opc> - <opr>V VR</opr> + <opr>V U</opr> + <cpuid>sse avx</cpuid> </def> </instruction> <instruction> <mnemonic>movmskpd</mnemonic> <def> - <pfx>oso rexr rexb</pfx> - <opc>sse66 0f 50</opc> - <opr>Gd VR</opr> + <pfx>oso rexr rexb vexl</pfx> + <opc>/sse=66 0f 50</opc> + <opr>Gd U</opr> + <cpuid>sse2 avx</cpuid> </def> </instruction> @@ -4843,16 +5029,18 @@ <def> <pfx>oso rexr rexb</pfx> <opc>0f 50</opc> - <opr>Gd VR</opr> + <opr>Gd U</opr> + <cpuid>sse2 avx</cpuid> </def> </instruction> <instruction> <mnemonic>movntdq</mnemonic> <def> - <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f e7</opc> + <pfx>aso rexr rexx rexb vexl</pfx> + <opc>/sse=66 0f e7</opc> <opr>M V</opr> + <cpuid>sse2 avx</cpuid> </def> </instruction> @@ -4868,24 +5056,27 @@ <instruction> <mnemonic>movntpd</mnemonic> <def> - <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 2b</opc> + <pfx>aso rexr rexx rexb vexl</pfx> + <opc>/sse=66 0f 2b</opc> <opr>M V</opr> + <cpuid>sse2 avx</cpuid> </def> </instruction> <instruction> <mnemonic>movntps</mnemonic> <def> - <pfx>aso rexr rexx rexb</pfx> + <pfx>aso rexr rexx rexb vexl</pfx> <opc>0f 2b</opc> <opr>M V</opr> + <cpuid>sse2 avx</cpuid> </def> </instruction> <instruction> <mnemonic>movntq</mnemonic> <def> + <pfx>aso rexr rexx rexb</pfx> <opc>0f e7</opc> <opr>M P</opr> </def> @@ -4894,31 +5085,59 @@ <instruction> <mnemonic>movq</mnemonic> <def> - <pfx>aso rexr rexx rexb</pfx> - <opc>0f 6f</opc> - <opr>P Q</opr> + <pfx>aso rexw rexr rexx rexb</pfx> + <opc>0f 6e /o=64</opc> + <opr>P Eq</opr> + <cpuid>mmx</cpuid> </def> <def> - <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f d6</opc> - <opr>W V</opr> + <pfx>aso rexw rexr rexx rexb</pfx> + <opc>/sse=66 0f 6e /o=64</opc> + <opr>V Eq</opr> + <cpuid>sse2 avx</cpuid> </def> <def> - <pfx>aso rexr rexx rexb</pfx> - <opc>ssef3 0f 7e</opc> + <pfx>aso rexw rexr rexx rexb</pfx> + <opc>0f 7e /o=64</opc> + <opr>Eq P</opr> + <cpuid>mmx</cpuid> + </def> + <def> + <pfx>aso rexw rexr rexx rexb</pfx> + <opc>/sse=66 0f 7e /o=64</opc> + <opr>Eq V</opr> + <cpuid>sse2 avx</cpuid> + </def> + <def> + <pfx>aso rexw rexr rexx rexb</pfx> + <opc>/sse=f3 0f 7e</opc> <opr>V W</opr> + <cpuid>sse2 avx</cpuid> </def> <def> - <pfx>aso rexr rexx rexb</pfx> + <pfx>aso rexw rexr rexx rexb</pfx> + <opc>/sse=66 0f d6</opc> + <opr>W V</opr> + <cpuid>sse2 avx</cpuid> + </def> + <def> + <pfx>aso rexw rexr rexx rexb</pfx> + <opc>0f 6f</opc> + <opr>P Q</opr> + <cpuid>mmx</cpuid> + </def> + <def> + <pfx>aso rexw rexr rexx rexb</pfx> <opc>0f 7f</opc> <opr>Q P</opr> + <cpuid>mmx</cpuid> </def> </instruction> <instruction> <mnemonic>movsb</mnemonic> <def> - <pfx>seg</pfx> + <pfx>rep seg</pfx> <opc>a4</opc> </def> </instruction> @@ -4926,7 +5145,7 @@ <instruction> <mnemonic>movsw</mnemonic> <def> - <pfx>seg oso rexw</pfx> + <pfx>rep seg oso rexw</pfx> <opc>a5 /o=16</opc> </def> </instruction> @@ -4934,25 +5153,27 @@ <instruction> <mnemonic>movsd</mnemonic> <def> - <pfx>seg oso rexw</pfx> + <pfx>rep seg oso rexw</pfx> <opc>a5 /o=32</opc> </def> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>ssef2 0f 10</opc> - <opr>V W</opr> + <opc>/sse=f2 0f 10</opc> + <opr>V MqU</opr> + <cpuid>sse2</cpuid> </def> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>ssef2 0f 11</opc> + <opc>/sse=f2 0f 11</opc> <opr>W V</opr> + <cpuid>sse2</cpuid> </def> </instruction> <instruction> <mnemonic>movsq</mnemonic> <def> - <pfx>seg oso rexw</pfx> + <pfx>rep seg oso rexw</pfx> <opc>a5 /o=64</opc> </def> </instruction> @@ -4961,13 +5182,15 @@ <mnemonic>movss</mnemonic> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>ssef3 0f 10</opc> - <opr>V W</opr> + <opc>/sse=f3 0f 10</opc> + <opr>V MdU</opr> + <cpuid>sse</cpuid> </def> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>ssef3 0f 11</opc> + <opc>/sse=f3 0f 11</opc> <opr>W V</opr> + <cpuid>sse</cpuid> </def> </instruction> @@ -4981,35 +5204,39 @@ <def> <pfx>aso oso rexw rexr rexx rexb</pfx> <opc>0f bf</opc> - <opr>Gv Ew</opr> + <opr>Gy Ew</opr> </def> </instruction> <instruction> <mnemonic>movupd</mnemonic> <def> - <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 10</opc> + <pfx>aso rexr rexx rexb vexl</pfx> + <opc>/sse=66 0f 10</opc> <opr>V W</opr> + <cpuid>sse2 avx</cpuid> </def> <def> - <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 11</opc> + <pfx>aso rexr rexx rexb vexl</pfx> + <opc>/sse=66 0f 11</opc> <opr>W V</opr> + <cpuid>sse2 avx</cpuid> </def> </instruction> <instruction> <mnemonic>movups</mnemonic> <def> - <pfx>aso rexr rexx rexb</pfx> + <pfx>aso rexr rexx rexb vexl</pfx> <opc>0f 10</opc> <opr>V W</opr> + <cpuid>sse2 avx</cpuid> </def> <def> - <pfx>aso rexr rexx rexb</pfx> + <pfx>aso rexr rexx rexb vexl</pfx> <opc>0f 11</opc> <opr>W V</opr> + <cpuid>sse2 avx</cpuid> </def> </instruction> @@ -5023,7 +5250,7 @@ <def> <pfx>aso oso rexw rexr rexx rexb</pfx> <opc>0f b7</opc> - <opr>Gv Ew</opr> + <opr>Gy Ew</opr> </def> </instruction> @@ -5044,18 +5271,20 @@ <instruction> <mnemonic>mulpd</mnemonic> <def> - <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 59</opc> - <opr>V W</opr> + <pfx>aso rexr rexx rexb vexl</pfx> + <opc>/sse=66 0f 59</opc> + <opr>V H W</opr> + <cpuid>sse2 avx</cpuid> </def> </instruction> <instruction> <mnemonic>mulps</mnemonic> <def> - <pfx>aso rexr rexx rexb</pfx> + <pfx>aso rexr rexx rexb vexl</pfx> <opc>0f 59</opc> - <opr>V W</opr> + <opr>V H W</opr> + <cpuid>sse2 avx</cpuid> </def> </instruction> @@ -5063,8 +5292,9 @@ <mnemonic>mulsd</mnemonic> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>ssef2 0f 59</opc> - <opr>V W</opr> + <opc>/sse=f2 0f 59</opc> + <opr>V H W</opr> + <cpuid>sse2 avx</cpuid> </def> </instruction> @@ -5072,8 +5302,9 @@ <mnemonic>mulss</mnemonic> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>ssef3 0f 59</opc> - <opr>V W</opr> + <opc>/sse=f3 0f 59</opc> + <opr>V H W</opr> + <cpuid>sse avx</cpuid> </def> </instruction> @@ -5101,9 +5332,6 @@ <instruction> <mnemonic>nop</mnemonic> <def> - <opc>90</opc> - </def> - <def> <pfx>aso rexr rexx rexb</pfx> <opc>0f 19</opc> <opr>M</opr> @@ -5183,8 +5411,7 @@ <def> <pfx>oso rexw</pfx> <opc>0d</opc> - <opr>rAX Iz</opr> - <syn>sext</syn> + <opr>rAX sIz</opr> </def> <def> <pfx>aso rexr rexx rexb</pfx> @@ -5194,38 +5421,37 @@ <def> <pfx>aso oso rexw rexr rexx rexb</pfx> <opc>81 /reg=1</opc> - <opr>Ev Iz</opr> - <syn>sext</syn> + <opr>Ev sIz</opr> </def> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>82 /reg=1</opc> + <opc>82 /reg=1 /m=!64</opc> <opr>Eb Ib</opr> - <mode>inv64</mode> </def> <def> <pfx>aso oso rexw rexr rexx rexb</pfx> <opc>83 /reg=1</opc> - <opr>Ev Ib</opr> - <syn>sext</syn> + <opr>Ev sIb</opr> </def> </instruction> <instruction> <mnemonic>orpd</mnemonic> <def> - <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 56</opc> - <opr>V W</opr> + <pfx>aso rexr rexx rexb vexl</pfx> + <opc>/sse=66 0f 56</opc> + <opr>V H W</opr> + <cpuid>sse2 avx</cpuid> </def> </instruction> <instruction> <mnemonic>orps</mnemonic> <def> - <pfx>aso rexr rexx rexb</pfx> + <pfx>aso rexr rexx rexb vexl</pfx> <opc>0f 56</opc> - <opr>V W</opr> + <opr>V H W</opr> + <cpuid>sse avx</cpuid> </def> </instruction> @@ -5254,6 +5480,7 @@ <instruction> <mnemonic>outsb</mnemonic> <def> + <pfx>rep seg</pfx> <opc>6e</opc> </def> </instruction> @@ -5261,7 +5488,7 @@ <instruction> <mnemonic>outsw</mnemonic> <def> - <pfx>oso</pfx> + <pfx>rep oso seg</pfx> <opc>6f /o=16</opc> </def> </instruction> @@ -5269,72 +5496,72 @@ <instruction> <mnemonic>outsd</mnemonic> <def> - <pfx>oso</pfx> + <pfx>rep oso seg</pfx> <opc>6f /o=32</opc> </def> </instruction> <instruction> - <mnemonic>outsq</mnemonic> - <def> - <pfx>oso</pfx> - <opc>6f /o=64</opc> - </def> - </instruction> - - <instruction> <mnemonic>packsswb</mnemonic> <def> - <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 63</opc> - <opr>V W</opr> + <pfx>aso rexr rexx rexb vexl</pfx> + <opc>/sse=66 0f 63</opc> + <opr>V H W</opr> + <cpuid>sse2 avx</cpuid> </def> <def> <pfx>aso rexr rexx rexb</pfx> <opc>0f 63</opc> <opr>P Q</opr> + <cpuid>mmx</cpuid> </def> </instruction> <instruction> <mnemonic>packssdw</mnemonic> <def> - <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 6b</opc> - <opr>V W</opr> + <pfx>aso rexr rexx rexb vexl</pfx> + <opc>/sse=66 0f 6b</opc> + <opr>V H W</opr> + <cpuid>sse2 avx</cpuid> </def> <def> <pfx>aso rexr rexx rexb</pfx> <opc>0f 6b</opc> <opr>P Q</opr> + <cpuid>mmx</cpuid> </def> </instruction> <instruction> <mnemonic>packuswb</mnemonic> <def> - <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 67</opc> - <opr>V W</opr> + <pfx>aso rexr rexx rexb vexl</pfx> + <opc>/sse=66 0f 67</opc> + <opr>V H W</opr> + <cpuid>sse2 avx</cpuid> </def> <def> <pfx>aso rexr rexx rexb</pfx> <opc>0f 67</opc> <opr>P Q</opr> + <cpuid>mmx</cpuid> </def> </instruction> <instruction> <mnemonic>paddb</mnemonic> <def> - <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f fc</opc> - <opr>V W</opr> + <pfx>aso rexr rexx rexb vexl</pfx> + <opc>/sse=66 0f fc</opc> + <opr>V H W</opr> + <cpuid>sse2 avx</cpuid> </def> <def> <pfx>aso rexr rexx rexb</pfx> <opc>0f fc</opc> <opr>P Q</opr> + <cpuid>mmx</cpuid> </def> </instruction> @@ -5344,11 +5571,13 @@ <pfx>aso rexr rexx rexb</pfx> <opc>0f fd</opc> <opr>P Q</opr> + <cpuid>mmx</cpuid> </def> <def> - <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f fd</opc> - <opr>V W</opr> + <pfx>aso rexr rexx rexb vexl</pfx> + <opc>/sse=66 0f fd</opc> + <opr>V H W</opr> + <cpuid>sse2 avx</cpuid> </def> </instruction> @@ -5358,11 +5587,13 @@ <pfx>aso rexr rexx rexb</pfx> <opc>0f fe</opc> <opr>P Q</opr> + <cpuid>mmx</cpuid> </def> <def> - <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f fe</opc> - <opr>V W</opr> + <pfx>aso rexr rexx rexb vexl</pfx> + <opc>/sse=66 0f fe</opc> + <opr>V H W</opr> + <cpuid>sse2 avx</cpuid> </def> </instruction> @@ -5376,8 +5607,9 @@ </def> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f ec</opc> - <opr>V W</opr> + <opc>/sse=66 0f ec</opc> + <opr>V H W</opr> + <cpuid>sse2 avx</cpuid> </def> </instruction> @@ -5390,8 +5622,9 @@ </def> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f ed</opc> - <opr>V W</opr> + <opc>/sse=66 0f ed</opc> + <opr>V H W</opr> + <cpuid>sse2 avx</cpuid> </def> </instruction> @@ -5404,8 +5637,9 @@ </def> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f dc</opc> - <opr>V W</opr> + <opc>/sse=66 0f dc</opc> + <opr>V H W</opr> + <cpuid>sse2 avx</cpuid> </def> </instruction> @@ -5418,8 +5652,9 @@ </def> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f dd</opc> - <opr>V W</opr> + <opc>/sse=66 0f dd</opc> + <opr>V H W</opr> + <cpuid>sse2 avx</cpuid> </def> </instruction> @@ -5427,8 +5662,9 @@ <mnemonic>pand</mnemonic> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f db</opc> - <opr>V W</opr> + <opc>/sse=66 0f db</opc> + <opr>V H W</opr> + <cpuid>sse2 avx</cpuid> </def> <def> <pfx>aso rexr rexx rexb</pfx> @@ -5441,8 +5677,9 @@ <mnemonic>pandn</mnemonic> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f df</opc> - <opr>V W</opr> + <opc>/sse=66 0f df</opc> + <opr>V H W</opr> + <cpuid>sse2 avx</cpuid> </def> <def> <pfx>aso rexr rexx rexb</pfx> @@ -5455,8 +5692,9 @@ <mnemonic>pavgb</mnemonic> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f e0</opc> - <opr>V W</opr> + <opc>/sse=66 0f e0</opc> + <opr>V H W</opr> + <cpuid>sse2 avx</cpuid> </def> <def> <pfx>aso rexr rexx rexb</pfx> @@ -5469,8 +5707,9 @@ <mnemonic>pavgw</mnemonic> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f e3</opc> - <opr>V W</opr> + <opc>/sse=66 0f e3</opc> + <opr>V H W</opr> + <cpuid>sse2 avx</cpuid> </def> <def> <pfx>aso rexr rexx rexb</pfx> @@ -5488,8 +5727,9 @@ </def> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 74</opc> - <opr>V W</opr> + <opc>/sse=66 0f 74</opc> + <opr>V H W</opr> + <cpuid>sse2 avx</cpuid> </def> </instruction> @@ -5502,8 +5742,9 @@ </def> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 75</opc> - <opr>V W</opr> + <opc>/sse=66 0f 75</opc> + <opr>V H W</opr> + <cpuid>sse2 avx</cpuid> </def> </instruction> @@ -5516,8 +5757,9 @@ </def> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 76</opc> - <opr>V W</opr> + <opc>/sse=66 0f 76</opc> + <opr>V H W</opr> + <cpuid>sse2 avx</cpuid> </def> </instruction> @@ -5525,8 +5767,9 @@ <mnemonic>pcmpgtb</mnemonic> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 64</opc> - <opr>V W</opr> + <opc>/sse=66 0f 64</opc> + <opr>V H W</opr> + <cpuid>sse2 avx</cpuid> </def> <def> <pfx>aso rexr rexx rexb</pfx> @@ -5539,8 +5782,9 @@ <mnemonic>pcmpgtw</mnemonic> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 65</opc> - <opr>V W</opr> + <opc>/sse=66 0f 65</opc> + <opr>V H W</opr> + <cpuid>sse2 avx</cpuid> </def> <def> <pfx>aso rexr rexx rexb</pfx> @@ -5553,8 +5797,9 @@ <mnemonic>pcmpgtd</mnemonic> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 66</opc> - <opr>V W</opr> + <opc>/sse=66 0f 66</opc> + <opr>V H W</opr> + <cpuid>sse2 avx</cpuid> </def> <def> <pfx>aso rexr rexx rexb</pfx> @@ -5566,24 +5811,27 @@ <instruction> <mnemonic>pextrb</mnemonic> <def> - <pfx>aso rexr rexb</pfx> - <opc>sse66 0f 3a 14</opc> + <pfx>aso rexx rexr rexb</pfx> + <opc>/sse=66 0f 3a 14 /vexw=0</opc> <opr>MbRv V Ib</opr> <mode>def64</mode> + <cpuid>sse4.1 avx</cpuid> </def> </instruction> <instruction> <mnemonic>pextrd</mnemonic> <def> - <pfx>aso rexr rexw rexb</pfx> - <opc>sse66 0f 3a 16 /o=16</opc> - <opr>Ev V Ib</opr> + <pfx>aso rexr rexx rexw rexb</pfx> + <opc>/sse=66 0f 3a 16 /o=16 /vexw=0</opc> + <opr>Ed V Ib</opr> + <cpuid>sse4.1 avx</cpuid> </def> <def> - <pfx>aso rexr rexw rexb</pfx> - <opc>sse66 0f 3a 16 /o=32</opc> - <opr>Ev V Ib</opr> + <pfx>aso rexr rexx rexw rexb</pfx> + <opc>/sse=66 0f 3a 16 /o=32 /vexw=0</opc> + <opr>Ed V Ib</opr> + <cpuid>sse4.1 avx</cpuid> </def> </instruction> @@ -5591,40 +5839,126 @@ <mnemonic>pextrq</mnemonic> <def> <pfx>aso rexr rexw rexb</pfx> - <opc>sse66 0f 3a 16 /o=64</opc> - <opr>Ev V Ib</opr> + <opc>/sse=66 0f 3a 16 /o=64 /vexw=1</opc> + <opr>Eq V Ib</opr> <mode>def64</mode> + <cpuid>sse4.1 avx</cpuid> </def> </instruction> <instruction> <mnemonic>pextrw</mnemonic> <def> - <pfx>aso rexr rexb</pfx> - <opc>sse66 0f c5</opc> - <opr>Gd VR Ib</opr> + <pfx>aso rexw rexr rexb</pfx> + <opc>/sse=66 0f c5</opc> + <opr>Gd U Ib</opr> + <cpuid>sse avx</cpuid> </def> <def> - <pfx>aso oso rexw rexr rexx rexb</pfx> + <pfx>aso rexw rexr rexx rexb</pfx> <opc>0f c5</opc> - <opr>Gd PR Ib</opr> + <opr>Gd N Ib</opr> + </def> + <def> + <pfx>aso rexw rexx rexr rexb</pfx> + <opc>/sse=66 0f 3a 15</opc> + <opr>MwRd V Ib</opr> + <cpuid>sse4.1 avx</cpuid> + </def> + </instruction> + + <instruction> + <mnemonic>pinsrb</mnemonic> + <def> + <pfx>aso rexw rexr rexx rexb</pfx> + <opc>/sse=66 0f 3a 20</opc> + <opr>V MbRd Ib</opr> + <cpuid>sse4.1</cpuid> </def> </instruction> <instruction> <mnemonic>pinsrw</mnemonic> <def> - <pfx>aso oso rexw rexr rexx rexb</pfx> + <pfx>aso rexw rexr rexx rexb</pfx> <opc>0f c4</opc> - <opr>P Ew Ib</opr> + <opr>P MwRy Ib</opr> + <mode>def64</mode> </def> <def> <pfx>aso rexw rexr rexx rexb</pfx> - <opc>sse66 0f c4</opc> - <opr>V Ew Ib</opr> + <opc>/sse=66 0f c4</opc> + <opr>V MwRy Ib</opr> + <mode>def64</mode> + <cpuid>sse2 avx</cpuid> + </def> + </instruction> + + <instruction> + <mnemonic>pinsrd</mnemonic> + <def> + <pfx>aso rexw rexr rexx rexb</pfx> + <opc>/sse=66 0f 3a 22 /o=16</opc> + <opr>V Ed Ib</opr> + <cpuid>sse4.1</cpuid> + </def> + + <def> + <pfx>aso rexw rexr rexx rexb</pfx> + <opc>/sse=66 0f 3a 22 /o=32</opc> + <opr>V Ed Ib</opr> + <cpuid>sse4.1</cpuid> + </def> + </instruction> + + <instruction> + <mnemonic>pinsrq</mnemonic> + <def> + <pfx>aso oso rexw rexr rexx rexb</pfx> + <opc>/sse=66 0f 3a 22 /o=64</opc> + <opr>V Eq Ib</opr> + <cpuid>sse4.1</cpuid> + </def> + </instruction> + + <instruction> + <mnemonic>vpinsrb</mnemonic> + <def> + <pfx>aso rexw rexr rexx rexb</pfx> + <opc>/vex=66_0f3a 20 /vexw=0 /vexl=0</opc> + <opr>V H MbRd Ib</opr> + <cpuid>avx</cpuid> + </def> + </instruction> + + <instruction> + <mnemonic>vpinsrd</mnemonic> + <def> + <pfx>aso oso rexw rexr rexx rexb</pfx> + <opc>/vex=66_0f3a 22 /m=!64 /vexw=0 /vexl=0</opc> + <opr>V H Ed Ib</opr> + <cpuid>avx</cpuid> + </def> + <def> + <pfx>aso oso rexw rexr rexx rexb</pfx> + <opc>/vex=66_0f3a 22 /m=64 /vexw=0 /vexl=0</opc> + <opr>V H Ed Ib</opr> + <cpuid>avx</cpuid> + </def> + </instruction> + + + <instruction> + <mnemonic>vpinsrq</mnemonic> + <def> + <pfx>aso oso rexw rexr rexx rexb</pfx> + <opc>/vex=66_0f3a 22 /m=64 /vexw=1 /vexl=0</opc> + <opr>V H Eq Ib</opr> + <cpuid>avx</cpuid> </def> </instruction> + <instruction> <mnemonic>pmaddwd</mnemonic> <def> @@ -5634,8 +5968,9 @@ </def> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f f5</opc> - <opr>V W</opr> + <opc>/sse=66 0f f5</opc> + <opr>V H W</opr> + <cpuid>sse4.1 avx</cpuid> </def> </instruction> @@ -5643,8 +5978,9 @@ <mnemonic>pmaxsw</mnemonic> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f ee</opc> - <opr>V W</opr> + <opc>/sse=66 0f ee</opc> + <opr>V H W</opr> + <cpuid>sse4.1 avx</cpuid> </def> <def> <pfx>aso rexr rexx rexb</pfx> @@ -5662,8 +5998,9 @@ </def> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f de</opc> - <opr>V W</opr> + <opc>/sse=66 0f de</opc> + <opr>V H W</opr> + <cpuid>sse2 avx</cpuid> </def> </instruction> @@ -5671,8 +6008,9 @@ <mnemonic>pminsw</mnemonic> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f ea</opc> - <opr>V W</opr> + <opc>/sse=66 0f ea</opc> + <opr>V H W</opr> + <cpuid>sse2 avx</cpuid> </def> <def> <pfx>aso rexr rexx rexb</pfx> @@ -5685,8 +6023,9 @@ <mnemonic>pminub</mnemonic> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f da</opc> - <opr>V W</opr> + <opc>/sse=66 0f da</opc> + <opr>V H W</opr> + <cpuid>sse2 avx</cpuid> </def> <def> <pfx>aso rexr rexx rexb</pfx> @@ -5698,14 +6037,15 @@ <instruction> <mnemonic>pmovmskb</mnemonic> <def> - <pfx>rexr rexb</pfx> - <opc>sse66 0f d7</opc> - <opr>Gd VR</opr> + <pfx>oso rexr rexw rexb</pfx> + <opc>/sse=66 0f d7 /vexl=0</opc> + <opr>Gd U</opr> + <cpuid>sse2 avx</cpuid> </def> <def> - <pfx>oso rexr rexb</pfx> + <pfx>oso rexr rexw rexb</pfx> <opc>0f d7</opc> - <opr>Gd PR</opr> + <opr>Gd N</opr> </def> </instruction> @@ -5718,8 +6058,9 @@ </def> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f e4</opc> - <opr>V W</opr> + <opc>/sse=66 0f e4</opc> + <opr>V H W</opr> + <cpuid>sse2 avx</cpuid> </def> </instruction> @@ -5727,8 +6068,9 @@ <mnemonic>pmulhw</mnemonic> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f e5</opc> - <opr>V W</opr> + <opc>/sse=66 0f e5</opc> + <opr>V H W</opr> + <cpuid>sse2 avx</cpuid> </def> <def> <pfx>aso rexr rexx rexb</pfx> @@ -5746,25 +6088,26 @@ </def> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f d5</opc> - <opr>V W</opr> + <opc>/sse=66 0f d5</opc> + <opr>V H W</opr> + <cpuid>sse2 avx</cpuid> </def> </instruction> <instruction> <mnemonic>pop</mnemonic> <def> - <opc>07</opc> + <opc>07 /m=!64</opc> <opr>ES</opr> <mode>inv64</mode> </def> <def> - <opc>17</opc> + <opc>17 /m=!64</opc> <opr>SS</opr> <mode>inv64</mode> </def> <def> - <opc>1f</opc> + <opc>1f /m=!64</opc> <opr>DS</opr> <mode>inv64</mode> </def> @@ -5779,56 +6122,56 @@ <def> <pfx>oso rexb</pfx> <opc>58</opc> - <opr>rAXr8</opr> - <mode>def64 depM</mode> + <opr>R0v</opr> + <mode>def64</mode> </def> <def> <pfx>oso rexb</pfx> <opc>59</opc> - <opr>rCXr9</opr> - <mode>def64 depM</mode> + <opr>R1v</opr> + <mode>def64</mode> </def> <def> <pfx>oso rexb</pfx> <opc>5a</opc> - <opr>rDXr10</opr> - <mode>def64 depM</mode> + <opr>R2v</opr> + <mode>def64</mode> </def> <def> <pfx>oso rexb</pfx> <opc>5b</opc> - <opr>rBXr11</opr> - <mode>def64 depM</mode> + <opr>R3v</opr> + <mode>def64</mode> </def> <def> <pfx>oso rexb</pfx> <opc>5c</opc> - <opr>rSPr12</opr> - <mode>def64 depM</mode> + <opr>R4v</opr> + <mode>def64</mode> </def> <def> <pfx>oso rexb</pfx> <opc>5d</opc> - <opr>rBPr13</opr> - <mode>def64 depM</mode> + <opr>R5v</opr> + <mode>def64</mode> </def> <def> <pfx>oso rexb</pfx> <opc>5e</opc> - <opr>rSIr14</opr> - <mode>def64 depM</mode> + <opr>R6v</opr> + <mode>def64</mode> </def> <def> <pfx>oso rexb</pfx> <opc>5f</opc> - <opr>rDIr15</opr> - <mode>def64 depM</mode> + <opr>R7v</opr> + <mode>def64</mode> </def> <def> <pfx>aso oso rexw rexr rexx rexb</pfx> <opc>8f /reg=0</opc> <opr>Ev</opr> - <mode>def64 depM</mode> + <mode>def64</mode> </def> </instruction> @@ -5836,7 +6179,7 @@ <mnemonic>popa</mnemonic> <def> <pfx>oso</pfx> - <opc>61 /o=16</opc> + <opc>61 /o=16 /m=!64</opc> <mode>inv64</mode> </def> </instruction> @@ -5845,7 +6188,7 @@ <mnemonic>popad</mnemonic> <def> <pfx>oso</pfx> - <opc>61 /o=32</opc> + <opc>61 /o=32 /m=!64</opc> <mode>inv64</mode> </def> </instruction> @@ -5854,13 +6197,7 @@ <mnemonic>popfw</mnemonic> <def> <pfx>oso</pfx> - <opc>9d /m=32 /o=16</opc> - <mode>def64 depM</mode> - </def> - <def> - <pfx>oso</pfx> - <opc>9d /m=16 /o=16</opc> - <mode>def64 depM</mode> + <opc>9d /m=!64 /o=16</opc> </def> </instruction> @@ -5868,13 +6205,7 @@ <mnemonic>popfd</mnemonic> <def> <pfx>oso</pfx> - <opc>9d /m=16 /o=32</opc> - <mode>def64 depM</mode> - </def> - <def> - <pfx>oso</pfx> - <opc>9d /m=32 /o=32</opc> - <mode>def64 depM</mode> + <opc>9d /m=!64 /o=32</opc> </def> </instruction> @@ -5882,8 +6213,13 @@ <mnemonic>popfq</mnemonic> <def> <pfx>oso</pfx> + <opc>9d /m=64 /o=32</opc> + <mode>def64</mode> + </def> + <def> + <pfx>oso</pfx> <opc>9d /m=64 /o=64</opc> - <mode>def64 depM</mode> + <mode>def64</mode> </def> </instruction> @@ -5891,8 +6227,9 @@ <mnemonic>por</mnemonic> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f eb</opc> - <opr>V W</opr> + <opc>/sse=66 0f eb</opc> + <opr>V H W</opr> + <cpuid>sse2 avx</cpuid> </def> <def> <pfx>aso rexr rexx rexb</pfx> @@ -5985,8 +6322,9 @@ <mnemonic>psadbw</mnemonic> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f f6</opc> - <opr>V W</opr> + <opc>/sse=66 0f f6</opc> + <opr>V H W</opr> + <cpuid>sse2 avx</cpuid> </def> <def> <pfx>aso rexr rexx rexb</pfx> @@ -6004,12 +6342,13 @@ </def> </instruction> - <instruction> + <instruction> <mnemonic>psllw</mnemonic> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f f1</opc> + <opc>/sse=66 0f f1</opc> <opr>V W</opr> + <cpuid>sse2</cpuid> </def> <def> <pfx>aso rexr rexx rexb</pfx> @@ -6018,12 +6357,13 @@ </def> <def> <pfx>rexb</pfx> - <opc>sse66 0f 71 /reg=6</opc> - <opr>VR Ib</opr> + <opc>/sse=66 0f 71 /reg=6</opc> + <opr>U Ib</opr> + <cpuid>sse2</cpuid> </def> <def> <opc>0f 71 /reg=6</opc> - <opr>PR Ib</opr> + <opr>N Ib</opr> </def> </instruction> @@ -6031,8 +6371,9 @@ <mnemonic>pslld</mnemonic> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f f2</opc> + <opc>/sse=66 0f f2</opc> <opr>V W</opr> + <cpuid>sse2</cpuid> </def> <def> <pfx>aso rexr rexx rexb</pfx> @@ -6041,12 +6382,13 @@ </def> <def> <pfx>rexb</pfx> - <opc>sse66 0f 72 /reg=6</opc> - <opr>VR Ib</opr> + <opc>/sse=66 0f 72 /reg=6</opc> + <opr>U Ib</opr> + <cpuid>sse2</cpuid> </def> <def> <opc>0f 72 /reg=6</opc> - <opr>PR Ib</opr> + <opr>N Ib</opr> </def> </instruction> @@ -6054,8 +6396,9 @@ <mnemonic>psllq</mnemonic> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f f3</opc> + <opc>/sse=66 0f f3</opc> <opr>V W</opr> + <cpuid>sse2</cpuid> </def> <def> <pfx>aso rexr rexx rexb</pfx> @@ -6064,12 +6407,13 @@ </def> <def> <pfx>rexb</pfx> - <opc>sse66 0f 73 /reg=6</opc> - <opr>VR Ib</opr> + <opc>/sse=66 0f 73 /reg=6</opc> + <opr>U Ib</opr> + <cpuid>sse2</cpuid> </def> <def> <opc>0f 73 /reg=6</opc> - <opr>PR Ib</opr> + <opr>N Ib</opr> </def> </instruction> @@ -6082,17 +6426,19 @@ </def> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f e1</opc> - <opr>V W</opr> + <opc>/sse=66 0f e1</opc> + <opr>V H W</opr> + <cpuid>sse2 avx</cpuid> </def> <def> <pfx>rexb</pfx> - <opc>sse66 0f 71 /reg=4</opc> - <opr>VR Ib</opr> + <opc>/sse=66 0f 71 /reg=4</opc> + <opr>H U Ib</opr> + <cpuid>sse2 avx</cpuid> </def> <def> <opc>0f 71 /reg=4</opc> - <opr>PR Ib</opr> + <opr>N Ib</opr> </def> </instruction> @@ -6100,12 +6446,13 @@ <mnemonic>psrad</mnemonic> <def> <opc>0f 72 /reg=4</opc> - <opr>PR Ib</opr> + <opr>N Ib</opr> </def> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f e2</opc> - <opr>V W</opr> + <opc>/sse=66 0f e2</opc> + <opr>V H W</opr> + <cpuid>sse2 avx</cpuid> </def> <def> <pfx>aso rexr rexx rexb</pfx> @@ -6114,8 +6461,9 @@ </def> <def> <pfx>rexb</pfx> - <opc>sse66 0f 72 /reg=4</opc> - <opr>VR Ib</opr> + <opc>/sse=66 0f 72 /reg=4</opc> + <opr>H U Ib</opr> + <cpuid>sse2 avx</cpuid> </def> </instruction> @@ -6123,7 +6471,7 @@ <mnemonic>psrlw</mnemonic> <def> <opc>0f 71 /reg=2</opc> - <opr>PR Ib</opr> + <opr>N Ib</opr> </def> <def> <pfx>aso rexr rexx rexb</pfx> @@ -6132,13 +6480,15 @@ </def> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f d1</opc> - <opr>V W</opr> + <opc>/sse=66 0f d1</opc> + <opr>V H W</opr> + <cpuid>sse2 avx</cpuid> </def> <def> <pfx>rexb</pfx> - <opc>sse66 0f 71 /reg=2</opc> - <opr>VR Ib</opr> + <opc>/sse=66 0f 71 /reg=2</opc> + <opr>H U Ib</opr> + <cpuid>sse2 avx</cpuid> </def> </instruction> @@ -6146,7 +6496,7 @@ <mnemonic>psrld</mnemonic> <def> <opc>0f 72 /reg=2</opc> - <opr>PR Ib</opr> + <opr>N Ib</opr> </def> <def> <pfx>aso rexr rexx rexb</pfx> @@ -6155,13 +6505,15 @@ </def> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f d2</opc> - <opr>V W</opr> + <opc>/sse=66 0f d2</opc> + <opr>V H W</opr> + <cpuid>sse2 avx</cpuid> </def> <def> <pfx>rexb</pfx> - <opc>sse66 0f 72 /reg=2</opc> - <opr>VR Ib</opr> + <opc>/sse=66 0f 72 /reg=2</opc> + <opr>H U Ib</opr> + <cpuid>sse2 avx</cpuid> </def> </instruction> @@ -6169,7 +6521,7 @@ <mnemonic>psrlq</mnemonic> <def> <opc>0f 73 /reg=2</opc> - <opr>PR Ib</opr> + <opr>N Ib</opr> </def> <def> <pfx>aso rexr rexx rexb</pfx> @@ -6178,13 +6530,15 @@ </def> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f d3</opc> - <opr>V W</opr> + <opc>/sse=66 0f d3</opc> + <opr>V H W</opr> + <cpuid>sse2 avx</cpuid> </def> <def> <pfx>rexb</pfx> - <opc>sse66 0f 73 /reg=2</opc> - <opr>VR Ib</opr> + <opc>/sse=66 0f 73 /reg=2</opc> + <opr>H U Ib</opr> + <cpuid>sse2 avx</cpuid> </def> </instruction> @@ -6192,8 +6546,9 @@ <mnemonic>psubb</mnemonic> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f f8</opc> - <opr>V W</opr> + <opc>/sse=66 0f f8</opc> + <opr>V H W</opr> + <cpuid>sse2 avx</cpuid> </def> <def> <pfx>aso rexr rexx rexb</pfx> @@ -6206,8 +6561,9 @@ <mnemonic>psubw</mnemonic> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f f9</opc> - <opr>V W</opr> + <opc>/sse=66 0f f9</opc> + <opr>V H W</opr> + <cpuid>sse2 avx</cpuid> </def> <def> <pfx>aso rexr rexx rexb</pfx> @@ -6225,8 +6581,9 @@ </def> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f fa</opc> - <opr>V W</opr> + <opc>/sse=66 0f fa</opc> + <opr>V H W</opr> + <cpuid>sse2 avx</cpuid> </def> </instruction> @@ -6239,8 +6596,9 @@ </def> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f e8</opc> - <opr>V W</opr> + <opc>/sse=66 0f e8</opc> + <opr>V H W</opr> + <cpuid>sse2 avx</cpuid> </def> </instruction> @@ -6253,8 +6611,9 @@ </def> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f e9</opc> - <opr>V W</opr> + <opc>/sse=66 0f e9</opc> + <opr>V H W</opr> + <cpuid>sse2 avx</cpuid> </def> </instruction> @@ -6267,8 +6626,9 @@ </def> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f d8</opc> - <opr>V W</opr> + <opc>/sse=66 0f d8</opc> + <opr>V H W</opr> + <cpuid>sse2 avx</cpuid> </def> </instruction> @@ -6281,8 +6641,9 @@ </def> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f d9</opc> - <opr>V W</opr> + <opc>/sse=66 0f d9</opc> + <opr>V H W</opr> + <cpuid>sse2 avx</cpuid> </def> </instruction> @@ -6290,8 +6651,9 @@ <mnemonic>punpckhbw</mnemonic> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 68</opc> - <opr>V W</opr> + <opc>/sse=66 0f 68</opc> + <opr>V H W</opr> + <cpuid>sse2 avx</cpuid> </def> <def> <pfx>aso rexr rexx rexb</pfx> @@ -6304,8 +6666,9 @@ <mnemonic>punpckhwd</mnemonic> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 69</opc> - <opr>V W</opr> + <opc>/sse=66 0f 69</opc> + <opr>V H W</opr> + <cpuid>sse2 avx</cpuid> </def> <def> <pfx>aso rexr rexx rexb</pfx> @@ -6318,8 +6681,9 @@ <mnemonic>punpckhdq</mnemonic> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 6a</opc> - <opr>V W</opr> + <opc>/sse=66 0f 6a</opc> + <opr>V H W</opr> + <cpuid>sse2 avx</cpuid> </def> <def> <pfx>aso rexr rexx rexb</pfx> @@ -6332,8 +6696,9 @@ <mnemonic>punpcklbw</mnemonic> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 60</opc> - <opr>V W</opr> + <opc>/sse=66 0f 60</opc> + <opr>V H W</opr> + <cpuid>sse2 avx</cpuid> </def> <def> <pfx>aso rexr rexx rexb</pfx> @@ -6346,8 +6711,9 @@ <mnemonic>punpcklwd</mnemonic> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 61</opc> - <opr>V W</opr> + <opc>/sse=66 0f 61</opc> + <opr>V H W</opr> + <cpuid>sse2 avx</cpuid> </def> <def> <pfx>aso rexr rexx rexb</pfx> @@ -6360,8 +6726,9 @@ <mnemonic>punpckldq</mnemonic> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 62</opc> - <opr>V W</opr> + <opc>/sse=66 0f 62</opc> + <opr>V H W</opr> + <cpuid>sse2 avx</cpuid> </def> <def> <pfx>aso rexr rexx rexb</pfx> @@ -6373,6 +6740,7 @@ <instruction> <mnemonic>pi2fw</mnemonic> <def> + <pfx>aso rexr rexx rexb</pfx> <opc>0f 0f /3dnow=0c</opc> <opr>P Q</opr> </def> @@ -6381,6 +6749,7 @@ <instruction> <mnemonic>pi2fd</mnemonic> <def> + <pfx>aso rexr rexx rexb</pfx> <opc>0f 0f /3dnow=0d</opc> <opr>P Q</opr> </def> @@ -6389,6 +6758,7 @@ <instruction> <mnemonic>pf2iw</mnemonic> <def> + <pfx>aso rexr rexx rexb</pfx> <opc>0f 0f /3dnow=1c</opc> <opr>P Q</opr> </def> @@ -6397,6 +6767,7 @@ <instruction> <mnemonic>pf2id</mnemonic> <def> + <pfx>aso rexr rexx rexb</pfx> <opc>0f 0f /3dnow=1d</opc> <opr>P Q</opr> </def> @@ -6405,6 +6776,7 @@ <instruction> <mnemonic>pfnacc</mnemonic> <def> + <pfx>aso rexr rexx rexb</pfx> <opc>0f 0f /3dnow=8a</opc> <opr>P Q</opr> </def> @@ -6413,6 +6785,7 @@ <instruction> <mnemonic>pfpnacc</mnemonic> <def> + <pfx>aso rexr rexx rexb</pfx> <opc>0f 0f /3dnow=8e</opc> <opr>P Q</opr> </def> @@ -6421,6 +6794,7 @@ <instruction> <mnemonic>pfcmpge</mnemonic> <def> + <pfx>aso rexr rexx rexb</pfx> <opc>0f 0f /3dnow=90</opc> <opr>P Q</opr> </def> @@ -6429,6 +6803,7 @@ <instruction> <mnemonic>pfmin</mnemonic> <def> + <pfx>aso rexr rexx rexb</pfx> <opc>0f 0f /3dnow=94</opc> <opr>P Q</opr> </def> @@ -6437,6 +6812,7 @@ <instruction> <mnemonic>pfrcp</mnemonic> <def> + <pfx>aso rexr rexx rexb</pfx> <opc>0f 0f /3dnow=96</opc> <opr>P Q</opr> </def> @@ -6445,6 +6821,7 @@ <instruction> <mnemonic>pfrsqrt</mnemonic> <def> + <pfx>aso rexr rexx rexb</pfx> <opc>0f 0f /3dnow=97</opc> <opr>P Q</opr> </def> @@ -6453,6 +6830,7 @@ <instruction> <mnemonic>pfsub</mnemonic> <def> + <pfx>aso rexr rexx rexb</pfx> <opc>0f 0f /3dnow=9a</opc> <opr>P Q</opr> </def> @@ -6461,6 +6839,7 @@ <instruction> <mnemonic>pfadd</mnemonic> <def> + <pfx>aso rexr rexx rexb</pfx> <opc>0f 0f /3dnow=9e</opc> <opr>P Q</opr> </def> @@ -6469,6 +6848,7 @@ <instruction> <mnemonic>pfcmpgt</mnemonic> <def> + <pfx>aso rexr rexx rexb</pfx> <opc>0f 0f /3dnow=a0</opc> <opr>P Q</opr> </def> @@ -6477,6 +6857,7 @@ <instruction> <mnemonic>pfmax</mnemonic> <def> + <pfx>aso rexr rexx rexb</pfx> <opc>0f 0f /3dnow=a4</opc> <opr>P Q</opr> </def> @@ -6485,6 +6866,7 @@ <instruction> <mnemonic>pfrcpit1</mnemonic> <def> + <pfx>aso rexr rexx rexb</pfx> <opc>0f 0f /3dnow=a6</opc> <opr>P Q</opr> </def> @@ -6493,6 +6875,7 @@ <instruction> <mnemonic>pfrsqit1</mnemonic> <def> + <pfx>aso rexr rexx rexb</pfx> <opc>0f 0f /3dnow=a7</opc> <opr>P Q</opr> </def> @@ -6501,6 +6884,7 @@ <instruction> <mnemonic>pfsubr</mnemonic> <def> + <pfx>aso rexr rexx rexb</pfx> <opc>0f 0f /3dnow=aa</opc> <opr>P Q</opr> </def> @@ -6509,6 +6893,7 @@ <instruction> <mnemonic>pfacc</mnemonic> <def> + <pfx>aso rexr rexx rexb</pfx> <opc>0f 0f /3dnow=ae</opc> <opr>P Q</opr> </def> @@ -6517,6 +6902,7 @@ <instruction> <mnemonic>pfcmpeq</mnemonic> <def> + <pfx>aso rexr rexx rexb</pfx> <opc>0f 0f /3dnow=b0</opc> <opr>P Q</opr> </def> @@ -6525,6 +6911,7 @@ <instruction> <mnemonic>pfmul</mnemonic> <def> + <pfx>aso rexr rexx rexb</pfx> <opc>0f 0f /3dnow=b4</opc> <opr>P Q</opr> </def> @@ -6533,6 +6920,7 @@ <instruction> <mnemonic>pfrcpit2</mnemonic> <def> + <pfx>aso rexr rexx rexb</pfx> <opc>0f 0f /3dnow=b6</opc> <opr>P Q</opr> </def> @@ -6541,6 +6929,7 @@ <instruction> <mnemonic>pmulhrw</mnemonic> <def> + <pfx>aso rexr rexx rexb</pfx> <opc>0f 0f /3dnow=b7</opc> <opr>P Q</opr> </def> @@ -6549,6 +6938,7 @@ <instruction> <mnemonic>pswapd</mnemonic> <def> + <pfx>aso rexr rexx rexb</pfx> <opc>0f 0f /3dnow=bb</opc> <opr>P Q</opr> </def> @@ -6557,6 +6947,7 @@ <instruction> <mnemonic>pavgusb</mnemonic> <def> + <pfx>aso rexr rexx rexb</pfx> <opc>0f 0f /3dnow=bf</opc> <opr>P Q</opr> </def> @@ -6565,22 +6956,22 @@ <instruction> <mnemonic>push</mnemonic> <def> - <opc>06</opc> + <opc>06 /m=!64</opc> <opr>ES</opr> <mode>inv64</mode> </def> <def> - <opc>0e</opc> + <opc>0e /m=!64</opc> <opr>CS</opr> <mode>inv64</mode> </def> <def> - <opc>16</opc> + <opc>16 /m=!64</opc> <opr>SS</opr> <mode>inv64</mode> </def> <def> - <opc>1e</opc> + <opc>1e /m=!64</opc> <opr>DS</opr> <mode>inv64</mode> </def> @@ -6595,56 +6986,56 @@ <def> <pfx>oso rexb</pfx> <opc>50</opc> - <opr>rAXr8</opr> - <mode>def64 depM</mode> + <opr>R0v</opr> + <mode>def64</mode> </def> <def> <pfx>oso rexb</pfx> <opc>51</opc> - <opr>rCXr9</opr> - <mode>def64 depM</mode> + <opr>R1v</opr> + <mode>def64</mode> </def> <def> <pfx>oso rexb</pfx> <opc>52</opc> - <opr>rDXr10</opr> - <mode>def64 depM</mode> + <opr>R2v</opr> + <mode>def64</mode> </def> <def> <pfx>oso rexb</pfx> <opc>53</opc> - <opr>rBXr11</opr> - <mode>def64 depM</mode> + <opr>R3v</opr> + <mode>def64</mode> </def> <def> <pfx>oso rexb</pfx> <opc>54</opc> - <opr>rSPr12</opr> - <mode>def64 depM</mode> + <opr>R4v</opr> + <mode>def64</mode> </def> <def> <pfx>oso rexb</pfx> <opc>55</opc> - <opr>rBPr13</opr> - <mode>def64 depM</mode> + <opr>R5v</opr> + <mode>def64</mode> </def> <def> <pfx>oso rexb</pfx> <opc>56</opc> - <opr>rSIr14</opr> - <mode>def64 depM</mode> + <opr>R6v</opr> + <mode>def64</mode> </def> <def> <pfx>oso rexb</pfx> <opc>57</opc> - <opr>rDIr15</opr> - <mode>def64 depM</mode> + <opr>R7v</opr> + <mode>def64</mode> </def> <def> <pfx>oso</pfx> <opc>68</opc> - <opr>Iz</opr> - <syn>cast</syn> + <opr>sIz</opr> + <mode>def64</mode> </def> <def> <pfx>aso oso rexw rexr rexx rexb</pfx> @@ -6653,9 +7044,10 @@ <mode>def64</mode> </def> <def> + <pfx>oso</pfx> <opc>6a</opc> - <opr>Ib</opr> - <syn>sext</syn> + <opr>sIb</opr> + <mode>def64</mode> </def> </instruction> @@ -6663,7 +7055,7 @@ <mnemonic>pusha</mnemonic> <def> <pfx>oso</pfx> - <opc>60 /o=16</opc> + <opc>60 /o=16 /m=!64</opc> <mode>inv64</mode> </def> </instruction> @@ -6672,7 +7064,7 @@ <mnemonic>pushad</mnemonic> <def> <pfx>oso</pfx> - <opc>60 /o=32</opc> + <opc>60 /o=32 /m=!64</opc> <mode>inv64</mode> </def> </instruction> @@ -6681,13 +7073,7 @@ <mnemonic>pushfw</mnemonic> <def> <pfx>oso</pfx> - <opc>9c /m=32 /o=16</opc> - <mode>def64</mode> - </def> - <def> - <pfx>oso</pfx> - <opc>9c /m=16 /o=16</opc> - <mode>def64</mode> + <opc>9c /m=!64 /o=16</opc> </def> <def> <pfx>oso rexw</pfx> @@ -6700,13 +7086,7 @@ <mnemonic>pushfd</mnemonic> <def> <pfx>oso</pfx> - <opc>9c /m=16 /o=32</opc> - <mode>def64</mode> - </def> - <def> - <pfx>oso</pfx> - <opc>9c /m=32 /o=32</opc> - <mode>def64</mode> + <opc>9c /m=!64 /o=32</opc> </def> </instruction> @@ -6728,8 +7108,9 @@ <mnemonic>pxor</mnemonic> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f ef</opc> - <opr>V W</opr> + <opc>/sse=66 0f ef</opc> + <opr>V H W</opr> + <cpuid>sse2 avx</cpuid> </def> <def> <pfx>aso rexr rexx rexb</pfx> @@ -6759,13 +7140,11 @@ <pfx>aso rexw rexr rexx rexb</pfx> <opc>d2 /reg=2</opc> <opr>Eb CL</opr> - <syn>cast</syn> </def> <def> <pfx>aso oso rexw rexr rexx rexb</pfx> <opc>d3 /reg=2</opc> <opr>Ev CL</opr> - <syn>cast</syn> </def> <def> <pfx>aso oso rexw rexr rexx rexb</pfx> @@ -6800,13 +7179,11 @@ <pfx>aso rexw rexr rexx rexb</pfx> <opc>d2 /reg=3</opc> <opr>Eb CL</opr> - <syn>cast</syn> </def> <def> <pfx>aso oso rexw rexr rexx rexb</pfx> <opc>d3 /reg=3</opc> <opr>Ev CL</opr> - <syn>cast</syn> </def> </instruction> @@ -6831,13 +7208,11 @@ <pfx>aso rexw rexr rexx rexb</pfx> <opc>d2 /reg=0</opc> <opr>Eb CL</opr> - <syn>cast</syn> </def> <def> <pfx>aso oso rexw rexr rexx rexb</pfx> <opc>d3 /reg=0</opc> <opr>Ev CL</opr> - <syn>cast</syn> </def> <def> <pfx>aso oso rexw rexr rexx rexb</pfx> @@ -6872,22 +7247,21 @@ <pfx>aso rexw rexr rexx rexb</pfx> <opc>d2 /reg=1</opc> <opr>Eb CL</opr> - <syn>cast</syn> </def> <def> <pfx>aso oso rexw rexr rexx rexb</pfx> <opc>d3 /reg=1</opc> <opr>Ev CL</opr> - <syn>cast</syn> </def> </instruction> <instruction> <mnemonic>rcpps</mnemonic> <def> - <pfx>aso rexr rexx rexb</pfx> + <pfx>aso rexr rexx rexb vexl</pfx> <opc>0f 53</opc> <opr>V W</opr> + <cpuid>sse avx</cpuid> </def> </instruction> @@ -6895,8 +7269,9 @@ <mnemonic>rcpss</mnemonic> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>ssef3 0f 53</opc> + <opc>/sse=f3 0f 53</opc> <opr>V W</opr> + <cpuid>sse avx</cpuid> </def> </instruction> @@ -6975,9 +7350,10 @@ <instruction> <mnemonic>rsqrtps</mnemonic> <def> - <pfx>aso rexr rexx rexb</pfx> + <pfx>aso rexr rexx rexb vexl</pfx> <opc>0f 52</opc> <opr>V W</opr> + <cpuid>sse avx</cpuid> </def> </instruction> @@ -6985,8 +7361,9 @@ <mnemonic>rsqrtss</mnemonic> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>ssef3 0f 52</opc> + <opc>/sse=f3 0f 52</opc> <opr>V W</opr> + <cpuid>sse avx</cpuid> </def> </instruction> @@ -7004,7 +7381,7 @@ <instruction> <mnemonic>salc</mnemonic> <def> - <opc>d6</opc> + <opc>d6 /m=!64</opc> <mode>inv64</mode> </def> </instruction> @@ -7035,13 +7412,11 @@ <pfx>aso rexw rexr rexx rexb</pfx> <opc>d2 /reg=7</opc> <opr>Eb CL</opr> - <syn>cast</syn> </def> <def> <pfx>aso oso rexw rexr rexx rexb</pfx> <opc>d3 /reg=7</opc> <opr>Ev CL</opr> - <syn>cast</syn> </def> </instruction> @@ -7066,13 +7441,11 @@ <pfx>aso rexw rexr rexx rexb</pfx> <opc>d2 /reg=6</opc> <opr>Eb CL</opr> - <syn>cast</syn> </def> <def> <pfx>aso oso rexw rexr rexx rexb</pfx> <opc>d3 /reg=6</opc> <opr>Ev CL</opr> - <syn>cast</syn> </def> <def> <pfx>aso oso rexw rexr rexx rexb</pfx> @@ -7083,7 +7456,6 @@ <pfx>aso rexr rexx rexb</pfx> <opc>d2 /reg=4</opc> <opr>Eb CL</opr> - <syn>cast</syn> </def> <def> <pfx>aso oso rexw rexr rexx rexb</pfx> @@ -7123,7 +7495,6 @@ <pfx>aso rexw rexr rexx rexb</pfx> <opc>d2 /reg=5</opc> <opr>Eb CL</opr> - <syn>cast</syn> </def> <def> <pfx>aso oso rexw rexr rexx rexb</pfx> @@ -7144,7 +7515,6 @@ <pfx>aso oso rexw rexr rexx rexb</pfx> <opc>d3 /reg=5</opc> <opr>Ev CL</opr> - <syn>cast</syn> </def> </instruction> @@ -7177,8 +7547,7 @@ <def> <pfx>oso rexw</pfx> <opc>1d</opc> - <opr>rAX Iz</opr> - <syn>sext</syn> + <opr>rAX sIz</opr> </def> <def> <pfx>aso rexr rexx rexb</pfx> @@ -7188,26 +7557,25 @@ <def> <pfx>aso oso rexw rexr rexx rexb</pfx> <opc>81 /reg=3</opc> - <opr>Ev Iz</opr> - <syn>sext</syn> + <opr>Ev sIz</opr> </def> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>82 /reg=3</opc> + <opc>82 /reg=3 /m=!64</opc> <opr>Eb Ib</opr> <mode>inv64</mode> </def> <def> <pfx>aso oso rexw rexr rexx rexb</pfx> <opc>83 /reg=3</opc> - <opr>Ev Ib</opr> - <syn>sext</syn> + <opr>Ev sIb</opr> </def> </instruction> <instruction> <mnemonic>scasb</mnemonic> <def> + <pfx>repz</pfx> <opc>ae</opc> </def> </instruction> @@ -7215,7 +7583,7 @@ <instruction> <mnemonic>scasw</mnemonic> <def> - <pfx>oso rexw</pfx> + <pfx>repz oso rexw</pfx> <opc>af /o=16</opc> </def> </instruction> @@ -7223,7 +7591,7 @@ <instruction> <mnemonic>scasd</mnemonic> <def> - <pfx>oso rexw</pfx> + <pfx>repz oso rexw</pfx> <opc>af /o=32</opc> </def> </instruction> @@ -7231,7 +7599,7 @@ <instruction> <mnemonic>scasq</mnemonic> <def> - <pfx>oso rexw</pfx> + <pfx>repz oso rexw</pfx> <opc>af /o=64</opc> </def> </instruction> @@ -7264,7 +7632,7 @@ </instruction> <instruction> - <mnemonic>setnb</mnemonic> + <mnemonic>setae</mnemonic> <def> <pfx>aso rexr rexx rexb</pfx> <opc>0f 93</opc> @@ -7448,9 +7816,10 @@ <instruction> <mnemonic>shufpd</mnemonic> <def> - <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f c6</opc> - <opr>V W Ib</opr> + <pfx>aso rexr rexx rexb vexl</pfx> + <opc>/sse=66 0f c6</opc> + <opr>V H W Ib</opr> + <cpuid>sse2 avx</cpuid> </def> </instruction> @@ -7459,7 +7828,8 @@ <def> <pfx>aso rexr rexx rexb</pfx> <opc>0f c6</opc> - <opr>V W Ib</opr> + <opr>V H W Ib</opr> + <cpuid>sse2 avx</cpuid> </def> </instruction> @@ -7475,7 +7845,7 @@ <instruction> <mnemonic>sldt</mnemonic> <def> - <pfx>aso oso rexr rexx rexb</pfx> + <pfx>aso oso rexr rexw rexx rexb</pfx> <opc>0f 00 /reg=0</opc> <opr>MwRv</opr> </def> @@ -7484,18 +7854,24 @@ <instruction> <mnemonic>smsw</mnemonic> <def> - <pfx>aso rexr rexx rexb</pfx> + <pfx>aso oso rexr rexw rexx rexb</pfx> <opc>0f 01 /reg=4 /mod=!11</opc> - <opr>M</opr> + <opr>MwRv</opr> + </def> + <def> + <pfx>aso oso rexr rexw rexx rexb</pfx> + <opc>0f 01 /reg=4 /mod=11</opc> + <opr>MwRv</opr> </def> </instruction> <instruction> <mnemonic>sqrtps</mnemonic> <def> - <pfx>aso rexr rexx rexb</pfx> + <pfx>aso rexr rexx rexb vexl</pfx> <opc>0f 51</opc> <opr>V W</opr> + <cpuid>sse avx</cpuid> </def> </instruction> @@ -7503,8 +7879,9 @@ <mnemonic>sqrtpd</mnemonic> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 51</opc> + <opc>/sse=66 0f 51</opc> <opr>V W</opr> + <cpuid>sse2 avx</cpuid> </def> </instruction> @@ -7512,8 +7889,9 @@ <mnemonic>sqrtsd</mnemonic> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>ssef2 0f 51</opc> - <opr>V W</opr> + <opc>/sse=f2 0f 51</opc> + <opr>V H W</opr> + <cpuid>sse2 avx</cpuid> </def> </instruction> @@ -7521,8 +7899,9 @@ <mnemonic>sqrtss</mnemonic> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>ssef3 0f 51</opc> - <opr>V W</opr> + <opc>/sse=f3 0f 51</opc> + <opr>V H W</opr> + <cpuid>sse avx</cpuid> </def> </instruction> @@ -7567,15 +7946,16 @@ <mnemonic>stmxcsr</mnemonic> <def> <pfx>aso rexw rexr rexx rexb</pfx> - <opc>0f ae /mod=11 /reg=3</opc> + <opc>0f ae /mod=!11 /reg=3</opc> <opr>Md</opr> + <cpuid>sse avx</cpuid> </def> </instruction> <instruction> <mnemonic>stosb</mnemonic> <def> - <pfx>seg</pfx> + <pfx>rep seg</pfx> <opc>aa</opc> </def> </instruction> @@ -7583,7 +7963,7 @@ <instruction> <mnemonic>stosw</mnemonic> <def> - <pfx>seg oso rexw</pfx> + <pfx>rep seg oso rexw</pfx> <opc>ab /o=16</opc> </def> </instruction> @@ -7591,7 +7971,7 @@ <instruction> <mnemonic>stosd</mnemonic> <def> - <pfx>seg oso rexw</pfx> + <pfx>rep seg oso rexw</pfx> <opc>ab /o=32</opc> </def> </instruction> @@ -7599,7 +7979,7 @@ <instruction> <mnemonic>stosq</mnemonic> <def> - <pfx>seg oso rexw</pfx> + <pfx>rep seg oso rexw</pfx> <opc>ab /o=64</opc> </def> </instruction> @@ -7607,9 +7987,9 @@ <instruction> <mnemonic>str</mnemonic> <def> - <pfx>aso oso rexr rexx rexb</pfx> + <pfx>aso oso rexr rexw rexx rexb</pfx> <opc>0f 00 /reg=1</opc> - <opr>Ev</opr> + <opr>MwRv</opr> </def> </instruction> @@ -7642,8 +8022,7 @@ <def> <pfx>oso rexw</pfx> <opc>2d</opc> - <opr>rAX Iz</opr> - <syn>sext</syn> + <opr>rAX sIz</opr> </def> <def> <pfx>aso rexr rexx rexb</pfx> @@ -7653,38 +8032,38 @@ <def> <pfx>aso oso rexw rexr rexx rexb</pfx> <opc>81 /reg=5</opc> - <opr>Ev Iz</opr> - <syn>sext</syn> + <opr>Ev sIz</opr> </def> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>82 /reg=5</opc> + <opc>82 /reg=5 /m=!64</opc> <opr>Eb Ib</opr> <mode>inv64</mode> </def> <def> <pfx>aso oso rexw rexr rexx rexb</pfx> <opc>83 /reg=5</opc> - <opr>Ev Ib</opr> - <syn>sext</syn> + <opr>Ev sIb</opr> </def> </instruction> <instruction> <mnemonic>subpd</mnemonic> <def> - <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 5c</opc> - <opr>V W</opr> + <pfx>aso rexr rexx rexb vexl</pfx> + <opc>/sse=66 0f 5c</opc> + <opr>V H W</opr> + <cpuid>sse2 avx</cpuid> </def> </instruction> <instruction> <mnemonic>subps</mnemonic> <def> - <pfx>aso rexr rexx rexb</pfx> + <pfx>aso rexr rexx rexb vexl</pfx> <opc>0f 5c</opc> - <opr>V W</opr> + <opr>V H W</opr> + <cpuid>sse avx</cpuid> </def> </instruction> @@ -7692,8 +8071,9 @@ <mnemonic>subsd</mnemonic> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>ssef2 0f 5c</opc> - <opr>V W</opr> + <opc>/sse=f2 0f 5c</opc> + <opr>V H W</opr> + <cpuid>sse2 avx</cpuid> </def> </instruction> @@ -7701,8 +8081,9 @@ <mnemonic>subss</mnemonic> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>ssef3 0f 5c</opc> - <opr>V W</opr> + <opc>/sse=f3 0f 5c</opc> + <opr>V H W</opr> + <cpuid>sse avx</cpuid> </def> </instruction> @@ -7723,15 +8104,22 @@ <instruction> <mnemonic>sysenter</mnemonic> <def> - <opc>0f 34</opc> - <mode>inv64</mode> + <opc>0f 34 /m=!64</opc> + </def> + <def> + <opc>0f 34 /m=64</opc> + <vendor>intel</vendor> </def> </instruction> <instruction> <mnemonic>sysexit</mnemonic> <def> - <opc>0f 35</opc> + <opc>0f 35 /m=!64</opc> + </def> + <def> + <opc>0f 35 /m=64</opc> + <vendor>intel</vendor> </def> </instruction> @@ -7766,8 +8154,7 @@ <def> <pfx>oso rexw</pfx> <opc>a9</opc> - <opr>rAX Iz</opr> - <syn>sext</syn> + <opr>rAX sIz</opr> </def> <def> <pfx>aso rexw rexr rexx rexb</pfx> @@ -7777,14 +8164,12 @@ <def> <pfx>aso oso rexw rexr rexx rexb</pfx> <opc>f7 /reg=0</opc> - <opr>Ev Iz</opr> - <syn>sext</syn> + <opr>Ev sIz</opr> </def> <def> <pfx>aso oso rexw rexr rexx rexb</pfx> <opc>f7 /reg=1</opc> <opr>Ev Iz</opr> - <syn>sext</syn> </def> </instruction> @@ -7792,8 +8177,9 @@ <mnemonic>ucomisd</mnemonic> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 2e</opc> + <opc>/sse=66 0f 2e</opc> <opr>V W</opr> + <cpuid>sse2 avx</cpuid> </def> </instruction> @@ -7803,6 +8189,7 @@ <pfx>aso rexr rexx rexb</pfx> <opc>0f 2e</opc> <opr>V W</opr> + <cpuid>sse avx</cpuid> </def> </instruction> @@ -7816,9 +8203,10 @@ <instruction> <mnemonic>unpckhpd</mnemonic> <def> - <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 15</opc> - <opr>V W</opr> + <pfx>aso rexr rexx rexb vexl</pfx> + <opc>/sse=66 0f 15</opc> + <opr>V H W</opr> + <cpuid>sse2 avx</cpuid> </def> </instruction> @@ -7827,7 +8215,8 @@ <def> <pfx>aso rexr rexx rexb</pfx> <opc>0f 15</opc> - <opr>V W</opr> + <opr>V H W</opr> + <cpuid>sse avx</cpuid> </def> </instruction> @@ -7836,16 +8225,18 @@ <def> <pfx>aso rexr rexx rexb</pfx> <opc>0f 14</opc> - <opr>V W</opr> + <opr>V H W</opr> + <cpuid>sse avx</cpuid> </def> </instruction> <instruction> <mnemonic>unpcklpd</mnemonic> <def> - <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 14</opc> - <opr>V W</opr> + <pfx>aso rexr rexx rexb vexl</pfx> + <opc>/sse=66 0f 14</opc> + <opr>V H W</opr> + <cpuid>sse2 avx</cpuid> </def> </instruction> @@ -7876,11 +8267,21 @@ </instruction> <instruction> + <mnemonic>rdrand</mnemonic> + <def> + <pfx>oso rexr rexw rexx rexb</pfx> + <opc>0f c7 /mod=11 /reg=6</opc> + <opr>R</opr> + </def> + <cpuid>rdrand</cpuid> + </instruction> + + <instruction> <mnemonic>vmclear</mnemonic> <vendor>intel</vendor> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f c7 /reg=6</opc> + <opc>/sse=66 0f c7 /mod=!11 /reg=6</opc> <opr>Mq</opr> </def> </instruction> @@ -7890,7 +8291,7 @@ <vendor>intel</vendor> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>ssef3 0f c7 /reg=6</opc> + <opc>/sse=f3 0f c7 /mod=!11 /reg=6</opc> <opr>Mq</opr> </def> </instruction> @@ -7900,7 +8301,7 @@ <vendor>intel</vendor> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>0f c7 /reg=6</opc> + <opc>0f c7 /mod=!11 /reg=6</opc> <opr>Mq</opr> </def> </instruction> @@ -7910,7 +8311,7 @@ <vendor>intel</vendor> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>0f c7 /reg=7</opc> + <opc>0f c7 /mod=!11 /reg=7</opc> <opr>Mq</opr> </def> </instruction> @@ -7944,20 +8345,8 @@ <vendor>intel</vendor> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>0f 78 /m=16</opc> - <opr>Ed Gd</opr> - <mode>def64</mode> - </def> - <def> - <pfx>aso rexr rexx rexb</pfx> - <opc>0f 78 /m=32</opc> - <opr>Ed Gd</opr> - <mode>def64</mode> - </def> - <def> - <pfx>aso rexr rexx rexb</pfx> - <opc>0f 78 /m=64</opc> - <opr>Eq Gq</opr> + <opc>0f 78</opc> + <opr>Ey Gy</opr> <mode>def64</mode> </def> </instruction> @@ -7967,20 +8356,8 @@ <vendor>intel</vendor> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>0f 79 /m=16</opc> - <opr>Gd Ed</opr> - <mode>def64</mode> - </def> - <def> - <pfx>aso rexr rexx rexb</pfx> - <opc>0f 79 /m=32</opc> - <opr>Gd Ed</opr> - <mode>def64</mode> - </def> - <def> - <pfx>aso rexr rexx rexb</pfx> - <opc>0f 79 /m=64</opc> - <opr>Gq Eq</opr> + <opc>0f 79</opc> + <opr>Gy Ey</opr> <mode>def64</mode> </def> </instruction> @@ -8067,49 +8444,56 @@ <def> <pfx>oso rexw rexb</pfx> <opc>90</opc> - <opr>rAXr8 rAX</opr> + <opr>R0v rAX</opr> </def> <def> <pfx>oso rexw rexb</pfx> <opc>91</opc> - <opr>rCXr9 rAX</opr> + <opr>R1v rAX</opr> </def> <def> <pfx>oso rexw rexb</pfx> <opc>92</opc> - <opr>rDXr10 rAX</opr> + <opr>R2v rAX</opr> </def> <def> <pfx>oso rexw rexb</pfx> <opc>93</opc> - <opr>rBXr11 rAX</opr> + <opr>R3v rAX</opr> </def> <def> <pfx>oso rexw rexb</pfx> <opc>94</opc> - <opr>rSPr12 rAX</opr> + <opr>R4v rAX</opr> </def> <def> <pfx>oso rexw rexb</pfx> <opc>95</opc> - <opr>rBPr13 rAX</opr> + <opr>R5v rAX</opr> </def> <def> <pfx>oso rexw rexb</pfx> <opc>96</opc> - <opr>rSIr14 rAX</opr> + <opr>R6v rAX</opr> </def> <def> <pfx>oso rexw rexb</pfx> <opc>97</opc> - <opr>rDIr15 rAX</opr> + <opr>R7v rAX</opr> </def> </instruction> <instruction> + <mnemonic>xgetbv</mnemonic> + <def> + <opc>0f 01 /mod=11 /reg=2 /rm=0</opc> + </def> + </instruction> + + <instruction> <mnemonic>xlatb</mnemonic> <def> - <pfx>rexw</pfx> + <pfx>rexw seg</pfx> <opc>d7</opc> </def> </instruction> @@ -8143,8 +8527,7 @@ <def> <pfx>oso rexw</pfx> <opc>35</opc> - <opr>rAX Iz</opr> - <syn>sext</syn> + <opr>rAX sIz</opr> </def> <def> <pfx>aso rexr rexx rexb</pfx> @@ -8154,29 +8537,28 @@ <def> <pfx>aso oso rexw rexr rexx rexb</pfx> <opc>81 /reg=6</opc> - <opr>Ev Iz</opr> - <syn>sext</syn> + <opr>Ev sIz</opr> </def> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>82 /reg=6</opc> + <opc>82 /reg=6 /m=!64</opc> <opr>Eb Ib</opr> <mode>inv64</mode> </def> <def> <pfx>aso oso rexw rexr rexx rexb</pfx> <opc>83 /reg=6</opc> - <opr>Ev Ib</opr> - <syn>sext</syn> + <opr>Ev sIb</opr> </def> </instruction> <instruction> <mnemonic>xorpd</mnemonic> <def> - <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 57</opc> - <opr>V W</opr> + <pfx>aso rexr rexx rexb vexl</pfx> + <opc>/sse=66 0f 57</opc> + <opr>V H W</opr> + <cpuid>sse2 avx</cpuid> </def> </instruction> @@ -8185,7 +8567,8 @@ <def> <pfx>aso rexr rexx rexb</pfx> <opc>0f 57</opc> - <opr>V W</opr> + <opr>V H W</opr> + <cpuid>sse2 avx</cpuid> </def> </instruction> @@ -8225,6 +8608,31 @@ </instruction> <instruction> + <mnemonic>xrstor</mnemonic> + <def> + <pfx>aso rexw rexr rexx rexb</pfx> + <opc>0f ae /reg=5 /mod=!11</opc> + <opr>M</opr> + </def> + </instruction> + + <instruction> + <mnemonic>xsave</mnemonic> + <def> + <pfx>aso rexw rexr rexx rexb</pfx> + <opc>0f ae /reg=4 /mod=!11</opc> + <opr>M</opr> + </def> + </instruction> + + <instruction> + <mnemonic>xsetbv</mnemonic> + <def> + <opc>0f 01 /mod=11 /reg=2 /rm=1</opc> + </def> + </instruction> + + <instruction> <mnemonic>xsha1</mnemonic> <def> <opc>0f a6 /mod=11 /rm=0 /reg=1</opc> @@ -8246,7 +8654,25 @@ </instruction> <instruction> - <mnemonic>db</mnemonic> + <mnemonic>pclmulqdq</mnemonic> + <def> + <pfx>aso rexr rexx rexb</pfx> + <opc>/sse=66 0f 3a 44</opc> + <opr>V H W Ib</opr> + <cpuid>aesni avx</cpuid> + </def> + </instruction> + + <!-- + SMX + --> + + <instruction> + <mnemonic>getsec</mnemonic> + <cpuid>smx</cpuid> + <def> + <opc>0f 37</opc> + </def> </instruction> <!-- @@ -8256,46 +8682,58 @@ <instruction> <mnemonic>movdqa</mnemonic> <def> - <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 7f</opc> + <pfx>aso rexr rexx rexb vexl</pfx> + <opc>/sse=66 0f 7f</opc> <opr>W V</opr> </def> <def> - <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 6f</opc> + <pfx>aso rexr rexx rexb vexl</pfx> + <opc>/sse=66 0f 6f</opc> <opr>V W</opr> </def> + <cpuid>sse2 avx</cpuid> + </instruction> + + <instruction> + <mnemonic>maskmovdqu</mnemonic> + <def> + <pfx>aso rexr rexx rexb</pfx> + <opc>/sse=66 0f f7 /mod=11</opc> + <opr>V U</opr> + <cpuid>sse2 avx</cpuid> + </def> </instruction> <instruction> <mnemonic>movdq2q</mnemonic> <def> <pfx>aso rexb</pfx> - <opc>ssef2 0f d6</opc> - <opr>P VR</opr> + <opc>/sse=f2 0f d6</opc> + <opr>P U</opr> </def> </instruction> <instruction> <mnemonic>movdqu</mnemonic> <def> - <pfx>aso rexr rexx rexb</pfx> - <opc>ssef3 0f 6f</opc> + <pfx>aso rexr rexx rexb vexl</pfx> + <opc>/sse=f3 0f 6f</opc> <opr>V W</opr> </def> <def> - <pfx>aso rexr rexx rexb</pfx> - <opc>ssef3 0f 7f</opc> + <pfx>aso rexr rexx rexb vexl</pfx> + <opc>/sse=f3 0f 7f</opc> <opr>W V</opr> </def> + <cpuid>sse2 avx</cpuid> </instruction> <instruction> <mnemonic>movq2dq</mnemonic> <def> - <pfx>aso</pfx> - <opc>ssef3 0f d6</opc> - <opr>V PR</opr> + <pfx>aso rexr</pfx> + <opc>/sse=f3 0f d6</opc> + <opr>V N</opr> </def> </instruction> @@ -8308,8 +8746,9 @@ </def> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f d4</opc> - <opr>V W</opr> + <opc>/sse=66 0f d4</opc> + <opr>V H W</opr> + <cpuid>sse2 avx</cpuid> </def> </instruction> @@ -8317,8 +8756,9 @@ <mnemonic>psubq</mnemonic> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f fb</opc> - <opr>V W</opr> + <opc>/sse=66 0f fb</opc> + <opr>V H W</opr> + <cpuid>sse2 avx</cpuid> </def> <def> <pfx>aso rexr rexx rexb</pfx> @@ -8336,7 +8776,7 @@ </def> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f f4</opc> + <opc>/sse=66 0f f4</opc> <opr>V W</opr> </def> </instruction> @@ -8345,8 +8785,9 @@ <mnemonic>pshufhw</mnemonic> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>ssef3 0f 70</opc> + <opc>/sse=f3 0f 70</opc> <opr>V W Ib</opr> + <cpuid>sse2 avx</cpuid> </def> </instruction> @@ -8354,8 +8795,9 @@ <mnemonic>pshuflw</mnemonic> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>ssef2 0f 70</opc> + <opc>/sse=f2 0f 70</opc> <opr>V W Ib</opr> + <cpuid>sse2 avx</cpuid> </def> </instruction> @@ -8363,8 +8805,9 @@ <mnemonic>pshufd</mnemonic> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 70</opc> + <opc>/sse=66 0f 70</opc> <opr>V W Ib</opr> + <cpuid>sse2 avx</cpuid> </def> </instruction> @@ -8372,8 +8815,9 @@ <mnemonic>pslldq</mnemonic> <def> <pfx>rexb</pfx> - <opc>sse66 0f 73 /reg=7</opc> - <opr>VR Ib</opr> + <opc>/sse=66 0f 73 /reg=7</opc> + <opr>H U Ib</opr> + <cpuid>sse2 avx</cpuid> </def> </instruction> @@ -8381,8 +8825,9 @@ <mnemonic>psrldq</mnemonic> <def> <pfx>rexb</pfx> - <opc>sse66 0f 73 /reg=3</opc> - <opr>VR Ib</opr> + <opc>/sse=66 0f 73 /reg=3</opc> + <opr>H U Ib</opr> + <cpuid>sse2 avx</cpuid> </def> </instruction> @@ -8390,8 +8835,9 @@ <mnemonic>punpckhqdq</mnemonic> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 6d</opc> - <opr>V W</opr> + <opc>/sse=66 0f 6d</opc> + <opr>V H W</opr> + <cpuid>sse2 avx</cpuid> </def> </instruction> @@ -8399,66 +8845,69 @@ <mnemonic>punpcklqdq</mnemonic> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 6c</opc> - <opr>V W</opr> + <opc>/sse=66 0f 6c</opc> + <opr>V H W</opr> + <cpuid>sse2 avx</cpuid> </def> </instruction> - <!-- - SSE 3 - --> - <instruction> - <mnemonic>addsubpd</mnemonic> + <mnemonic>haddpd</mnemonic> <def> - <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f d0</opc> - <opr>V W</opr> + <pfx>aso rexr rexx rexb vexl</pfx> + <opc>/sse=66 0f 7c</opc> + <opr>V H W</opr> + <cpuid>sse3 avx</cpuid> </def> </instruction> <instruction> - <mnemonic>addsubps</mnemonic> + <mnemonic>haddps</mnemonic> <def> - <pfx>aso rexr rexx rexb</pfx> - <opc>ssef2 0f d0</opc> - <opr>V W</opr> + <pfx>aso rexr rexx rexb vexl</pfx> + <opc>/sse=f2 0f 7c</opc> + <opr>V H W</opr> + <cpuid>sse3 avx</cpuid> </def> </instruction> <instruction> - <mnemonic>haddpd</mnemonic> + <mnemonic>hsubpd</mnemonic> <def> - <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 7c</opc> - <opr>V W</opr> + <pfx>aso rexr rexx rexb vexl</pfx> + <opc>/sse=66 0f 7d</opc> + <opr>V H W</opr> + <cpuid>sse3 avx</cpuid> </def> </instruction> <instruction> - <mnemonic>haddps</mnemonic> + <mnemonic>hsubps</mnemonic> <def> - <pfx>aso rexr rexx rexb</pfx> - <opc>ssef2 0f 7c</opc> - <opr>V W</opr> + <pfx>aso rexr rexx rexb vexl</pfx> + <opc>/sse=f2 0f 7d</opc> + <opr>V H W</opr> + <cpuid>sse3 avx</cpuid> </def> </instruction> <instruction> - <mnemonic>hsubpd</mnemonic> + <mnemonic>insertps</mnemonic> <def> - <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 7d</opc> - <opr>V W</opr> + <pfx>aso rexr rexw rexx rexb</pfx> + <opc>/sse=66 0f 3a 21</opc> + <opr>V H Md Ib</opr> + <cpuid>sse4.1 avx</cpuid> </def> </instruction> <instruction> - <mnemonic>hsubps</mnemonic> + <mnemonic>lddqu</mnemonic> <def> - <pfx>aso rexr rexx rexb</pfx> - <opc>ssef2 0f 7d</opc> - <opr>V W</opr> + <pfx>aso rexr rexx rexb vexl</pfx> + <opc>/sse=f2 0f f0</opc> + <opr>V M</opr> + <cpuid>sse3 avx</cpuid> </def> </instruction> @@ -8466,41 +8915,46 @@ <mnemonic>movddup</mnemonic> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>ssef2 0f 12 /mod=11</opc> + <opc>/sse=f2 0f 12 /mod=11</opc> <opr>V W</opr> </def> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>ssef2 0f 12 /mod=!11</opc> + <opc>/sse=f2 0f 12 /mod=!11</opc> <opr>V W</opr> </def> + <cpuid>sse3 avx</cpuid> </instruction> <instruction> <mnemonic>movshdup</mnemonic> <def> - <pfx>aso rexr rexx rexb</pfx> - <opc>ssef3 0f 16 /mod=11</opc> + <pfx>aso rexr rexx rexb vexl</pfx> + <opc>/sse=f3 0f 16 /mod=11</opc> <opr>V W</opr> + <cpuid>sse3 avx</cpuid> </def> <def> - <pfx>aso rexr rexx rexb</pfx> - <opc>ssef3 0f 16 /mod=!11</opc> + <pfx>aso rexr rexx rexb vexl</pfx> + <opc>/sse=f3 0f 16 /mod=!11</opc> <opr>V W</opr> + <cpuid>sse3 avx</cpuid> </def> </instruction> <instruction> <mnemonic>movsldup</mnemonic> <def> - <pfx>aso rexr rexx rexb</pfx> - <opc>ssef3 0f 12 /mod=11</opc> + <pfx>aso rexr rexx rexb vexl</pfx> + <opc>/sse=f3 0f 12 /mod=11</opc> <opr>V W</opr> + <cpuid>sse3 avx</cpuid> </def> <def> - <pfx>aso rexr rexx rexb</pfx> - <opc>ssef3 0f 12 /mod=!11</opc> + <pfx>aso rexr rexx rexb vexl</pfx> + <opc>/sse=f3 0f 12 /mod=!11</opc> <opr>V W</opr> + <cpuid>sse3 avx</cpuid> </def> </instruction> @@ -8514,11 +8968,13 @@ <pfx>aso rexr rexx rexb</pfx> <opc>0f 38 1c</opc> <opr>P Q</opr> + <cpuid>ssse3</cpuid> </def> <def> - <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 38 1c</opc> + <pfx>aso rexr rexx rexb vexl</pfx> + <opc>/sse=66 0f 38 1c</opc> <opr>V W</opr> + <cpuid>ssse3 avx</cpuid> </def> </instruction> @@ -8528,11 +8984,13 @@ <pfx>aso rexr rexx rexb</pfx> <opc>0f 38 1d</opc> <opr>P Q</opr> + <cpuid>ssse3</cpuid> </def> <def> - <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 38 1d</opc> + <pfx>aso rexr rexx rexb vexl</pfx> + <opc>/sse=66 0f 38 1d</opc> <opr>V W</opr> + <cpuid>ssse3 avx</cpuid> </def> </instruction> @@ -8542,16 +9000,18 @@ <pfx>aso rexr rexx rexb</pfx> <opc>0f 38 1e</opc> <opr>P Q</opr> + <cpuid>ssse3</cpuid> </def> <def> - <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 38 1e</opc> + <pfx>aso rexr rexx rexb vexl</pfx> + <opc>/sse=66 0f 38 1e</opc> <opr>V W</opr> + <cpuid>ssse3 avx</cpuid> </def> </instruction> <instruction> - <mnemonic>psignb</mnemonic> + <mnemonic>pshufb</mnemonic> <def> <pfx>aso rexr rexx rexb</pfx> <opc>0f 38 00</opc> @@ -8559,8 +9019,9 @@ </def> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 38 00</opc> - <opr>V W</opr> + <opc>/sse=66 0f 38 00</opc> + <opr>V H W</opr> + <cpuid>ssse3 avx</cpuid> </def> </instruction> @@ -8573,8 +9034,9 @@ </def> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 38 01</opc> - <opr>V W</opr> + <opc>/sse=66 0f 38 01</opc> + <opr>V H W</opr> + <cpuid>ssse3 avx</cpuid> </def> </instruction> @@ -8587,8 +9049,9 @@ </def> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 38 02</opc> - <opr>V W</opr> + <opc>/sse=66 0f 38 02</opc> + <opr>V H W</opr> + <cpuid>ssse3 avx</cpuid> </def> </instruction> @@ -8601,8 +9064,9 @@ </def> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 38 03</opc> - <opr>V W</opr> + <opc>/sse=66 0f 38 03</opc> + <opr>V H W</opr> + <cpuid>ssse3 avx</cpuid> </def> </instruction> @@ -8615,8 +9079,9 @@ </def> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 38 04</opc> - <opr>V W</opr> + <opc>/sse=66 0f 38 04</opc> + <opr>V H W</opr> + <cpuid>ssse3 avx</cpuid> </def> </instruction> @@ -8629,8 +9094,9 @@ </def> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 38 05</opc> - <opr>V W</opr> + <opc>/sse=66 0f 38 05</opc> + <opr>V H W</opr> + <cpuid>ssse3 avx</cpuid> </def> </instruction> @@ -8643,8 +9109,9 @@ </def> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 38 06</opc> - <opr>V W</opr> + <opc>/sse=66 0f 38 06</opc> + <opr>V H W</opr> + <cpuid>ssse3 avx</cpuid> </def> </instruction> @@ -8657,8 +9124,9 @@ </def> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 38 07</opc> - <opr>V W</opr> + <opc>/sse=66 0f 38 07</opc> + <opr>V H W</opr> + <cpuid>ssse3 avx</cpuid> </def> </instruction> @@ -8671,8 +9139,9 @@ </def> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 38 08</opc> - <opr>V W</opr> + <opc>/sse=66 0f 38 08</opc> + <opr>V H W</opr> + <cpuid>ssse3 avx</cpuid> </def> </instruction> @@ -8685,8 +9154,9 @@ </def> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 38 0a</opc> - <opr>V W</opr> + <opc>/sse=66 0f 38 0a</opc> + <opr>V H W</opr> + <cpuid>ssse3 avx</cpuid> </def> </instruction> @@ -8699,8 +9169,9 @@ </def> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 38 09</opc> - <opr>V W</opr> + <opc>/sse=66 0f 38 09</opc> + <opr>V H W</opr> + <cpuid>ssse3 avx</cpuid> </def> </instruction> @@ -8713,8 +9184,9 @@ </def> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 38 0b</opc> - <opr>V W</opr> + <opc>/sse=66 0f 38 0b</opc> + <opr>V H W</opr> + <cpuid>ssse3 avx</cpuid> </def> </instruction> @@ -8727,8 +9199,9 @@ </def> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 3a 0f</opc> - <opr>V W Ib</opr> + <opc>/sse=66 0f 3a 0f</opc> + <opr>V H W Ib</opr> + <cpuid>ssse3 avx</cpuid> </def> </instruction> @@ -8740,8 +9213,9 @@ <mnemonic>pblendvb</mnemonic> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 38 10</opc> + <opc>/sse=66 0f 38 10</opc> <opr>V W</opr> + <cpuid>sse4.1</cpuid> </def> </instruction> @@ -8749,8 +9223,9 @@ <mnemonic>pmuldq</mnemonic> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 38 28</opc> - <opr>V W</opr> + <opc>/sse=66 0f 38 28</opc> + <opr>V H W</opr> + <cpuid>sse4.1 avx</cpuid> </def> </instruction> @@ -8758,8 +9233,9 @@ <mnemonic>pminsb</mnemonic> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 38 38</opc> - <opr>V W</opr> + <opc>/sse=66 0f 38 38</opc> + <opr>V H W</opr> + <cpuid>sse4.1 avx</cpuid> </def> </instruction> @@ -8767,8 +9243,9 @@ <mnemonic>pminsd</mnemonic> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 38 39</opc> - <opr>V W</opr> + <opc>/sse=66 0f 38 39</opc> + <opr>V H W</opr> + <cpuid>sse4.1 avx</cpuid> </def> </instruction> @@ -8776,8 +9253,9 @@ <mnemonic>pminuw</mnemonic> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 38 3a</opc> - <opr>V W</opr> + <opc>/sse=66 0f 38 3a</opc> + <opr>V H W</opr> + <cpuid>sse4.1 avx</cpuid> </def> </instruction> @@ -8785,8 +9263,9 @@ <mnemonic>pminud</mnemonic> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 38 3b</opc> - <opr>V W</opr> + <opc>/sse=66 0f 38 3b</opc> + <opr>V H W</opr> + <cpuid>sse4.1 avx</cpuid> </def> </instruction> @@ -8794,8 +9273,9 @@ <mnemonic>pmaxsb</mnemonic> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 38 3c</opc> - <opr>V W</opr> + <opc>/sse=66 0f 38 3c</opc> + <opr>V H W</opr> + <cpuid>sse4.1 avx</cpuid> </def> </instruction> @@ -8803,8 +9283,9 @@ <mnemonic>pmaxsd</mnemonic> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 38 3d</opc> - <opr>V W</opr> + <opc>/sse=66 0f 38 3d</opc> + <opr>V H W</opr> + <cpuid>sse4.1 avx</cpuid> </def> </instruction> @@ -8812,8 +9293,19 @@ <mnemonic>pmaxud</mnemonic> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 38 3f</opc> - <opr>V W</opr> + <opc>/sse=66 0f 38 3f</opc> + <opr>V H W</opr> + <cpuid>sse4.1 avx</cpuid> + </def> + </instruction> + + <instruction> + <mnemonic>pmaxuw</mnemonic> + <def> + <pfx>aso rexr rexx rexb</pfx> + <opc>/sse=66 0f 38 3e</opc> + <opr>V H W</opr> + <cpuid>sse4.1 avx</cpuid> </def> </instruction> @@ -8821,8 +9313,9 @@ <mnemonic>pmulld</mnemonic> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 38 40</opc> - <opr>V W</opr> + <opc>/sse=66 0f 38 40</opc> + <opr>V H W</opr> + <cpuid>sse4.1 avx</cpuid> </def> </instruction> @@ -8830,26 +9323,29 @@ <mnemonic>phminposuw</mnemonic> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 38 41</opc> + <opc>/sse=66 0f 38 41</opc> <opr>V W</opr> + <cpuid>sse4.1 avx</cpuid> </def> </instruction> <instruction> <mnemonic>roundps</mnemonic> <def> - <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 3a 08</opc> + <pfx>aso rexr rexx rexb vexl</pfx> + <opc>/sse=66 0f 3a 08</opc> <opr>V W Ib</opr> + <cpuid>sse avx</cpuid> </def> </instruction> <instruction> <mnemonic>roundpd</mnemonic> <def> - <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 3a 09</opc> + <pfx>aso rexr rexx rexb vexl</pfx> + <opc>/sse=66 0f 3a 09</opc> <opr>V W Ib</opr> + <cpuid>sse4.1 avx</cpuid> </def> </instruction> @@ -8857,8 +9353,9 @@ <mnemonic>roundss</mnemonic> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 3a 0a</opc> - <opr>V W Ib</opr> + <opc>/sse=66 0f 3a 0a</opc> + <opr>V H W Ib</opr> + <cpuid>sse4.1 avx</cpuid> </def> </instruction> @@ -8866,89 +9363,448 @@ <mnemonic>roundsd</mnemonic> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 3a 0b</opc> - <opr>V W Ib</opr> + <opc>/sse=66 0f 3a 0b</opc> + <opr>V H W Ib</opr> + <cpuid>sse4.1 avx</cpuid> </def> </instruction> <instruction> <mnemonic>blendpd</mnemonic> <def> - <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 3a 0d</opc> - <opr>V W Ib</opr> + <pfx>aso rexr rexx rexb vexl</pfx> + <opc>/sse=66 0f 3a 0d</opc> + <opr>V H W Ib</opr> + <cpuid>sse4.1 avx</cpuid> </def> </instruction> <instruction> - <mnemonic>pblendw</mnemonic> + <mnemonic>blendps</mnemonic> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 3a 0e</opc> - <opr>V W Ib</opr> + <opc>/sse=66 0f 3a 0c</opc> + <opr>V H W Ib</opr> + <cpuid>sse4.1 avx</cpuid> </def> </instruction> <instruction> - <mnemonic>blendps</mnemonic> + <mnemonic>blendvpd</mnemonic> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 3a 0c</opc> - <opr>V W Ib</opr> + <opc>/sse=66 0f 38 15</opc> + <opr>V W</opr> + <cpuid>sse4.1</cpuid> </def> </instruction> <instruction> - <mnemonic>blendvpd</mnemonic> + <mnemonic>blendvps</mnemonic> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 38 15</opc> + <opc>/sse=66 0f 38 14</opc> <opr>V W</opr> + <cpuid>sse4.1</cpuid> </def> </instruction> <instruction> - <mnemonic>blendvps</mnemonic> + <mnemonic>bound</mnemonic> + <def> + <pfx>aso oso</pfx> + <opc>62 /m=!64</opc> + <opr>Gv M</opr> + </def> + </instruction> + + <instruction> + <mnemonic>bsf</mnemonic> + <def> + <pfx>aso oso rexw rexr rexx rexb</pfx> + <opc>0f bc</opc> + <opr>Gv Ev</opr> + </def> + </instruction> + + <instruction> + <mnemonic>bsr</mnemonic> + <def> + <pfx>aso oso rexw rexr rexx rexb</pfx> + <opc>0f bd</opc> + <opr>Gv Ev</opr> + </def> + </instruction> + + <instruction> + <mnemonic>bswap</mnemonic> + <def> + <pfx>oso rexw rexb</pfx> + <opc>0f c8</opc> + <opr>R0y</opr> + </def> + <def> + <pfx>oso rexw rexb</pfx> + <opc>0f c9</opc> + <opr>R1y</opr> + </def> + <def> + <pfx>oso rexw rexb</pfx> + <opc>0f ca</opc> + <opr>R2y</opr> + </def> + <def> + <pfx>oso rexw rexb</pfx> + <opc>0f cb</opc> + <opr>R3y</opr> + </def> + <def> + <pfx>oso rexw rexb</pfx> + <opc>0f cc</opc> + <opr>R4y</opr> + </def> + <def> + <pfx>oso rexw rexb</pfx> + <opc>0f cd</opc> + <opr>R5y</opr> + </def> + <def> + <pfx>oso rexw rexb</pfx> + <opc>0f ce</opc> + <opr>R6y</opr> + </def> + <def> + <pfx>oso rexw rexb</pfx> + <opc>0f cf</opc> + <opr>R7y</opr> + </def> + </instruction> + + <instruction> + <mnemonic>bt</mnemonic> + <def> + <pfx>aso oso rexw rexr rexx rexb</pfx> + <opc>0f ba /reg=4</opc> + <opr>Ev Ib</opr> + </def> + <def> + <pfx>aso oso rexw rexr rexx rexb</pfx> + <opc>0f a3</opc> + <opr>Ev Gv</opr> + </def> + </instruction> + + <instruction> + <mnemonic>btc</mnemonic> + <def> + <pfx>aso oso rexw rexr rexx rexb</pfx> + <opc>0f bb</opc> + <opr>Ev Gv</opr> + </def> + <def> + <pfx>aso oso rexw rexr rexx rexb</pfx> + <opc>0f ba /reg=7</opc> + <opr>Ev Ib</opr> + </def> + </instruction> + + <instruction> + <mnemonic>btr</mnemonic> + <def> + <pfx>aso oso rexw rexr rexx rexb</pfx> + <opc>0f b3</opc> + <opr>Ev Gv</opr> + </def> + <def> + <pfx>aso oso rexw rexr rexx rexb</pfx> + <opc>0f ba /reg=6</opc> + <opr>Ev Ib</opr> + </def> + </instruction> + + <instruction> + <mnemonic>bts</mnemonic> + <def> + <pfx>aso oso rexw rexr rexx rexb</pfx> + <opc>0f ab</opc> + <opr>Ev Gv</opr> + </def> + <def> + <pfx>aso oso rexw rexr rexx rexb</pfx> + <opc>0f ba /reg=5</opc> + <opr>Ev Ib</opr> + </def> + </instruction> + + <instruction> + <mnemonic>pblendw</mnemonic> <def> <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 38 14</opc> + <opc>/sse=66 0f 3a 0e</opc> + <opr>V H W Ib</opr> + <cpuid>sse4.1 avx</cpuid> + </def> + </instruction> + + <instruction> + <mnemonic>mpsadbw</mnemonic> + <def> + <pfx>aso rexr rexx rexb vexl</pfx> + <opc>/sse=66 0f 3a 42</opc> + <opr>V H W Ib</opr> + <cpuid>sse4.1 avx</cpuid> + </def> + </instruction> + + <instruction> + <mnemonic>movntdqa</mnemonic> + <def> + <pfx>aso rexr rexw rexx rexb vexl</pfx> + <opc>/sse=66 0f 38 2a</opc> + <opr>V M</opr> + <cpuid>sse4.1 avx</cpuid> + </def> + </instruction> + + <instruction> + <mnemonic>packusdw</mnemonic> + <def> + <pfx>aso rexr rexw rexx rexb vexl</pfx> + <opc>/sse=66 0f 38 2b</opc> + <opr>V H W</opr> + <cpuid>sse2 avx</cpuid> + </def> + </instruction> + + <instruction> + <mnemonic>pmovsxbw</mnemonic> + <def> + <pfx>aso rexr rexw rexx rexb</pfx> + <opc>/sse=66 0f 38 20</opc> + <opr>V MqU</opr> + <cpuid>sse4.1 avx</cpuid> + </def> + </instruction> + + <instruction> + <mnemonic>pmovsxbd</mnemonic> + <def> + <pfx>aso rexr rexw rexx rexb</pfx> + <opc>/sse=66 0f 38 21</opc> + <opr>V MdU</opr> + <cpuid>sse4.1 avx</cpuid> + </def> + </instruction> + + <instruction> + <mnemonic>pmovsxbq</mnemonic> + <def> + <pfx>aso rexr rexw rexx rexb</pfx> + <opc>/sse=66 0f 38 22</opc> + <opr>V MwU</opr> + <cpuid>sse4.1 avx</cpuid> + </def> + </instruction> + + <instruction> + <mnemonic>pmovsxwd</mnemonic> + <def> + <pfx>aso rexr rexw rexx rexb</pfx> + <opc>/sse=66 0f 38 23</opc> + <opr>V MqU</opr> + <cpuid>sse4.1 avx</cpuid> + </def> + </instruction> + + <instruction> + <mnemonic>pmovsxwq</mnemonic> + <def> + <pfx>aso rexr rexw rexx rexb</pfx> + <opc>/sse=66 0f 38 24</opc> + <opr>V MdU</opr> + <cpuid>sse4.1 avx</cpuid> + </def> + </instruction> + + <instruction> + <mnemonic>pmovsxdq</mnemonic> + <def> + <pfx>aso rexr rexw rexx rexb</pfx> + <opc>/sse=66 0f 38 25</opc> + <opr>V MqU</opr> + <cpuid>sse4.1</cpuid> + </def> + </instruction> + + <instruction> + <mnemonic>pmovzxbw</mnemonic> + <def> + <pfx>aso rexr rexw rexx rexb</pfx> + <opc>/sse=66 0f 38 30</opc> + <opr>V MqU</opr> + <cpuid>sse4.1 avx</cpuid> + </def> + </instruction> + + <instruction> + <mnemonic>pmovzxbd</mnemonic> + <def> + <pfx>aso rexr rexw rexx rexb</pfx> + <opc>/sse=66 0f 38 31</opc> + <opr>V MdU</opr> + <cpuid>sse4.1 avx</cpuid> + </def> + </instruction> + + <instruction> + <mnemonic>pmovzxbq</mnemonic> + <def> + <pfx>aso rexr rexw rexx rexb</pfx> + <opc>/sse=66 0f 38 32</opc> + <opr>V MwU</opr> + <cpuid>sse4.1 avx</cpuid> + </def> + </instruction> + + <instruction> + <mnemonic>pmovzxwd</mnemonic> + <def> + <pfx>aso rexr rexw rexx rexb</pfx> + <opc>/sse=66 0f 38 33</opc> + <opr>V MqU</opr> + <cpuid>sse4.1 avx</cpuid> + </def> + </instruction> + + <instruction> + <mnemonic>pmovzxwq</mnemonic> + <def> + <pfx>aso rexr rexw rexx rexb</pfx> + <opc>/sse=66 0f 38 34</opc> + <opr>V MdU</opr> + <cpuid>sse4.1 avx</cpuid> + </def> + </instruction> + + <instruction> + <mnemonic>pmovzxdq</mnemonic> + <def> + <pfx>aso rexr rexw rexx rexb</pfx> + <opc>/sse=66 0f 38 35</opc> + <opr>V MqU</opr> + <cpuid>sse4.1 avx</cpuid> + </def> + </instruction> + + <instruction> + <mnemonic>pcmpeqq</mnemonic> + <def> + <pfx>aso rexr rexw rexx rexb</pfx> + <opc>/sse=66 0f 38 29</opc> + <opr>V H W</opr> + <cpuid>sse4.1 avx</cpuid> + </def> + </instruction> + + <instruction> + <mnemonic>popcnt</mnemonic> + <def> + <pfx>aso oso rexr rexw rexx rexb</pfx> + <opc>/sse=f3 0f b8</opc> + <opr>Gv Ev</opr> + </def> + <cpuid>sse4.2</cpuid> + </instruction> + + <instruction> + <mnemonic>ptest</mnemonic> + <def> + <pfx>aso rexr rexw rexx rexb vexl</pfx> + <opc>/sse=66 0f 38 17</opc> <opr>V W</opr> + <cpuid>sse4.1 avx</cpuid> </def> </instruction> <instruction> - <mnemonic>dpps</mnemonic> + <mnemonic>pcmpestri</mnemonic> <def> - <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 3a 40</opc> + <pfx>aso rexr rexw rexx rexb</pfx> + <opc>/sse=66 0f 3a 61</opc> <opr>V W Ib</opr> + <cpuid>sse4.2 avx</cpuid> </def> </instruction> <instruction> - <mnemonic>dppd</mnemonic> + <mnemonic>pcmpestrm</mnemonic> <def> - <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 3a 41</opc> + <pfx>aso rexr rexw rexx rexb</pfx> + <opc>/sse=66 0f 3a 60</opc> <opr>V W Ib</opr> + <cpuid>sse4.2 avx</cpuid> </def> </instruction> <instruction> - <mnemonic>mpsadbw</mnemonic> + <mnemonic>pcmpgtq</mnemonic> <def> - <pfx>aso rexr rexx rexb</pfx> - <opc>sse66 0f 3a 42</opc> + <pfx>aso rexr rexw rexx rexb</pfx> + <opc>/sse=66 0f 38 37</opc> + <opr>V H W</opr> + <cpuid>sse4.2 avx</cpuid> + </def> + </instruction> + + <instruction> + <mnemonic>pcmpistri</mnemonic> + <def> + <pfx>aso rexr rexw rexx rexb</pfx> + <opc>/sse=66 0f 3a 63</opc> <opr>V W Ib</opr> + <cpuid>sse4.2 avx</cpuid> </def> </instruction> <instruction> - <mnemonic>extractps</mnemonic> + <mnemonic>pcmpistrm</mnemonic> <def> - <pfx>aso rexr rexw rexb</pfx> - <opc>sse66 0f 3a 17</opc> - <opr>MdRy V Ib</opr> + <pfx>aso rexr rexw rexx rexb</pfx> + <opc>/sse=66 0f 3a 62</opc> + <opr>V W Ib</opr> + <cpuid>sse4.2 avx</cpuid> + </def> + </instruction> + + <instruction> + <mnemonic>movbe</mnemonic> + <def> + <pfx>aso oso rexr rexw rexx rexb</pfx> + <opc>0f 38 f0</opc> + <opr>Gv Mv</opr> + <cpuid>sse3 atom</cpuid> + </def> + <def> + <pfx>aso oso rexr rexw rexx rexb</pfx> + <opc>0f 38 f1</opc> + <opr>Mv Gv</opr> + <cpuid>sse3 atom</cpuid> + </def> + </instruction> + + <instruction> + <mnemonic>crc32</mnemonic> + <def> + <pfx>aso oso rexr rexw rexx rexb</pfx> + <opc>/sse=f2 0f 38 f0</opc> + <opr>Gy Eb</opr> + <cpuid>sse4.2</cpuid> + </def> + <def> + <pfx>aso oso rexr rexw rexx rexb</pfx> + <opc>/sse=f2 0f 38 f1</opc> + <opr>Gy Ev</opr> + <cpuid>sse4.2</cpuid> </def> </instruction> @@ -8956,4 +9812,288 @@ <mnemonic>invalid</mnemonic> </instruction> + <instruction> + <mnemonic>vbroadcastss</mnemonic> + <def> + <pfx>aso rexr rexx rexb vexl</pfx> + <opc>/vex=66_0f38 18 /vexw=0</opc> + <opr>V Md</opr> + <cpuid>avx</cpuid> + </def> + </instruction> + + <instruction> + <mnemonic>vbroadcastsd</mnemonic> + <def> + <pfx>aso rexr rexx rexb vexl</pfx> + <opc>/vex=66_0f38 19 /vexw=0 /vexl=1</opc> + <opr>Vqq Mq</opr> + <cpuid>avx</cpuid> + </def> + </instruction> + + <instruction> + <mnemonic>vextractf128</mnemonic> + <def> + <pfx>aso rexr rexx rexb vexl</pfx> + <opc>/vex=66_0f3a 19 /vexw=0 /vexl=1</opc> + <opr>Wdq Vqq Ib</opr> + <cpuid>avx</cpuid> + </def> + </instruction> + + <instruction> + <mnemonic>vinsertf128</mnemonic> + <def> + <pfx>aso rexr rexx rexb vexl</pfx> + <opc>/vex=66_0f3a 18 /vexw=0 /vexl=1</opc> + <opr>Vqq Hqq Wdq Ib</opr> + <cpuid>avx</cpuid> + </def> + </instruction> + + <instruction> + <mnemonic>vmaskmovps</mnemonic> + <def> + <pfx>aso rexr rexx rexb vexl</pfx> + <opc>/vex=66_0f38 2c /vexw=0</opc> + <opr>V H M</opr> + <cpuid>avx</cpuid> + </def> + <def> + <pfx>aso rexr rexx rexb vexl</pfx> + <opc>/vex=66_0f38 2e /vexw=0</opc> + <opr>M H V</opr> + <cpuid>avx</cpuid> + </def> + </instruction> + + <instruction> + <mnemonic>vmaskmovpd</mnemonic> + <def> + <pfx>aso rexr rexx rexb vexl</pfx> + <opc>/vex=66_0f38 2d /vexw=0</opc> + <opr>V H M</opr> + <cpuid>avx</cpuid> + </def> + <def> + <pfx>aso rexr rexx rexb vexl</pfx> + <opc>/vex=66_0f38 2f /vexw=0</opc> + <opr>M H V</opr> + <cpuid>avx</cpuid> + </def> + </instruction> + + <instruction> + <mnemonic>vpermilpd</mnemonic> + <def> + <pfx>aso rexr rexx rexb vexl</pfx> + <opc>/vex=66_0f38 0d /vexw=0</opc> + <opr>Vx Hx Wx</opr> + <cpuid>avx</cpuid> + </def> + <def> + <pfx>aso rexr rexx rexb vexl</pfx> + <opc>/vex=66_0f3a 05 /vexw=0</opc> + <opr>V W Ib</opr> + <cpuid>avx</cpuid> + </def> + </instruction> + + <instruction> + <mnemonic>vpermilps</mnemonic> + <def> + <pfx>aso rexr rexx rexb vexl</pfx> + <opc>/vex=66_0f38 0c /vexw=0</opc> + <opr>Vx Hx Wx</opr> + <cpuid>avx</cpuid> + </def> + <def> + <pfx>aso rexr rexx rexb vexl</pfx> + <opc>/vex=66_0f3a 04 /vexw=0</opc> + <opr>Vx Wx Ib</opr> + <cpuid>avx</cpuid> + </def> + </instruction> + + <instruction> + <mnemonic>vperm2f128</mnemonic> + <def> + <pfx>aso rexr rexx rexb vexl</pfx> + <opc>/vex=66_0f3a 06 /vexw=0 /vexl=1</opc> + <opr>Vqq Hqq Wqq Ib</opr> + <cpuid>avx</cpuid> + </def> + </instruction> + + <instruction> + <mnemonic>vtestps</mnemonic> + <def> + <pfx>aso rexr rexx rexb vexl</pfx> + <opc>/vex=66_0f38 0e /vexw=0</opc> + <opr>Vx Wx</opr> + <cpuid>avx</cpuid> + </def> + </instruction> + + <instruction> + <mnemonic>vtestpd</mnemonic> + <def> + <pfx>aso rexr rexx rexb vexl</pfx> + <opc>/vex=66_0f38 0f /vexw=0</opc> + <opr>Vx Wx</opr> + <cpuid>avx</cpuid> + </def> + </instruction> + + <instruction> + <mnemonic>vzeroupper</mnemonic> + <def> + <opc>/vex=0f 77 /vexl=0</opc> + <cpuid>avx</cpuid> + </def> + </instruction> + + <instruction> + <mnemonic>vzeroall</mnemonic> + <def> + <opc>/vex=0f 77 /vexl=1</opc> + <cpuid>avx</cpuid> + </def> + </instruction> + + <instruction> + <mnemonic>vblendvpd</mnemonic> + <def> + <pfx>aso rexr rexx rexb vexl</pfx> + <opc>/vex=66_0f3a 4b /vexw=0</opc> + <opr>Vx Hx Wx Lx</opr> + <cpuid>avx</cpuid> + </def> + </instruction> + + <instruction> + <mnemonic>vblendvps</mnemonic> + <def> + <pfx>aso rexr rexx rexb vexl</pfx> + <opc>/vex=66_0f3a 4a /vexw=0</opc> + <opr>Vx Hx Wx Lx</opr> + <cpuid>avx</cpuid> + </def> + </instruction> + + <instruction> + <mnemonic>vmovsd</mnemonic> + <def> + <pfx>aso rexr rexx rexb</pfx> + <opc>/vex=f2_0f 10 /mod=11</opc> + <opr>V H U</opr> + <cpuid>avx</cpuid> + </def> + <def> + <pfx>aso rexr rexx rexb</pfx> + <opc>/vex=f2_0f 10 /mod=!11</opc> + <opr>V Mq</opr> + <cpuid>avx</cpuid> + </def> + <def> + <pfx>aso rexr rexx rexb</pfx> + <opc>/vex=f2_0f 11 /mod=11</opc> + <opr>U H V</opr> + <cpuid>avx</cpuid> + </def> + <def> + <pfx>aso rexr rexx rexb</pfx> + <opc>/vex=f2_0f 11 /mod=!11</opc> + <opr>Mq V</opr> + <cpuid>avx</cpuid> + </def> + </instruction> + + <instruction> + <mnemonic>vmovss</mnemonic> + <def> + <pfx>aso rexr rexx rexb</pfx> + <opc>/vex=f3_0f 10 /mod=11</opc> + <opr>V H U</opr> + <cpuid>avx</cpuid> + </def> + <def> + <pfx>aso rexr rexx rexb</pfx> + <opc>/vex=f3_0f 10 /mod=!11</opc> + <opr>V Md</opr> + <cpuid>avx</cpuid> + </def> + <def> + <pfx>aso rexr rexx rexb</pfx> + <opc>/vex=f3_0f 11 /mod=11</opc> + <opr>U H V</opr> + <cpuid>avx</cpuid> + </def> + <def> + <pfx>aso rexr rexx rexb</pfx> + <opc>/vex=f3_0f 11 /mod=!11</opc> + <opr>Md V</opr> + <cpuid>avx</cpuid> + </def> + </instruction> + + <instruction> + <mnemonic>vpblendvb</mnemonic> + <def> + <pfx>aso rexr rexx rexb</pfx> + <opc>/vex=66_0f3a 4c /vexw=0</opc> + <opr>V H W L</opr> + <cpuid>avx</cpuid> + </def> + </instruction> + + <instruction> + <mnemonic>vpsllw</mnemonic> + <def> + <pfx>aso rexr rexx rexb</pfx> + <opc>/vex=66_0f f1 /vexl=0</opc> + <opr>V H W</opr> + <cpuid>avx</cpuid> + </def> + <def> + <pfx>aso rexr rexx rexb</pfx> + <opc>/vex=66_0f 71 /reg=6 /vexl=0</opc> + <opr>H V W</opr> + <cpuid>avx</cpuid> + </def> + </instruction> + + <instruction> + <mnemonic>vpslld</mnemonic> + <def> + <pfx>aso rexr rexx rexb</pfx> + <opc>/vex=66_0f f2 /vexl=0</opc> + <opr>V H W</opr> + <cpuid>avx</cpuid> + </def> + <def> + <pfx>aso rexr rexx rexb</pfx> + <opc>/vex=66_0f 72 /reg=6 /vexl=0</opc> + <opr>H V W</opr> + <cpuid>avx</cpuid> + </def> + </instruction> + + <instruction> + <mnemonic>vpsllq</mnemonic> + <def> + <pfx>aso rexr rexx rexb</pfx> + <opc>/vex=66_0f f3 /vexl=0</opc> + <opr>V H W</opr> + <cpuid>avx</cpuid> + </def> + <def> + <pfx>aso rexr rexx rexb</pfx> + <opc>/vex=66_0f 73 /reg=6 /vexl=0</opc> + <opr>H V W</opr> + <cpuid>avx</cpuid> + </def> + </instruction> + </x86optable> diff --git a/Source/JavaScriptCore/disassembler/udis86/ud_itab.py b/Source/JavaScriptCore/disassembler/udis86/ud_itab.py new file mode 100644 index 000000000..ef011d2ec --- /dev/null +++ b/Source/JavaScriptCore/disassembler/udis86/ud_itab.py @@ -0,0 +1,379 @@ +# udis86 - scripts/ud_itab.py +# +# Copyright (c) 2009, 2013 Vivek Thampi +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without modification, +# are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +# ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +import os +import sys +from ud_opcode import UdOpcodeTable, UdOpcodeTables, UdInsnDef + +class UdItabGenerator: + + OperandDict = { + "Av" : [ "OP_A" , "SZ_V" ], + "E" : [ "OP_E" , "SZ_NA" ], + "Eb" : [ "OP_E" , "SZ_B" ], + "Ew" : [ "OP_E" , "SZ_W" ], + "Ev" : [ "OP_E" , "SZ_V" ], + "Ed" : [ "OP_E" , "SZ_D" ], + "Ey" : [ "OP_E" , "SZ_Y" ], + "Eq" : [ "OP_E" , "SZ_Q" ], + "Ez" : [ "OP_E" , "SZ_Z" ], + "Fv" : [ "OP_F" , "SZ_V" ], + "G" : [ "OP_G" , "SZ_NA" ], + "Gb" : [ "OP_G" , "SZ_B" ], + "Gw" : [ "OP_G" , "SZ_W" ], + "Gv" : [ "OP_G" , "SZ_V" ], + "Gy" : [ "OP_G" , "SZ_Y" ], + "Gd" : [ "OP_G" , "SZ_D" ], + "Gq" : [ "OP_G" , "SZ_Q" ], + "Gz" : [ "OP_G" , "SZ_Z" ], + "M" : [ "OP_M" , "SZ_NA" ], + "Mb" : [ "OP_M" , "SZ_B" ], + "Mw" : [ "OP_M" , "SZ_W" ], + "Ms" : [ "OP_M" , "SZ_W" ], + "Md" : [ "OP_M" , "SZ_D" ], + "Mq" : [ "OP_M" , "SZ_Q" ], + "Mdq" : [ "OP_M" , "SZ_DQ" ], + "Mv" : [ "OP_M" , "SZ_V" ], + "Mt" : [ "OP_M" , "SZ_T" ], + "Mo" : [ "OP_M" , "SZ_O" ], + "MbRd" : [ "OP_MR" , "SZ_BD" ], + "MbRv" : [ "OP_MR" , "SZ_BV" ], + "MwRv" : [ "OP_MR" , "SZ_WV" ], + "MwRd" : [ "OP_MR" , "SZ_WD" ], + "MwRy" : [ "OP_MR" , "SZ_WY" ], + "MdRy" : [ "OP_MR" , "SZ_DY" ], + "I1" : [ "OP_I1" , "SZ_NA" ], + "I3" : [ "OP_I3" , "SZ_NA" ], + "Ib" : [ "OP_I" , "SZ_B" ], + "Iw" : [ "OP_I" , "SZ_W" ], + "Iv" : [ "OP_I" , "SZ_V" ], + "Iz" : [ "OP_I" , "SZ_Z" ], + "sIb" : [ "OP_sI" , "SZ_B" ], + "sIz" : [ "OP_sI" , "SZ_Z" ], + "sIv" : [ "OP_sI" , "SZ_V" ], + "Jv" : [ "OP_J" , "SZ_V" ], + "Jz" : [ "OP_J" , "SZ_Z" ], + "Jb" : [ "OP_J" , "SZ_B" ], + "R" : [ "OP_R" , "SZ_RDQ" ], + "C" : [ "OP_C" , "SZ_NA" ], + "D" : [ "OP_D" , "SZ_NA" ], + "S" : [ "OP_S" , "SZ_W" ], + "Ob" : [ "OP_O" , "SZ_B" ], + "Ow" : [ "OP_O" , "SZ_W" ], + "Ov" : [ "OP_O" , "SZ_V" ], + "U" : [ "OP_U" , "SZ_O" ], + "Ux" : [ "OP_U" , "SZ_X" ], + "V" : [ "OP_V" , "SZ_DQ" ], + "Vdq" : [ "OP_V" , "SZ_DQ" ], + "Vqq" : [ "OP_V" , "SZ_QQ" ], + "Vsd" : [ "OP_V" , "SZ_Q" ], + "Vx" : [ "OP_V" , "SZ_X" ], + "H" : [ "OP_H" , "SZ_X" ], + "Hx" : [ "OP_H" , "SZ_X" ], + "Hqq" : [ "OP_H" , "SZ_QQ" ], + "W" : [ "OP_W" , "SZ_DQ" ], + "Wdq" : [ "OP_W" , "SZ_DQ" ], + "Wqq" : [ "OP_W" , "SZ_QQ" ], + "Wsd" : [ "OP_W" , "SZ_Q" ], + "Wx" : [ "OP_W" , "SZ_X" ], + "L" : [ "OP_L" , "SZ_O" ], + "Lx" : [ "OP_L" , "SZ_X" ], + "MwU" : [ "OP_MU" , "SZ_WO" ], + "MdU" : [ "OP_MU" , "SZ_DO" ], + "MqU" : [ "OP_MU" , "SZ_QO" ], + "N" : [ "OP_N" , "SZ_Q" ], + "P" : [ "OP_P" , "SZ_Q" ], + "Q" : [ "OP_Q" , "SZ_Q" ], + "AL" : [ "OP_AL" , "SZ_B" ], + "AX" : [ "OP_AX" , "SZ_W" ], + "eAX" : [ "OP_eAX" , "SZ_Z" ], + "rAX" : [ "OP_rAX" , "SZ_V" ], + "CL" : [ "OP_CL" , "SZ_B" ], + "CX" : [ "OP_CX" , "SZ_W" ], + "eCX" : [ "OP_eCX" , "SZ_Z" ], + "rCX" : [ "OP_rCX" , "SZ_V" ], + "DL" : [ "OP_DL" , "SZ_B" ], + "DX" : [ "OP_DX" , "SZ_W" ], + "eDX" : [ "OP_eDX" , "SZ_Z" ], + "rDX" : [ "OP_rDX" , "SZ_V" ], + "R0b" : [ "OP_R0" , "SZ_B" ], + "R1b" : [ "OP_R1" , "SZ_B" ], + "R2b" : [ "OP_R2" , "SZ_B" ], + "R3b" : [ "OP_R3" , "SZ_B" ], + "R4b" : [ "OP_R4" , "SZ_B" ], + "R5b" : [ "OP_R5" , "SZ_B" ], + "R6b" : [ "OP_R6" , "SZ_B" ], + "R7b" : [ "OP_R7" , "SZ_B" ], + "R0w" : [ "OP_R0" , "SZ_W" ], + "R1w" : [ "OP_R1" , "SZ_W" ], + "R2w" : [ "OP_R2" , "SZ_W" ], + "R3w" : [ "OP_R3" , "SZ_W" ], + "R4w" : [ "OP_R4" , "SZ_W" ], + "R5w" : [ "OP_R5" , "SZ_W" ], + "R6w" : [ "OP_R6" , "SZ_W" ], + "R7w" : [ "OP_R7" , "SZ_W" ], + "R0v" : [ "OP_R0" , "SZ_V" ], + "R1v" : [ "OP_R1" , "SZ_V" ], + "R2v" : [ "OP_R2" , "SZ_V" ], + "R3v" : [ "OP_R3" , "SZ_V" ], + "R4v" : [ "OP_R4" , "SZ_V" ], + "R5v" : [ "OP_R5" , "SZ_V" ], + "R6v" : [ "OP_R6" , "SZ_V" ], + "R7v" : [ "OP_R7" , "SZ_V" ], + "R0z" : [ "OP_R0" , "SZ_Z" ], + "R1z" : [ "OP_R1" , "SZ_Z" ], + "R2z" : [ "OP_R2" , "SZ_Z" ], + "R3z" : [ "OP_R3" , "SZ_Z" ], + "R4z" : [ "OP_R4" , "SZ_Z" ], + "R5z" : [ "OP_R5" , "SZ_Z" ], + "R6z" : [ "OP_R6" , "SZ_Z" ], + "R7z" : [ "OP_R7" , "SZ_Z" ], + "R0y" : [ "OP_R0" , "SZ_Y" ], + "R1y" : [ "OP_R1" , "SZ_Y" ], + "R2y" : [ "OP_R2" , "SZ_Y" ], + "R3y" : [ "OP_R3" , "SZ_Y" ], + "R4y" : [ "OP_R4" , "SZ_Y" ], + "R5y" : [ "OP_R5" , "SZ_Y" ], + "R6y" : [ "OP_R6" , "SZ_Y" ], + "R7y" : [ "OP_R7" , "SZ_Y" ], + "ES" : [ "OP_ES" , "SZ_NA" ], + "CS" : [ "OP_CS" , "SZ_NA" ], + "DS" : [ "OP_DS" , "SZ_NA" ], + "SS" : [ "OP_SS" , "SZ_NA" ], + "GS" : [ "OP_GS" , "SZ_NA" ], + "FS" : [ "OP_FS" , "SZ_NA" ], + "ST0" : [ "OP_ST0" , "SZ_NA" ], + "ST1" : [ "OP_ST1" , "SZ_NA" ], + "ST2" : [ "OP_ST2" , "SZ_NA" ], + "ST3" : [ "OP_ST3" , "SZ_NA" ], + "ST4" : [ "OP_ST4" , "SZ_NA" ], + "ST5" : [ "OP_ST5" , "SZ_NA" ], + "ST6" : [ "OP_ST6" , "SZ_NA" ], + "ST7" : [ "OP_ST7" , "SZ_NA" ], + "NONE" : [ "OP_NONE" , "SZ_NA" ], + } + + # + # opcode prefix dictionary + # + PrefixDict = { + "rep" : "P_str", + "repz" : "P_strz", + "aso" : "P_aso", + "oso" : "P_oso", + "rexw" : "P_rexw", + "rexb" : "P_rexb", + "rexx" : "P_rexx", + "rexr" : "P_rexr", + "vexl" : "P_vexl", + "vexw" : "P_vexw", + "seg" : "P_seg", + "inv64" : "P_inv64", + "def64" : "P_def64", + "cast" : "P_cast", + } + + MnemonicAliases = ( "invalid", "3dnow", "none", "db", "pause" ) + + def __init__(self, tables): + self.tables = tables + self._insnIndexMap, i = {}, 0 + for insn in tables.getInsnList(): + self._insnIndexMap[insn], i = i, i + 1 + + self._tableIndexMap, i = {}, 0 + for table in tables.getTableList(): + self._tableIndexMap[table], i = i, i + 1 + + def getInsnIndex(self, insn): + assert isinstance(insn, UdInsnDef) + return self._insnIndexMap[insn] + + def getTableIndex(self, table): + assert isinstance(table, UdOpcodeTable) + return self._tableIndexMap[table] + + def getTableName(self, table): + return "ud_itab__%d" % self.getTableIndex(table) + + def genOpcodeTable(self, table, isGlobal=False): + """Emit Opcode Table in C. + """ + self.ItabC.write( "\n" ); + if not isGlobal: + self.ItabC.write('static ') + self.ItabC.write( "const uint16_t %s[] = {\n" % self.getTableName(table)) + for i in range(table.size()): + if i > 0 and i % 4 == 0: + self.ItabC.write( "\n" ) + if i % 4 == 0: + self.ItabC.write( " /* %2x */" % i) + e = table.entryAt(i) + if e is None: + self.ItabC.write("%12s," % "INVALID") + elif isinstance(e, UdOpcodeTable): + self.ItabC.write("%12s," % ("GROUP(%d)" % self.getTableIndex(e))) + elif isinstance(e, UdInsnDef): + self.ItabC.write("%12s," % self.getInsnIndex(e)) + self.ItabC.write( "\n" ) + self.ItabC.write( "};\n" ) + + + def genOpcodeTables(self): + tables = self.tables.getTableList() + for table in tables: + self.genOpcodeTable(table, table is self.tables.root) + + + def genOpcodeTablesLookupIndex(self): + self.ItabC.write( "\n\n" ); + self.ItabC.write( "struct ud_lookup_table_list_entry ud_lookup_table_list[] = {\n" ) + for table in self.tables.getTableList(): + f0 = self.getTableName(table) + "," + f1 = table.label() + "," + f2 = "\"%s\"" % table.meta() + self.ItabC.write(" /* %03d */ { %s %s %s },\n" % + (self.getTableIndex(table), f0, f1, f2)) + self.ItabC.write( "};" ) + + + def genInsnTable( self ): + self.ItabC.write( "struct ud_itab_entry ud_itab[] = {\n" ); + for insn in self.tables.getInsnList(): + opr_c = [ "O_NONE", "O_NONE", "O_NONE", "O_NONE" ] + pfx_c = [] + opr = insn.operands + for i in range(len(opr)): + if not (opr[i] in self.OperandDict.keys()): + print("error: invalid operand declaration: %s\n" % opr[i]) + opr_c[i] = "O_" + opr[i] + opr = "%s %s %s %s" % (opr_c[0] + ",", opr_c[1] + ",", + opr_c[2] + ",", opr_c[3]) + + for p in insn.prefixes: + if not ( p in self.PrefixDict.keys() ): + print("error: invalid prefix specification: %s \n" % pfx) + pfx_c.append( self.PrefixDict[p] ) + if len(insn.prefixes) == 0: + pfx_c.append( "P_none" ) + pfx = "|".join( pfx_c ) + + self.ItabC.write( " /* %04d */ { UD_I%s %s, %s },\n" \ + % ( self.getInsnIndex(insn), insn.mnemonic + ',', opr, pfx ) ) + self.ItabC.write( "};\n" ) + + + def getMnemonicsList(self): + mnemonics = self.tables.getMnemonicsList() + mnemonics.extend(self.MnemonicAliases) + return mnemonics + + def genMnemonicsList(self): + mnemonics = self.getMnemonicsList() + self.ItabC.write( "\n\n" ); + self.ItabC.write( "const char* ud_mnemonics_str[] = {\n " ) + self.ItabC.write( ",\n ".join( [ "\"%s\"" % m for m in mnemonics ] ) ) + self.ItabC.write( "\n};\n" ) + + + def genItabH( self, filePath ): + self.ItabH = open( filePath, "w" ) + + # Generate Table Type Enumeration + self.ItabH.write( "#ifndef UD_ITAB_H\n" ) + self.ItabH.write( "#define UD_ITAB_H\n\n" ) + + self.ItabH.write("/* itab.h -- generated by udis86:scripts/ud_itab.py, do no edit */\n\n") + + # table type enumeration + self.ItabH.write( "/* ud_table_type -- lookup table types (see decode.c) */\n" ) + self.ItabH.write( "enum ud_table_type {\n " ) + enum = UdOpcodeTable.getLabels() + self.ItabH.write( ",\n ".join( enum ) ) + self.ItabH.write( "\n};\n\n" ); + + # mnemonic enumeration + self.ItabH.write( "/* ud_mnemonic -- mnemonic constants */\n" ) + enum = "enum ud_mnemonic_code {\n " + enum += ",\n ".join( [ "UD_I%s" % m for m in self.getMnemonicsList() ] ) + enum += ",\n UD_MAX_MNEMONIC_CODE" + enum += "\n};\n" + self.ItabH.write( enum ) + self.ItabH.write( "\n" ) + + self.ItabH.write( "extern const char * ud_mnemonics_str[];\n" ) + + self.ItabH.write( "\n#endif /* UD_ITAB_H */\n" ) + + self.ItabH.close() + + + def genItabC(self, filePath): + self.ItabC = open(filePath, "w") + self.ItabC.write("/* itab.c -- generated by udis86:scripts/ud_itab.py, do no edit") + self.ItabC.write(" */\n"); + self.ItabC.write("#include \"udis86_decode.h\"\n\n"); + + self.ItabC.write("#define GROUP(n) (0x8000 | (n))\n") + self.ItabC.write("#define INVALID %d\n\n" % self.getInsnIndex(self.tables.invalidInsn)) + + self.genOpcodeTables() + self.genOpcodeTablesLookupIndex() + + # + # Macros defining short-names for operands + # + self.ItabC.write("\n\n/* itab entry operand definitions (for readability) */\n"); + operands = self.OperandDict.keys() + operands = sorted(operands) + for o in operands: + self.ItabC.write("#define O_%-7s { %-12s %-8s }\n" % + (o, self.OperandDict[o][0] + ",", self.OperandDict[o][1])); + self.ItabC.write("\n"); + + self.genInsnTable() + self.genMnemonicsList() + + self.ItabC.close() + + def genItab( self, location ): + self.genItabC(os.path.join(location, "udis86_itab.c")) + self.genItabH(os.path.join(location, "udis86_itab.h")) + +def usage(): + print("usage: ud_itab.py <optable.xml> <output-path>") + +def main(): + + if len(sys.argv) != 3: + usage() + sys.exit(1) + + tables = UdOpcodeTables(xml=sys.argv[1]) + itab = UdItabGenerator(tables) + itab.genItab(sys.argv[2]) + +if __name__ == '__main__': + main() diff --git a/Source/JavaScriptCore/disassembler/udis86/ud_opcode.py b/Source/JavaScriptCore/disassembler/udis86/ud_opcode.py index f82738062..fe1833dc7 100644 --- a/Source/JavaScriptCore/disassembler/udis86/ud_opcode.py +++ b/Source/JavaScriptCore/disassembler/udis86/ud_opcode.py @@ -1,6 +1,6 @@ # udis86 - scripts/ud_opcode.py # -# Copyright (c) 2009 Vivek Thampi +# Copyright (c) 2009, 2013 Vivek Thampi # All rights reserved. # # Redistribution and use in source and binary forms, with or without modification, @@ -23,213 +23,600 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS # SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -class UdOpcodeTables: - - TableInfo = { - 'opctbl' : { 'name' : 'UD_TAB__OPC_TABLE', 'size' : 256 }, - '/sse' : { 'name' : 'UD_TAB__OPC_SSE', 'size' : 4 }, - '/reg' : { 'name' : 'UD_TAB__OPC_REG', 'size' : 8 }, - '/rm' : { 'name' : 'UD_TAB__OPC_RM', 'size' : 8 }, - '/mod' : { 'name' : 'UD_TAB__OPC_MOD', 'size' : 2 }, - '/m' : { 'name' : 'UD_TAB__OPC_MODE', 'size' : 3 }, - '/x87' : { 'name' : 'UD_TAB__OPC_X87', 'size' : 64 }, - '/a' : { 'name' : 'UD_TAB__OPC_ASIZE', 'size' : 3 }, - '/o' : { 'name' : 'UD_TAB__OPC_OSIZE', 'size' : 3 }, - '/3dnow' : { 'name' : 'UD_TAB__OPC_3DNOW', 'size' : 256 }, - 'vendor' : { 'name' : 'UD_TAB__OPC_VENDOR', 'size' : 3 }, - } +import os + +# Some compatibility stuff for supporting python 2.x as well as python 3.x +def itemslist(dict): + try: + return dict.iteritems() # python 2.x + except AttributeError: + return list(dict.items()) # python 3.x + +class UdInsnDef: + """An x86 instruction definition + """ + def __init__(self, **insnDef): + self.mnemonic = insnDef['mnemonic'] + self.prefixes = insnDef['prefixes'] + self.opcodes = insnDef['opcodes'] + self.operands = insnDef['operands'] + self._cpuid = insnDef['cpuid'] + self._opcexts = {} + + for opc in self.opcodes: + if opc.startswith('/'): + e, v = opc.split('=') + self._opcexts[e] = v + + def lookupPrefix(self, pfx): + """Lookup prefix (if any, None otherwise), by name""" + return True if pfx in self.prefixes else None + + + @property + def vendor(self): + return self._opcexts.get('/vendor', None) + + @property + def mode(self): + return self._opcexts.get('/m', None) + + @property + def osize(self): + return self._opcexts.get('/o', None) + + def isDef64(self): + return 'def64' in self.prefixes + + def __str__(self): + return self.mnemonic + " " + ', '.join(self.operands) + \ + " " + ' '.join(self.opcodes) - OpcodeTable0 = { - 'type' : 'opctbl', - 'entries' : {}, - 'meta' : 'table0' - } - OpcExtIndex = { - - # ssef2, ssef3, sse66 - 'sse': { - 'none' : '00', - 'f2' : '01', - 'f3' : '02', - '66' : '03' - }, - - # /mod= - 'mod': { - '!11' : '00', - '11' : '01' - }, - - # /m=, /o=, /a= - 'mode': { - '16' : '00', - '32' : '01', - '64' : '02' - }, - - 'vendor' : { - 'amd' : '00', - 'intel' : '01', - 'any' : '02' +class UdOpcodeTable: + """A single table of instruction definitions, indexed by + a decode field. + """ + + class CollisionError(Exception): + pass + + class IndexError(Exception): + """Invalid Index Error""" + pass + + @classmethod + def vendor2idx(cls, v): + return (0 if v == 'amd' + else (1 if v == 'intel' + else 2)) + + @classmethod + def vex2idx(cls, v): + if v.startswith("none_"): + v = v[5:] + vexOpcExtMap = { + 'none' : 0x0, + '0f' : 0x1, + '0f38' : 0x2, + '0f3a' : 0x3, + '66' : 0x4, + '66_0f' : 0x5, + '66_0f38' : 0x6, + '66_0f3a' : 0x7, + 'f3' : 0x8, + 'f3_0f' : 0x9, + 'f3_0f38' : 0xa, + 'f3_0f3a' : 0xb, + 'f2' : 0xc, + 'f2_0f' : 0xd, + 'f2_0f38' : 0xe, + 'f2_0f3a' : 0xf, } + return vexOpcExtMap[v] + + + # A mapping of opcode extensions to their representational + # values used in the opcode map. + OpcExtMap = { + '/rm' : lambda v: int(v, 16), + '/x87' : lambda v: int(v, 16), + '/3dnow' : lambda v: int(v, 16), + '/reg' : lambda v: int(v, 16), + # modrm.mod + # (!11, 11) => (00b, 01b) + '/mod' : lambda v: 0 if v == '!11' else 1, + # Mode extensions: + # (16, 32, 64) => (00, 01, 02) + '/o' : lambda v: (int(v) / 32), + '/a' : lambda v: (int(v) / 32), + # Disassembly mode + # (!64, 64) => (00b, 01b) + '/m' : lambda v: 1 if v == '64' else 0, + # SSE + # none => 0 + # f2 => 1 + # f3 => 2 + # 66 => 3 + '/sse' : lambda v: (0 if v == 'none' + else (((int(v, 16) & 0xf) + 1) / 2)), + # AVX + '/vex' : lambda v: UdOpcodeTable.vex2idx(v), + '/vexw' : lambda v: 0 if v == '0' else 1, + '/vexl' : lambda v: 0 if v == '0' else 1, + # Vendor + '/vendor': lambda v: UdOpcodeTable.vendor2idx(v) } - InsnTable = [] - MnemonicsTable = [] - ThreeDNowTable = {} + _TableInfo = { + 'opctbl' : { 'label' : 'UD_TAB__OPC_TABLE', 'size' : 256 }, + '/sse' : { 'label' : 'UD_TAB__OPC_SSE', 'size' : 4 }, + '/reg' : { 'label' : 'UD_TAB__OPC_REG', 'size' : 8 }, + '/rm' : { 'label' : 'UD_TAB__OPC_RM', 'size' : 8 }, + '/mod' : { 'label' : 'UD_TAB__OPC_MOD', 'size' : 2 }, + '/m' : { 'label' : 'UD_TAB__OPC_MODE', 'size' : 2 }, + '/x87' : { 'label' : 'UD_TAB__OPC_X87', 'size' : 64 }, + '/a' : { 'label' : 'UD_TAB__OPC_ASIZE', 'size' : 3 }, + '/o' : { 'label' : 'UD_TAB__OPC_OSIZE', 'size' : 3 }, + '/3dnow' : { 'label' : 'UD_TAB__OPC_3DNOW', 'size' : 256 }, + '/vendor' : { 'label' : 'UD_TAB__OPC_VENDOR', 'size' : 3 }, + '/vex' : { 'label' : 'UD_TAB__OPC_VEX', 'size' : 16 }, + '/vexw' : { 'label' : 'UD_TAB__OPC_VEX_W', 'size' : 2 }, + '/vexl' : { 'label' : 'UD_TAB__OPC_VEX_L', 'size' : 2 }, + } + + + def __init__(self, typ): + assert typ in self._TableInfo + self._typ = typ + self._entries = {} + + + def size(self): + return self._TableInfo[self._typ]['size'] + + def entries(self): + return itemslist(self._entries) - def sizeOfTable( self, t ): - return self.TableInfo[ t ][ 'size' ] + def numEntries(self): + return len(self._entries.keys()) - def nameOfTable( self, t ): - return self.TableInfo[ t ][ 'name' ] + def label(self): + return self._TableInfo[self._typ]['label'] - # - # Updates a table entry: If the entry doesn't exist - # it will create the entry, otherwise, it will walk - # while validating the path. - # - def updateTable( self, table, index, type, meta ): - if not index in table[ 'entries' ]: - table[ 'entries' ][ index ] = { 'type' : type, 'entries' : {}, 'meta' : meta } - if table[ 'entries' ][ index ][ 'type' ] != type: - raise NameError( "error: violation in opcode mapping (overwrite) %s with %s." % - ( table[ 'entries' ][ index ][ 'type' ], type) ) - return table[ 'entries' ][ index ] + def typ(self): + return self._typ - class Insn: - """An abstract type representing an instruction in the opcode map. + def meta(self): + return self._typ + + + def __str__(self): + return "table-%s" % self._typ + + + def add(self, opc, obj): + typ = UdOpcodeTable.getOpcodeTyp(opc) + idx = UdOpcodeTable.getOpcodeIdx(opc) + if self._typ != typ or idx in self._entries: + raise CollisionError() + self._entries[idx] = obj + + + def lookup(self, opc): + typ = UdOpcodeTable.getOpcodeTyp(opc) + idx = UdOpcodeTable.getOpcodeIdx(opc) + if self._typ != typ: + raise UdOpcodeTable.CollisionError("%s <-> %s" % (self._typ, typ)) + return self._entries.get(idx, None) + + + def entryAt(self, index): + """Returns the entry at a given index of the table, + None if there is none. Raises an exception if the + index is out of bounds. """ + if index < self.size(): + return self._entries.get(index, None) + raise self.IndexError("index out of bounds: %s" % index) - # A mapping of opcode extensions to their representational - # values used in the opcode map. - OpcExtMap = { - '/rm' : lambda v: "%02x" % int(v, 16), - '/x87' : lambda v: "%02x" % int(v, 16), - '/3dnow' : lambda v: "%02x" % int(v, 16), - '/reg' : lambda v: "%02x" % int(v, 16), - # modrm.mod - # (!11, 11) => (00, 01) - '/mod' : lambda v: '00' if v == '!11' else '01', - # Mode extensions: - # (16, 32, 64) => (00, 01, 02) - '/o' : lambda v: "%02x" % (int(v) / 32), - '/a' : lambda v: "%02x" % (int(v) / 32), - '/m' : lambda v: "%02x" % (int(v) / 32), - '/sse' : lambda v: UdOpcodeTables.OpcExtIndex['sse'][v] - } + def setEntryAt(self, index, obj): + if index < self.size(): + self._entries[index] = obj + else: + raise self.IndexError("index out of bounds: %s" % index) + + @classmethod + def getOpcodeTyp(cls, opc): + if opc.startswith('/'): + return opc.split('=')[0] + else: + return 'opctbl' + + + @classmethod + def getOpcodeIdx(cls, opc): + if opc.startswith('/'): + typ, v = opc.split('=') + return cls.OpcExtMap[typ](v) + else: + # plain opctbl opcode + return int(opc, 16) + + + @classmethod + def getLabels(cls): + """Returns a list of all labels""" + return [cls._TableInfo[k]['label'] for k in cls._TableInfo.keys()] + + +class UdOpcodeTables(object): + """Collection of opcode tables + """ + + class CollisionError(Exception): + def __init__(self, obj1, obj2): + self.obj1, self.obj2 = obj1, obj2 + + def newTable(self, typ): + """Create a new opcode table of a give type `typ`. """ + tbl = UdOpcodeTable(typ) + self._tables.append(tbl) + return tbl + + def mkTrie(self, opcodes, obj): + """Recursively contruct a trie entry mapping a string of + opcodes to an object. + """ + if len(opcodes) == 0: + return obj + opc = opcodes[0] + tbl = self.newTable(UdOpcodeTable.getOpcodeTyp(opc)) + tbl.add(opc, self.mkTrie(opcodes[1:], obj)) + return tbl + + def walk(self, tbl, opcodes): + """Walk down the opcode trie, starting at a given opcode + table, given a string of opcodes. Return None if unable + to walk, the object at the leaf otherwise. + """ + opc = opcodes[0] + e = tbl.lookup(opc) + if e is None: + return None + elif isinstance(e, UdOpcodeTable) and len(opcodes[1:]): + return self.walk(e, opcodes[1:]) + return e + + def map(self, tbl, opcodes, obj): + """Create a mapping from a given string of opcodes to an + object in the opcode trie. Constructs trie branches as + needed. + """ + opc = opcodes[0] + e = tbl.lookup(opc) + if e is None: + tbl.add(opc, self.mkTrie(opcodes[1:], obj)) + else: + if len(opcodes[1:]) == 0: + raise self.CollisionError(e, obj) + self.map(e, opcodes[1:], obj) + + def __init__(self, xml): + self._tables = [] + self._insns = [] + self._mnemonics = {} - def __init__(self, prefixes, mnemonic, opcodes, operands, vendor): - self.opcodes = opcodes - self.prefixes = prefixes - self.mnemonic = mnemonic - self.operands = operands - self.vendor = vendor - self.opcext = {} - - ssePrefix = None - if self.opcodes[0] in ('ssef2', 'ssef3', 'sse66'): - ssePrefix = self.opcodes[0][3:] - self.opcodes.pop(0) - - # do some preliminary decoding of the instruction type - # 1byte, 2byte or 3byte instruction? - self.nByteInsn = 1 - if self.opcodes[0] == '0f': # 2byte - # 2+ byte opcodes are always disambiguated by an - # sse prefix, unless it is a 3d now instruction - # which is 0f 0f ... - if self.opcodes[1] != '0f' and ssePrefix is None: - ssePrefix = 'none' - if self.opcodes[1] in ('38', '3a'): # 3byte - self.nByteInsn = 3 + # The root table is always a 256 entry opctbl, indexed + # by a plain opcode byte + self.root = self.newTable('opctbl') + + if os.getenv("UD_OPCODE_DEBUG"): + self._logFh = open("opcodeTables.log", "w") + + # add an invalid instruction entry without any mapping + # in the opcode tables. + self.invalidInsn = UdInsnDef(mnemonic="invalid", opcodes=[], cpuid=[], + operands=[], prefixes=[]) + self._insns.append(self.invalidInsn) + + # Construct UdOpcodeTables object from the given + # udis86 optable.xml + for insn in self.__class__.parseOptableXML(xml): + self.addInsnDef(insn) + self.patchAvx2byte() + self.mergeSSENONE() + self.printStats() + + def log(self, s): + if os.getenv("UD_OPCODE_DEBUG"): + self._logFh.write(s + "\n") + + + def mergeSSENONE(self): + """Merge sse tables with only one entry for /sse=none + """ + for table in self._tables: + for k, e in table.entries(): + if isinstance(e, UdOpcodeTable) and e.typ() == '/sse': + if e.numEntries() == 1: + sse = e.lookup("/sse=none") + if sse: + table.setEntryAt(k, sse) + uniqTables = {} + def genTableList(tbl): + if tbl not in uniqTables: + self._tables.append(tbl) + uniqTables[tbl] = 1 + for k, e in tbl.entries(): + if isinstance(e, UdOpcodeTable): + genTableList(e) + self._tables = [] + genTableList(self.root) + + + def patchAvx2byte(self): + # create avx tables + for pp in (None, 'f2', 'f3', '66'): + for m in (None, '0f', '0f38', '0f3a'): + if pp is None and m is None: + continue + if pp is None: + vex = m + elif m is None: + vex = pp else: - self.nByteInsn = 2 - - # The opcode that indexes into the opcode table. - self.opcode = self.opcodes[self.nByteInsn - 1] - - # Record opcode extensions - for opcode in self.opcodes[self.nByteInsn:]: - arg, val = opcode.split('=') - self.opcext[arg] = self.OpcExtMap[arg](val) - - # Record sse extension: the reason sse extension is handled - # separately is that historically sse was handled as a first - # class opcode, not as an extension. Now that sse is handled - # as an extension, we do the manual conversion here, as opposed - # to modifying the opcode xml file. - if ssePrefix is not None: - self.opcext['/sse'] = self.OpcExtMap['/sse'](ssePrefix) - - def parse(self, table, insn): - index = insn.opcodes[0]; - if insn.nByteInsn > 1: - assert index == '0f' - table = self.updateTable(table, index, 'opctbl', '0f') - index = insn.opcodes[1] - - if insn.nByteInsn == 3: - table = self.updateTable(table, index, 'opctbl', index) - index = insn.opcodes[2] - - # Walk down the tree, create levels as needed, for opcode - # extensions. The order is important, and determines how + vex = pp + '_' + m + table = self.walk(self.root, ('c4', '/vex=' + vex)) + self.map(self.root, ('c5', '/vex=' + vex), table) + + + def addInsn(self, **insnDef): + + # Canonicalize opcode list + opcexts = insnDef['opcexts'] + opcodes = list(insnDef['opcodes']) + + # Re-order vex + if '/vex' in opcexts: + assert opcodes[0] == 'c4' or opcodes[0] == 'c5' + opcodes.insert(1, '/vex=' + opcexts['/vex']) + + # Add extensions. The order is important, and determines how # well the opcode table is packed. Also note, /sse must be # before /o, because /sse may consume operand size prefix # affect the outcome of /o. - for ext in ('/mod', '/x87', '/reg', '/rm', '/sse', - '/o', '/a', '/m', '/3dnow'): - if ext in insn.opcext: - table = self.updateTable(table, index, ext, ext) - index = insn.opcext[ext] - - # additional table for disambiguating vendor - if len(insn.vendor): - table = self.updateTable(table, index, 'vendor', insn.vendor) - index = self.OpcExtIndex['vendor'][insn.vendor] - - # make leaf node entries - leaf = self.updateTable(table, index, 'insn', '') - - leaf['mnemonic'] = insn.mnemonic - leaf['prefixes'] = insn.prefixes - leaf['operands'] = insn.operands - - # add instruction to linear table of instruction forms - self.InsnTable.append({ 'prefixes' : insn.prefixes, - 'mnemonic' : insn.mnemonic, - 'operands' : insn.operands }) - - # add mnemonic to mnemonic table - if not insn.mnemonic in self.MnemonicsTable: - self.MnemonicsTable.append(insn.mnemonic) - - - # Adds an instruction definition to the opcode tables - def addInsnDef( self, prefixes, mnemonic, opcodes, operands, vendor ): - insn = self.Insn(prefixes=prefixes, - mnemonic=mnemonic, - opcodes=opcodes, - operands=operands, - vendor=vendor) - self.parse(self.OpcodeTable0, insn) - - def print_table( self, table, pfxs ): - print("%s |" % pfxs) - keys = table[ 'entries' ].keys() - if ( len( keys ) ): - keys.sort() - for idx in keys: - e = table[ 'entries' ][ idx ] - if e[ 'type' ] == 'insn': - print("%s |-<%s>" % ( pfxs, idx )), - print("%s %s" % ( e[ 'mnemonic' ], ' '.join( e[ 'operands'] ))) + for ext in ('/mod', '/x87', '/reg', '/rm', '/sse', '/o', '/a', '/m', + '/vexw', '/vexl', '/3dnow', '/vendor'): + if ext in opcexts: + opcodes.append(ext + '=' + opcexts[ext]) + + insn = UdInsnDef(mnemonic = insnDef['mnemonic'], + prefixes = insnDef['prefixes'], + operands = insnDef['operands'], + opcodes = opcodes, + cpuid = insnDef['cpuid']) + try: + self.map(self.root, opcodes, insn) + except self.CollisionError as e: + self.pprint() + print(opcodes, insn, str(e.obj1), str(e.obj2)) + raise + except Exception as e: + self.pprint() + raise + self._insns.append(insn) + # add to lookup by mnemonic structure + if insn.mnemonic not in self._mnemonics: + self._mnemonics[insn.mnemonic] = [ insn ] + else: + self._mnemonics[insn.mnemonic].append(insn) + + + def addInsnDef(self, insnDef): + opcodes = [] + opcexts = {} + + # pack plain opcodes first, and collect opcode + # extensions + for opc in insnDef['opcodes']: + if not opc.startswith('/'): + opcodes.append(opc) else: - print("%s |-<%s> %s" % ( pfxs, idx, e['type'] )) - self.print_table( e, pfxs + ' |' ) + e, v = opc.split('=') + opcexts[e] = v + + # treat vendor as an opcode extension + if len(insnDef['vendor']): + opcexts['/vendor'] = insnDef['vendor'][0] + + if insnDef['mnemonic'] in ('lds', 'les'): + # + # Massage lds and les, which share the same prefix as AVX + # instructions, to work well with the opcode tree. + # + opcexts['/vex'] = 'none' + elif '/vex' in opcexts: + # A proper avx instruction definition; make sure there are + # no legacy opcode extensions + assert '/sse' not in opcodes + + # make sure the opcode definitions don't already include + # the avx prefixes. + assert opcodes[0] not in ('c4', 'c5') + + # An avx only instruction is defined by the /vex= opcode + # extension. They do not include the c4 (long form) or + # c5 (short form) prefix. As part of opcode table generate, + # here we create the long form definition, and then patch + # the table for c5 in a later stage. + # Construct a long-form definition of the avx instruction + opcodes.insert(0, 'c4') + elif (opcodes[0] == '0f' and opcodes[1] != '0f' and + '/sse' not in opcexts): + # Make all 2-byte opcode form isntructions play nice with sse + # opcode maps. + opcexts['/sse'] = 'none' + + # legacy sse defs that get promoted to avx + fn = self.addInsn + if 'avx' in insnDef['cpuid'] and '/sse' in opcexts: + fn = self.addSSE2AVXInsn + + fn(mnemonic = insnDef['mnemonic'], + prefixes = insnDef['prefixes'], + opcodes = opcodes, + opcexts = opcexts, + operands = insnDef['operands'], + cpuid = insnDef['cpuid']) + + + def addSSE2AVXInsn(self, **insnDef): + """Add an instruction definition containing an avx cpuid bit, but + declared in its legacy SSE form. The function splits the + definition to create two new definitions, one for SSE and one + promoted to an AVX form. + """ + + # SSE + ssemnemonic = insnDef['mnemonic'] + sseopcodes = insnDef['opcodes'] + # remove vex opcode extensions + sseopcexts = dict([(e, v) for e, v in itemslist(insnDef['opcexts']) + if not e.startswith('/vex')]) + # strip out avx operands, preserving relative ordering + # of remaining operands + sseoperands = [opr for opr in insnDef['operands'] + if opr not in ('H', 'L')] + # strip out avx prefixes + sseprefixes = [pfx for pfx in insnDef['prefixes'] + if not pfx.startswith('vex')] + # strip out avx bits from cpuid + ssecpuid = [flag for flag in insnDef['cpuid'] + if not flag.startswith('avx')] + + self.addInsn(mnemonic = ssemnemonic, + prefixes = sseprefixes, + opcodes = sseopcodes, + opcexts = sseopcexts, + operands = sseoperands, + cpuid = ssecpuid) + + # AVX + vexmnemonic = 'v' + insnDef['mnemonic'] + vexprefixes = insnDef['prefixes'] + vexopcodes = ['c4'] + vexopcexts = dict([(e, insnDef['opcexts'][e]) + for e in insnDef['opcexts'] if e != '/sse']) + vexopcexts['/vex'] = insnDef['opcexts']['/sse'] + '_' + '0f' + if insnDef['opcodes'][1] == '38' or insnDef['opcodes'][1] == '3a': + vexopcexts['/vex'] += insnDef['opcodes'][1] + vexopcodes.extend(insnDef['opcodes'][2:]) + else: + vexopcodes.extend(insnDef['opcodes'][1:]) + vexoperands = [] + for o in insnDef['operands']: + # make the operand size explicit: x + if o in ('V', 'W', 'H', 'U'): + o = o + 'x' + vexoperands.append(o) + vexcpuid = [flag for flag in insnDef['cpuid'] + if not flag.startswith('sse')] + + self.addInsn(mnemonic = vexmnemonic, + prefixes = vexprefixes, + opcodes = vexopcodes, + opcexts = vexopcexts, + operands = vexoperands, + cpuid = vexcpuid) + + def getInsnList(self): + """Returns a list of all instructions in the collection""" + return self._insns + + + def getTableList(self): + """Returns a list of all tables in the collection""" + return self._tables + + def getMnemonicsList(self): + """Returns a sorted list of mnemonics""" + return sorted(self._mnemonics.keys()) + + + def pprint(self): + def printWalk(tbl, indent=""): + entries = tbl.entries() + for k, e in entries: + if isinstance(e, UdOpcodeTable): + self.log("%s |-<%02x> %s" % (indent, k, e)) + printWalk(e, indent + " |") + elif isinstance(e, UdInsnDef): + self.log("%s |-<%02x> %s" % (indent, k, e)) + printWalk(self.root) + + + def printStats(self): + tables = self.getTableList() + self.log("stats: ") + self.log(" Num tables = %d" % len(tables)) + self.log(" Num insnDefs = %d" % len(self.getInsnList())) + self.log(" Num insns = %d" % len(self.getMnemonicsList())) + + totalSize = 0 + totalEntries = 0 + for table in tables: + totalSize += table.size() + totalEntries += table.numEntries() + self.log(" Packing Ratio = %d%%" % ((totalEntries * 100) / totalSize)) + self.log("--------------------") + + self.pprint() + + + @staticmethod + def parseOptableXML(xml): + """Parse udis86 optable.xml file and return list of + instruction definitions. + """ + from xml.dom import minidom + + xmlDoc = minidom.parse(xml) + tlNode = xmlDoc.firstChild + insns = [] + + while tlNode and tlNode.localName != "x86optable": + tlNode = tlNode.nextSibling + + for insnNode in tlNode.childNodes: + if not insnNode.localName: + continue + if insnNode.localName != "instruction": + raise Exception("warning: invalid insn node - %s" % insnNode.localName) + mnemonic = insnNode.getElementsByTagName('mnemonic')[0].firstChild.data + vendor, cpuid = '', [] + + for node in insnNode.childNodes: + if node.localName == 'vendor': + vendor = node.firstChild.data.split() + elif node.localName == 'cpuid': + cpuid = node.firstChild.data.split() - def print_tree( self ): - self.print_table( self.OpcodeTable0, '' ) + for node in insnNode.childNodes: + if node.localName == 'def': + insnDef = { 'pfx' : [] } + for node in node.childNodes: + if not node.localName: + continue + if node.localName in ('pfx', 'opc', 'opr', 'vendor', 'cpuid'): + insnDef[node.localName] = node.firstChild.data.split() + elif node.localName == 'mode': + insnDef['pfx'].extend(node.firstChild.data.split()) + insns.append({'prefixes' : insnDef.get('pfx', []), + 'mnemonic' : mnemonic, + 'opcodes' : insnDef.get('opc', []), + 'operands' : insnDef.get('opr', []), + 'vendor' : insnDef.get('vendor', vendor), + 'cpuid' : insnDef.get('cpuid', cpuid)}) + return insns diff --git a/Source/JavaScriptCore/disassembler/udis86/ud_optable.py b/Source/JavaScriptCore/disassembler/udis86/ud_optable.py deleted file mode 100644 index 0350643fd..000000000 --- a/Source/JavaScriptCore/disassembler/udis86/ud_optable.py +++ /dev/null @@ -1,103 +0,0 @@ -# udis86 - scripts/ud_optable.py (optable.xml parser) -# -# Copyright (c) 2009 Vivek Thampi -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without modification, -# are permitted provided that the following conditions are met: -# -# * Redistributions of source code must retain the above copyright notice, -# this list of conditions and the following disclaimer. -# * Redistributions in binary form must reproduce the above copyright notice, -# this list of conditions and the following disclaimer in the documentation -# and/or other materials provided with the distribution. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -# ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -import os -import sys -from xml.dom import minidom - -class UdOptableXmlParser: - - def parseDef( self, node ): - ven = '' - pfx = [] - opc = [] - opr = [] - for def_node in node.childNodes: - if not def_node.localName: - continue - if def_node.localName == 'pfx': - pfx = def_node.firstChild.data.split(); - elif def_node.localName == 'opc': - opc = def_node.firstChild.data.split(); - elif def_node.localName == 'opr': - opr = def_node.firstChild.data.split(); - elif def_node.localName == 'mode': - pfx.extend( def_node.firstChild.data.split() ); - elif def_node.localName == 'syn': - pfx.extend( def_node.firstChild.data.split() ); - elif def_node.localName == 'vendor': - ven = ( def_node.firstChild.data ); - else: - print("warning: invalid node - %s" % def_node.localName) - continue - return ( pfx, opc, opr, ven ) - - def parse( self, xml, fn ): - xmlDoc = minidom.parse( xml ) - self.TlNode = xmlDoc.firstChild - - while self.TlNode and self.TlNode.localName != "x86optable": - self.TlNode = self.TlNode.nextSibling - - for insnNode in self.TlNode.childNodes: - if not insnNode.localName: - continue - if insnNode.localName != "instruction": - print("warning: invalid insn node - %s" % insnNode.localName) - continue - - mnemonic = insnNode.getElementsByTagName( 'mnemonic' )[ 0 ].firstChild.data - vendor = '' - - for node in insnNode.childNodes: - if node.localName == 'vendor': - vendor = node.firstChild.data - elif node.localName == 'def': - ( prefixes, opcodes, operands, local_vendor ) = \ - self.parseDef( node ) - if ( len( local_vendor ) ): - vendor = local_vendor - # callback - fn( prefixes, mnemonic, opcodes, operands, vendor ) - - -def printFn( pfx, mnm, opc, opr, ven ): - print('def: '), - if len( pfx ): - print(' '.join( pfx )), - print("%s %s %s %s" % \ - ( mnm, ' '.join( opc ), ' '.join( opr ), ven )) - - -def parse( xml, callback ): - parser = UdOptableXmlParser() - parser.parse( xml, callback ) - -def main(): - parser = UdOptableXmlParser() - parser.parse( sys.argv[ 1 ], printFn ) - -if __name__ == "__main__": - main() diff --git a/Source/JavaScriptCore/disassembler/udis86/udis86.c b/Source/JavaScriptCore/disassembler/udis86/udis86.c index 264103423..489f9b8ad 100644 --- a/Source/JavaScriptCore/disassembler/udis86/udis86.c +++ b/Source/JavaScriptCore/disassembler/udis86/udis86.c @@ -1,6 +1,6 @@ /* udis86 - libudis86/udis86.c * - * Copyright (c) 2002-2009 Vivek Thampi + * Copyright (c) 2002-2013 Vivek Thampi * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, @@ -28,16 +28,19 @@ #if USE(UDIS86) -#include "udis86_input.h" +#include "udis86_udint.h" #include "udis86_extern.h" +#include "udis86_decode.h" -#ifndef __UD_STANDALONE__ -# include <stdlib.h> -# include <string.h> -#endif /* __UD_STANDALONE__ */ +#if !defined(__UD_STANDALONE__) +#include <string.h> +#endif /* !__UD_STANDALONE__ */ + +static void ud_inp_init(struct ud *u); /* ============================================================================= - * ud_init() - Initializes ud_t object. + * ud_init + * Initializes ud_t object. * ============================================================================= */ extern void @@ -50,30 +53,34 @@ ud_init(struct ud* u) #ifndef __UD_STANDALONE__ ud_set_input_file(u, stdin); #endif /* __UD_STANDALONE__ */ + + ud_set_asm_buffer(u, u->asm_buf_int, sizeof(u->asm_buf_int)); } + /* ============================================================================= - * ud_disassemble() - disassembles one instruction and returns the number of - * bytes disassembled. A zero means end of disassembly. + * ud_disassemble + * Disassembles one instruction and returns the number of + * bytes disassembled. A zero means end of disassembly. * ============================================================================= */ extern unsigned int ud_disassemble(struct ud* u) { - if (ud_input_end(u)) - return 0; - - - u->insn_buffer[0] = u->insn_hexcode[0] = 0; - - - if (ud_decode(u) == 0) - return 0; - if (u->translator) - u->translator(u); - return ud_insn_len(u); + int len; + if (u->inp_end) { + return 0; + } + if ((len = ud_decode(u)) > 0) { + if (u->translator != NULL) { + u->asm_buf[0] = '\0'; + u->translator(u); + } + } + return len; } + /* ============================================================================= * ud_set_mode() - Set Disassemly Mode. * ============================================================================= @@ -82,10 +89,10 @@ extern void ud_set_mode(struct ud* u, uint8_t m) { switch(m) { - case 16: - case 32: - case 64: u->dis_mode = m ; return; - default: u->dis_mode = 16; return; + case 16: + case 32: + case 64: u->dis_mode = m ; return; + default: u->dis_mode = 16; return; } } @@ -97,14 +104,14 @@ extern void ud_set_vendor(struct ud* u, unsigned v) { switch(v) { - case UD_VENDOR_INTEL: - u->vendor = v; - break; - case UD_VENDOR_ANY: - u->vendor = v; - break; - default: - u->vendor = UD_VENDOR_AMD; + case UD_VENDOR_INTEL: + u->vendor = v; + break; + case UD_VENDOR_ANY: + u->vendor = v; + break; + default: + u->vendor = UD_VENDOR_AMD; } } @@ -132,18 +139,18 @@ ud_set_syntax(struct ud* u, void (*t)(struct ud*)) * ud_insn() - returns the disassembled instruction * ============================================================================= */ -extern char* -ud_insn_asm(struct ud* u) +const char* +ud_insn_asm(const struct ud* u) { - return u->insn_buffer; + return u->asm_buf; } /* ============================================================================= * ud_insn_offset() - Returns the offset. * ============================================================================= */ -extern uint64_t -ud_insn_off(struct ud* u) +uint64_t +ud_insn_off(const struct ud* u) { return u->insn_offset; } @@ -153,30 +160,303 @@ ud_insn_off(struct ud* u) * ud_insn_hex() - Returns hex form of disassembled instruction. * ============================================================================= */ -extern char* +const char* ud_insn_hex(struct ud* u) { + u->insn_hexcode[0] = 0; + if (!u->error) { + unsigned int i; + const unsigned char *src_ptr = ud_insn_ptr(u); + char* src_hex = (char*) u->insn_hexcode; + char* const src_hex_base = src_hex; + /* for each byte used to decode instruction */ + for (i = 0; i < ud_insn_len(u) && i < sizeof(u->insn_hexcode) / 2; + ++i, ++src_ptr) { + snprintf(src_hex, sizeof(u->insn_hexcode) - (src_hex - src_hex_base), "%02x", *src_ptr & 0xFF); + src_hex += 2; + } + } return u->insn_hexcode; } + /* ============================================================================= - * ud_insn_ptr() - Returns code disassembled. + * ud_insn_ptr + * Returns a pointer to buffer containing the bytes that were + * disassembled. * ============================================================================= */ -extern uint8_t* -ud_insn_ptr(struct ud* u) +extern const uint8_t* +ud_insn_ptr(const struct ud* u) { - return u->inp_sess; + return (u->inp_buf == NULL) ? + u->inp_sess : u->inp_buf + (u->inp_buf_index - u->inp_ctr); } + /* ============================================================================= - * ud_insn_len() - Returns the count of bytes disassembled. + * ud_insn_len + * Returns the count of bytes disassembled. * ============================================================================= */ extern unsigned int -ud_insn_len(struct ud* u) +ud_insn_len(const struct ud* u) { return u->inp_ctr; } + +/* ============================================================================= + * ud_insn_get_opr + * Return the operand struct representing the nth operand of + * the currently disassembled instruction. Returns NULL if + * there's no such operand. + * ============================================================================= + */ +const struct ud_operand* +ud_insn_opr(const struct ud *u, unsigned int n) +{ + if (n > 3 || u->operand[n].type == UD_NONE) { + return NULL; + } else { + return &u->operand[n]; + } +} + + +/* ============================================================================= + * ud_opr_is_sreg + * Returns non-zero if the given operand is of a segment register type. + * ============================================================================= + */ +int +ud_opr_is_sreg(const struct ud_operand *opr) +{ + return opr->type == UD_OP_REG && + opr->base >= UD_R_ES && + opr->base <= UD_R_GS; +} + + +/* ============================================================================= + * ud_opr_is_sreg + * Returns non-zero if the given operand is of a general purpose + * register type. + * ============================================================================= + */ +int +ud_opr_is_gpr(const struct ud_operand *opr) +{ + return opr->type == UD_OP_REG && + opr->base >= UD_R_AL && + opr->base <= UD_R_R15; +} + + +/* ============================================================================= + * ud_set_user_opaque_data + * ud_get_user_opaque_data + * Get/set user opaqute data pointer + * ============================================================================= + */ +void +ud_set_user_opaque_data(struct ud * u, void* opaque) +{ + u->user_opaque_data = opaque; +} + +void* +ud_get_user_opaque_data(const struct ud *u) +{ + return u->user_opaque_data; +} + + +/* ============================================================================= + * ud_set_asm_buffer + * Allow the user to set an assembler output buffer. If `buf` is NULL, + * we switch back to the internal buffer. + * ============================================================================= + */ +void +ud_set_asm_buffer(struct ud *u, char *buf, size_t size) +{ + if (buf == NULL) { + ud_set_asm_buffer(u, u->asm_buf_int, sizeof(u->asm_buf_int)); + } else { + u->asm_buf = buf; + u->asm_buf_size = size; + } +} + + +/* ============================================================================= + * ud_set_sym_resolver + * Set symbol resolver for relative targets used in the translation + * phase. + * + * The resolver is a function that takes a uint64_t address and returns a + * symbolic name for the that address. The function also takes a second + * argument pointing to an integer that the client can optionally set to a + * non-zero value for offsetted targets. (symbol+offset) The function may + * also return NULL, in which case the translator only prints the target + * address. + * + * The function pointer maybe NULL which resets symbol resolution. + * ============================================================================= + */ +void +ud_set_sym_resolver(struct ud *u, const char* (*resolver)(struct ud*, + uint64_t addr, + int64_t *offset)) +{ + u->sym_resolver = resolver; +} + + +/* ============================================================================= + * ud_insn_mnemonic + * Return the current instruction mnemonic. + * ============================================================================= + */ +enum ud_mnemonic_code +ud_insn_mnemonic(const struct ud *u) +{ + return u->mnemonic; +} + + +/* ============================================================================= + * ud_lookup_mnemonic + * Looks up mnemonic code in the mnemonic string table. + * Returns NULL if the mnemonic code is invalid. + * ============================================================================= + */ +const char* +ud_lookup_mnemonic(enum ud_mnemonic_code c) +{ + if (c < UD_MAX_MNEMONIC_CODE) { + return ud_mnemonics_str[c]; + } else { + return NULL; + } +} + + +/* + * ud_inp_init + * Initializes the input system. + */ +static void +ud_inp_init(struct ud *u) +{ + u->inp_hook = NULL; + u->inp_buf = NULL; + u->inp_buf_size = 0; + u->inp_buf_index = 0; + u->inp_curr = 0; + u->inp_ctr = 0; + u->inp_end = 0; + u->inp_peek = UD_EOI; + UD_NON_STANDALONE(u->inp_file = NULL); +} + + +/* ============================================================================= + * ud_inp_set_hook + * Sets input hook. + * ============================================================================= + */ +void +ud_set_input_hook(register struct ud* u, int (*hook)(struct ud*)) +{ + ud_inp_init(u); + u->inp_hook = hook; +} + +/* ============================================================================= + * ud_inp_set_buffer + * Set buffer as input. + * ============================================================================= + */ +void +ud_set_input_buffer(register struct ud* u, const uint8_t* buf, size_t len) +{ + ud_inp_init(u); + u->inp_buf = buf; + u->inp_buf_size = len; + u->inp_buf_index = 0; +} + + +#ifndef __UD_STANDALONE__ +/* ============================================================================= + * ud_input_set_file + * Set FILE as input. + * ============================================================================= + */ +static int +inp_file_hook(struct ud* u) +{ + return fgetc(u->inp_file); +} + +void +ud_set_input_file(register struct ud* u, FILE* f) +{ + ud_inp_init(u); + u->inp_hook = inp_file_hook; + u->inp_file = f; +} +#endif /* __UD_STANDALONE__ */ + + +/* ============================================================================= + * ud_input_skip + * Skip n input bytes. + * ============================================================================ + */ +void +ud_input_skip(struct ud* u, size_t n) +{ + if (u->inp_end) { + return; + } + if (u->inp_buf == NULL) { + while (n--) { + int c = u->inp_hook(u); + if (c == UD_EOI) { + goto eoi; + } + } + return; + } else { + if (n > u->inp_buf_size || + u->inp_buf_index > u->inp_buf_size - n) { + u->inp_buf_index = u->inp_buf_size; + goto eoi; + } + u->inp_buf_index += n; + return; + } +eoi: + u->inp_end = 1; + UDERR(u, "cannot skip, eoi received\b"); + return; +} + + +/* ============================================================================= + * ud_input_end + * Returns non-zero on end-of-input. + * ============================================================================= + */ +int +ud_input_end(const struct ud *u) +{ + return u->inp_end; +} + #endif // USE(UDIS86) + +/* vim:set ts=2 sw=2 expandtab */ diff --git a/Source/JavaScriptCore/disassembler/udis86/udis86_decode.c b/Source/JavaScriptCore/disassembler/udis86/udis86_decode.c index 579903642..c0ea28362 100644 --- a/Source/JavaScriptCore/disassembler/udis86/udis86_decode.c +++ b/Source/JavaScriptCore/disassembler/udis86/udis86_decode.c @@ -28,14 +28,10 @@ #if USE(UDIS86) -#include "udis86_extern.h" +#include "udis86_udint.h" #include "udis86_types.h" -#include "udis86_input.h" +#include "udis86_extern.h" #include "udis86_decode.h" -#include <wtf/Assertions.h> - -#define dbg(x, n...) -/* #define dbg printf */ #ifndef __UD_STANDALONE__ # include <string.h> @@ -44,15 +40,164 @@ /* The max number of prefixes to an instruction */ #define MAX_PREFIXES 15 -/* instruction aliases and special cases */ -static struct ud_itab_entry s_ie__invalid = - { UD_Iinvalid, O_NONE, O_NONE, O_NONE, P_none }; +/* rex prefix bits */ +#define REX_W(r) ( ( 0xF & ( r ) ) >> 3 ) +#define REX_R(r) ( ( 0x7 & ( r ) ) >> 2 ) +#define REX_X(r) ( ( 0x3 & ( r ) ) >> 1 ) +#define REX_B(r) ( ( 0x1 & ( r ) ) >> 0 ) +#define REX_PFX_MASK(n) ( ( P_REXW(n) << 3 ) | \ + ( P_REXR(n) << 2 ) | \ + ( P_REXX(n) << 1 ) | \ + ( P_REXB(n) << 0 ) ) + +/* scable-index-base bits */ +#define SIB_S(b) ( ( b ) >> 6 ) +#define SIB_I(b) ( ( ( b ) >> 3 ) & 7 ) +#define SIB_B(b) ( ( b ) & 7 ) + +/* modrm bits */ +#define MODRM_REG(b) ( ( ( b ) >> 3 ) & 7 ) +#define MODRM_NNN(b) ( ( ( b ) >> 3 ) & 7 ) +#define MODRM_MOD(b) ( ( ( b ) >> 6 ) & 3 ) +#define MODRM_RM(b) ( ( b ) & 7 ) + +static int decode_ext(struct ud *u, uint16_t ptr); +static int decode_opcode(struct ud *u); + +enum reg_class { /* register classes */ + REGCLASS_GPR, + REGCLASS_MMX, + REGCLASS_CR, + REGCLASS_DB, + REGCLASS_SEG, + REGCLASS_XMM +}; + + /* + * inp_start + * Should be called before each de-code operation. + */ +static void +inp_start(struct ud *u) +{ + u->inp_ctr = 0; +} -static int -decode_ext(struct ud *u, uint16_t ptr); +static uint8_t +inp_peek(struct ud *u) +{ + if (u->inp_end == 0) { + if (u->inp_buf != NULL) { + if (u->inp_buf_index < u->inp_buf_size) { + return u->inp_buf[u->inp_buf_index]; + } + } else if (u->inp_peek != UD_EOI) { + return u->inp_peek; + } else { + int c; + if ((c = u->inp_hook(u)) != UD_EOI) { + u->inp_peek = c; + return u->inp_peek; + } + } + } + u->inp_end = 1; + UDERR(u, "byte expected, eoi received\n"); + return 0; +} + +static uint8_t +inp_next(struct ud *u) +{ + if (u->inp_end == 0) { + if (u->inp_buf != NULL) { + if (u->inp_buf_index < u->inp_buf_size) { + u->inp_ctr++; + return (u->inp_curr = u->inp_buf[u->inp_buf_index++]); + } + } else { + int c = u->inp_peek; + if (c != UD_EOI || (c = u->inp_hook(u)) != UD_EOI) { + u->inp_peek = UD_EOI; + u->inp_curr = c; + u->inp_sess[u->inp_ctr++] = u->inp_curr; + return u->inp_curr; + } + } + } + u->inp_end = 1; + UDERR(u, "byte expected, eoi received\n"); + return 0; +} +static uint8_t +inp_curr(struct ud *u) +{ + return u->inp_curr; +} + + +/* + * inp_uint8 + * int_uint16 + * int_uint32 + * int_uint64 + * Load little-endian values from input + */ +static uint8_t +inp_uint8(struct ud* u) +{ + return inp_next(u); +} + +static uint16_t +inp_uint16(struct ud* u) +{ + uint16_t r, ret; -static inline int + ret = inp_next(u); + r = inp_next(u); + return ret | (r << 8); +} + +static uint32_t +inp_uint32(struct ud* u) +{ + uint32_t r, ret; + + ret = inp_next(u); + r = inp_next(u); + ret = ret | (r << 8); + r = inp_next(u); + ret = ret | (r << 16); + r = inp_next(u); + return ret | (r << 24); +} + +static uint64_t +inp_uint64(struct ud* u) +{ + uint64_t r, ret; + + ret = inp_next(u); + r = inp_next(u); + ret = ret | (r << 8); + r = inp_next(u); + ret = ret | (r << 16); + r = inp_next(u); + ret = ret | (r << 24); + r = inp_next(u); + ret = ret | (r << 32); + r = inp_next(u); + ret = ret | (r << 40); + r = inp_next(u); + ret = ret | (r << 48); + r = inp_next(u); + return ret | (r << 56); +} + + +static UD_INLINE int eff_opr_mode(int dis_mode, int rex_w, int pfx_opr) { if (dis_mode == 64) { @@ -60,13 +205,13 @@ eff_opr_mode(int dis_mode, int rex_w, int pfx_opr) } else if (dis_mode == 32) { return pfx_opr ? 16 : 32; } else { - ASSERT(dis_mode == 16); + UD_ASSERT(dis_mode == 16); return pfx_opr ? 32 : 16; } } -static inline int +static UD_INLINE int eff_adr_mode(int dis_mode, int pfx_adr) { if (dis_mode == 64) { @@ -74,21 +219,12 @@ eff_adr_mode(int dis_mode, int pfx_adr) } else if (dis_mode == 32) { return pfx_adr ? 16 : 32; } else { - ASSERT(dis_mode == 16); + UD_ASSERT(dis_mode == 16); return pfx_adr ? 32 : 16; } } -/* Looks up mnemonic code in the mnemonic string table - * Returns NULL if the mnemonic code is invalid - */ -const char * ud_lookup_mnemonic( enum ud_mnemonic_code c ) -{ - return ud_mnemonics_str[ c ]; -} - - /* * decode_prefixes * @@ -97,164 +233,128 @@ const char * ud_lookup_mnemonic( enum ud_mnemonic_code c ) static int decode_prefixes(struct ud *u) { - unsigned int have_pfx = 1; - unsigned int i; - uint8_t curr; - - /* if in error state, bail out */ - if ( u->error ) - return -1; - - /* keep going as long as there are prefixes available */ - for ( i = 0; have_pfx ; ++i ) { - - /* Get next byte. */ - ud_inp_next(u); - if ( u->error ) - return -1; - curr = ud_inp_curr( u ); - - /* rex prefixes in 64bit mode */ - if ( u->dis_mode == 64 && ( curr & 0xF0 ) == 0x40 ) { - u->pfx_rex = curr; - } else { - switch ( curr ) - { - case 0x2E : - u->pfx_seg = UD_R_CS; - u->pfx_rex = 0; - break; - case 0x36 : - u->pfx_seg = UD_R_SS; - u->pfx_rex = 0; - break; - case 0x3E : - u->pfx_seg = UD_R_DS; - u->pfx_rex = 0; - break; - case 0x26 : - u->pfx_seg = UD_R_ES; - u->pfx_rex = 0; - break; - case 0x64 : - u->pfx_seg = UD_R_FS; - u->pfx_rex = 0; - break; - case 0x65 : - u->pfx_seg = UD_R_GS; - u->pfx_rex = 0; - break; - case 0x67 : /* adress-size override prefix */ - u->pfx_adr = 0x67; - u->pfx_rex = 0; - break; - case 0xF0 : - u->pfx_lock = 0xF0; - u->pfx_rex = 0; - break; - case 0x66: - /* the 0x66 sse prefix is only effective if no other sse prefix - * has already been specified. - */ - if ( !u->pfx_insn ) u->pfx_insn = 0x66; - u->pfx_opr = 0x66; - u->pfx_rex = 0; - break; - case 0xF2: - u->pfx_insn = 0xF2; - u->pfx_repne = 0xF2; - u->pfx_rex = 0; - break; - case 0xF3: - u->pfx_insn = 0xF3; - u->pfx_rep = 0xF3; - u->pfx_repe = 0xF3; - u->pfx_rex = 0; - break; - default : - /* No more prefixes */ - have_pfx = 0; - break; - } - } - - /* check if we reached max instruction length */ - if ( i + 1 == MAX_INSN_LENGTH ) { - u->error = 1; - break; - } + int done = 0; + uint8_t curr = 0, last = 0; + UD_RETURN_ON_ERROR(u); + + do { + last = curr; + curr = inp_next(u); + UD_RETURN_ON_ERROR(u); + if (u->inp_ctr == MAX_INSN_LENGTH) { + UD_RETURN_WITH_ERROR(u, "max instruction length"); + } + + switch (curr) + { + case 0x2E: + u->pfx_seg = UD_R_CS; + break; + case 0x36: + u->pfx_seg = UD_R_SS; + break; + case 0x3E: + u->pfx_seg = UD_R_DS; + break; + case 0x26: + u->pfx_seg = UD_R_ES; + break; + case 0x64: + u->pfx_seg = UD_R_FS; + break; + case 0x65: + u->pfx_seg = UD_R_GS; + break; + case 0x67: /* adress-size override prefix */ + u->pfx_adr = 0x67; + break; + case 0xF0: + u->pfx_lock = 0xF0; + break; + case 0x66: + u->pfx_opr = 0x66; + break; + case 0xF2: + u->pfx_str = 0xf2; + break; + case 0xF3: + u->pfx_str = 0xf3; + break; + default: + /* consume if rex */ + done = (u->dis_mode == 64 && (curr & 0xF0) == 0x40) ? 0 : 1; + break; } + } while (!done); + /* rex prefixes in 64bit mode, must be the last prefix */ + if (u->dis_mode == 64 && (last & 0xF0) == 0x40) { + u->pfx_rex = last; + } + return 0; +} - /* return status */ - if ( u->error ) - return -1; - /* rewind back one byte in stream, since the above loop - * stops with a non-prefix byte. - */ - ud_inp_back(u); - return 0; +/* + * vex_l, vex_w + * Return the vex.L and vex.W bits + */ +static UD_INLINE uint8_t +vex_l(const struct ud *u) +{ + UD_ASSERT(u->vex_op != 0); + return ((u->vex_op == 0xc4 ? u->vex_b2 : u->vex_b1) >> 2) & 1; } +static UD_INLINE uint8_t +vex_w(const struct ud *u) +{ + UD_ASSERT(u->vex_op != 0); + return u->vex_op == 0xc4 ? ((u->vex_b2 >> 7) & 1) : 0; +} -static inline unsigned int modrm( struct ud * u ) + +static UD_INLINE uint8_t +modrm(struct ud * u) { if ( !u->have_modrm ) { - u->modrm = ud_inp_next( u ); + u->modrm = inp_next( u ); + u->modrm_offset = (uint8_t) (u->inp_ctr - 1); u->have_modrm = 1; } return u->modrm; } -static unsigned int resolve_operand_size( const struct ud * u, unsigned int s ) +static unsigned int +resolve_operand_size(const struct ud* u, ud_operand_size_t osize) { - switch ( s ) - { - case SZ_V: - return ( u->opr_mode ); - case SZ_Z: - return ( u->opr_mode == 16 ) ? 16 : 32; - case SZ_P: - return ( u->opr_mode == 16 ) ? SZ_WP : SZ_DP; - case SZ_MDQ: - return ( u->opr_mode == 16 ) ? 32 : u->opr_mode; - case SZ_RDQ: - return ( u->dis_mode == 64 ) ? 64 : 32; - default: - return s; - } + switch (osize) { + case SZ_V: + return u->opr_mode; + case SZ_Z: + return u->opr_mode == 16 ? 16 : 32; + case SZ_Y: + return u->opr_mode == 16 ? 32 : u->opr_mode; + case SZ_RDQ: + return u->dis_mode == 64 ? 64 : 32; + case SZ_X: + UD_ASSERT(u->vex_op != 0); + return (P_VEXL(u->itab_entry->prefix) && vex_l(u)) ? SZ_QQ : SZ_DQ; + default: + return osize; + } } static int resolve_mnemonic( struct ud* u ) { - /* far/near flags */ - u->br_far = 0; - u->br_near = 0; - /* readjust operand sizes for call/jmp instrcutions */ - if ( u->mnemonic == UD_Icall || u->mnemonic == UD_Ijmp ) { - /* WP: 16:16 pointer */ - if ( u->operand[ 0 ].size == SZ_WP ) { - u->operand[ 0 ].size = 16; - u->br_far = 1; - u->br_near= 0; - /* DP: 32:32 pointer */ - } else if ( u->operand[ 0 ].size == SZ_DP ) { - u->operand[ 0 ].size = 32; - u->br_far = 1; - u->br_near= 0; - } else { - u->br_far = 0; - u->br_near= 1; - } /* resolve 3dnow weirdness. */ - } else if ( u->mnemonic == UD_I3dnow ) { - u->mnemonic = ud_itab[ u->le->table[ ud_inp_curr( u ) ] ].mnemonic; + if ( u->mnemonic == UD_I3dnow ) { + u->mnemonic = ud_itab[ u->le->table[ inp_curr( u ) ] ].mnemonic; } /* SWAPGS is only valid in 64bits mode */ if ( u->mnemonic == UD_Iswapgs && u->dis_mode != 64 ) { - u->error = 1; + UDERR(u, "swapgs invalid in 64bits mode\n"); return -1; } @@ -269,8 +369,8 @@ static int resolve_mnemonic( struct ud* u ) } } - if (u->mnemonic == UD_Inop && u->pfx_rep) { - u->pfx_rep = 0; + if (u->mnemonic == UD_Inop && u->pfx_repe) { + u->pfx_repe = 0; u->mnemonic = UD_Ipause; } return 0; @@ -288,14 +388,14 @@ decode_a(struct ud* u, struct ud_operand *op) /* seg16:off16 */ op->type = UD_OP_PTR; op->size = 32; - op->lval.ptr.off = ud_inp_uint16(u); - op->lval.ptr.seg = ud_inp_uint16(u); + op->lval.ptr.off = inp_uint16(u); + op->lval.ptr.seg = inp_uint16(u); } else { /* seg16:off32 */ op->type = UD_OP_PTR; op->size = 48; - op->lval.ptr.off = ud_inp_uint32(u); - op->lval.ptr.seg = ud_inp_uint16(u); + op->lval.ptr.off = inp_uint32(u); + op->lval.ptr.seg = inp_uint16(u); } } @@ -306,15 +406,11 @@ decode_a(struct ud* u, struct ud_operand *op) static enum ud_type decode_gpr(register struct ud* u, unsigned int s, unsigned char rm) { - s = resolve_operand_size(u, s); - switch (s) { case 64: return UD_R_RAX + rm; - case SZ_DP: case 32: return UD_R_EAX + rm; - case SZ_WP: case 16: return UD_R_AX + rm; case 8: @@ -323,94 +419,103 @@ decode_gpr(register struct ud* u, unsigned int s, unsigned char rm) return UD_R_SPL + (rm-4); return UD_R_AL + rm; } else return UD_R_AL + rm; + case 0: + /* invalid size in case of a decode error */ + UD_ASSERT(u->error); + return UD_NONE; default: - return 0; + UD_ASSERT(!"invalid operand size"); + return UD_NONE; } } -/* ----------------------------------------------------------------------------- - * resolve_gpr64() - 64bit General Purpose Register-Selection. - * ----------------------------------------------------------------------------- - */ -static enum ud_type -resolve_gpr64(struct ud* u, enum ud_operand_code gpr_op, enum ud_operand_size * size) -{ - if (gpr_op >= OP_rAXr8 && gpr_op <= OP_rDIr15) - gpr_op = (gpr_op - OP_rAXr8) | (REX_B(u->pfx_rex) << 3); - else gpr_op = (gpr_op - OP_rAX); - - if (u->opr_mode == 16) { - *size = 16; - return gpr_op + UD_R_AX; - } - if (u->dis_mode == 32 || - (u->opr_mode == 32 && ! (REX_W(u->pfx_rex) || u->default64))) { - *size = 32; - return gpr_op + UD_R_EAX; - } - - *size = 64; - return gpr_op + UD_R_RAX; -} - -/* ----------------------------------------------------------------------------- - * resolve_gpr32 () - 32bit General Purpose Register-Selection. - * ----------------------------------------------------------------------------- - */ -static enum ud_type -resolve_gpr32(struct ud* u, enum ud_operand_code gpr_op) -{ - gpr_op = gpr_op - OP_eAX; - - if (u->opr_mode == 16) - return gpr_op + UD_R_AX; - - return gpr_op + UD_R_EAX; -} - -/* ----------------------------------------------------------------------------- - * resolve_reg() - Resolves the register type - * ----------------------------------------------------------------------------- - */ -static enum ud_type -resolve_reg(struct ud* u, unsigned int type, unsigned char i) +static void +decode_reg(struct ud *u, + struct ud_operand *opr, + int type, + int num, + int size) { + int reg; + size = resolve_operand_size(u, size); switch (type) { - case T_MMX : return UD_R_MM0 + (i & 7); - case T_XMM : return UD_R_XMM0 + i; - case T_CRG : return UD_R_CR0 + i; - case T_DBG : return UD_R_DR0 + i; - case T_SEG : { + case REGCLASS_GPR : reg = decode_gpr(u, size, num); break; + case REGCLASS_MMX : reg = UD_R_MM0 + (num & 7); break; + case REGCLASS_XMM : + reg = num + (size == SZ_QQ ? UD_R_YMM0 : UD_R_XMM0); + break; + case REGCLASS_CR : reg = UD_R_CR0 + num; break; + case REGCLASS_DB : reg = UD_R_DR0 + num; break; + case REGCLASS_SEG : { /* * Only 6 segment registers, anything else is an error. */ - if ((i & 7) > 5) { - u->error = 1; + if ((num & 7) > 5) { + UDERR(u, "invalid segment register value\n"); + return; } else { - return UD_R_ES + (i & 7); + reg = UD_R_ES + (num & 7); } + break; } - case T_NONE: - default: return UD_NONE; + default: + UD_ASSERT(!"invalid register type"); + return; } + opr->type = UD_OP_REG; + opr->base = reg; + opr->size = size; } -/* ----------------------------------------------------------------------------- - * decode_imm() - Decodes Immediate values. - * ----------------------------------------------------------------------------- + +/* + * decode_imm + * + * Decode Immediate values. */ static void -decode_imm(struct ud* u, unsigned int s, struct ud_operand *op) +decode_imm(struct ud* u, unsigned int size, struct ud_operand *op) { - op->size = resolve_operand_size(u, s); + op->size = resolve_operand_size(u, size); op->type = UD_OP_IMM; switch (op->size) { - case 8: op->lval.sbyte = ud_inp_uint8(u); break; - case 16: op->lval.uword = ud_inp_uint16(u); break; - case 32: op->lval.udword = ud_inp_uint32(u); break; - case 64: op->lval.uqword = ud_inp_uint64(u); break; - default: return; + case 8: op->lval.sbyte = inp_uint8(u); break; + case 16: op->lval.uword = inp_uint16(u); break; + case 32: op->lval.udword = inp_uint32(u); break; + case 64: op->lval.uqword = inp_uint64(u); break; + default: return; + } +} + + +/* + * decode_mem_disp + * + * Decode mem address displacement. + */ +static void +decode_mem_disp(struct ud* u, unsigned int size, struct ud_operand *op) +{ + switch (size) { + case 8: + op->offset = 8; + op->lval.ubyte = inp_uint8(u); + break; + case 16: + op->offset = 16; + op->lval.uword = inp_uint16(u); + break; + case 32: + op->offset = 32; + op->lval.udword = inp_uint32(u); + break; + case 64: + op->offset = 64; + op->lval.uqword = inp_uint64(u); + break; + default: + return; } } @@ -421,21 +526,14 @@ decode_imm(struct ud* u, unsigned int s, struct ud_operand *op) * Decodes reg field of mod/rm byte * */ -static void +static UD_INLINE void decode_modrm_reg(struct ud *u, struct ud_operand *operand, unsigned int type, unsigned int size) { - uint8_t reg = (REX_R(u->pfx_rex) << 3) | MODRM_REG(modrm(u)); - operand->type = UD_OP_REG; - operand->size = resolve_operand_size(u, size); - - if (type == T_GPR) { - operand->base = decode_gpr(u, operand->size, reg); - } else { - operand->base = resolve_reg(u, type, reg); - } + uint8_t reg = (REX_R(u->_rex) << 3) | MODRM_REG(modrm(u)); + decode_reg(u, operand, type, reg, size); } @@ -448,67 +546,58 @@ decode_modrm_reg(struct ud *u, static void decode_modrm_rm(struct ud *u, struct ud_operand *op, - unsigned char type, - unsigned int size) + unsigned char type, /* register type */ + unsigned int size) /* operand size */ { - unsigned char mod, rm, reg; + size_t offset = 0; + unsigned char mod, rm; /* get mod, r/m and reg fields */ mod = MODRM_MOD(modrm(u)); - rm = (REX_B(u->pfx_rex) << 3) | MODRM_RM(modrm(u)); - reg = (REX_R(u->pfx_rex) << 3) | MODRM_REG(modrm(u)); - - UNUSED_PARAM(reg); - - op->size = resolve_operand_size(u, size); + rm = (REX_B(u->_rex) << 3) | MODRM_RM(modrm(u)); /* * If mod is 11b, then the modrm.rm specifies a register. * */ if (mod == 3) { - op->type = UD_OP_REG; - if (type == T_GPR) { - op->base = decode_gpr(u, op->size, rm); - } else { - op->base = resolve_reg(u, type, (REX_B(u->pfx_rex) << 3) | (rm & 7)); - } + decode_reg(u, op, type, rm, size); return; - } - + } /* - * !11 => Memory Address + * !11b => Memory Address */ op->type = UD_OP_MEM; + op->size = resolve_operand_size(u, size); if (u->adr_mode == 64) { op->base = UD_R_RAX + rm; if (mod == 1) { - op->offset = 8; + offset = 8; } else if (mod == 2) { - op->offset = 32; + offset = 32; } else if (mod == 0 && (rm & 7) == 5) { op->base = UD_R_RIP; - op->offset = 32; + offset = 32; } else { - op->offset = 0; + offset = 0; } /* * Scale-Index-Base (SIB) */ if ((rm & 7) == 4) { - ud_inp_next(u); + inp_next(u); - op->scale = (1 << SIB_S(ud_inp_curr(u))) & ~1; - op->index = UD_R_RAX + (SIB_I(ud_inp_curr(u)) | (REX_X(u->pfx_rex) << 3)); - op->base = UD_R_RAX + (SIB_B(ud_inp_curr(u)) | (REX_B(u->pfx_rex) << 3)); - + op->base = UD_R_RAX + (SIB_B(inp_curr(u)) | (REX_B(u->_rex) << 3)); + op->index = UD_R_RAX + (SIB_I(inp_curr(u)) | (REX_X(u->_rex) << 3)); /* special conditions for base reference */ if (op->index == UD_R_RSP) { op->index = UD_NONE; op->scale = UD_NONE; + } else { + op->scale = (1 << SIB_S(inp_curr(u))) & ~1; } if (op->base == UD_R_RBP || op->base == UD_R_R13) { @@ -516,32 +605,35 @@ decode_modrm_rm(struct ud *u, op->base = UD_NONE; } if (mod == 1) { - op->offset = 8; + offset = 8; } else { - op->offset = 32; + offset = 32; } } + } else { + op->scale = UD_NONE; + op->index = UD_NONE; } } else if (u->adr_mode == 32) { op->base = UD_R_EAX + rm; if (mod == 1) { - op->offset = 8; + offset = 8; } else if (mod == 2) { - op->offset = 32; + offset = 32; } else if (mod == 0 && rm == 5) { op->base = UD_NONE; - op->offset = 32; + offset = 32; } else { - op->offset = 0; + offset = 0; } /* Scale-Index-Base (SIB) */ if ((rm & 7) == 4) { - ud_inp_next(u); + inp_next(u); - op->scale = (1 << SIB_S(ud_inp_curr(u))) & ~1; - op->index = UD_R_EAX + (SIB_I(ud_inp_curr(u)) | (REX_X(u->pfx_rex) << 3)); - op->base = UD_R_EAX + (SIB_B(ud_inp_curr(u)) | (REX_B(u->pfx_rex) << 3)); + op->scale = (1 << SIB_S(inp_curr(u))) & ~1; + op->index = UD_R_EAX + (SIB_I(inp_curr(u)) | (REX_X(u->pfx_rex) << 3)); + op->base = UD_R_EAX + (SIB_B(inp_curr(u)) | (REX_B(u->pfx_rex) << 3)); if (op->index == UD_R_ESP) { op->index = UD_NONE; @@ -554,11 +646,14 @@ decode_modrm_rm(struct ud *u, op->base = UD_NONE; } if (mod == 1) { - op->offset = 8; + offset = 8; } else { - op->offset = 32; + offset = 32; } } + } else { + op->scale = UD_NONE; + op->index = UD_NONE; } } else { const unsigned int bases[] = { UD_R_BX, UD_R_BX, UD_R_BP, UD_R_BP, @@ -567,58 +662,72 @@ decode_modrm_rm(struct ud *u, UD_NONE, UD_NONE, UD_NONE, UD_NONE }; op->base = bases[rm & 7]; op->index = indices[rm & 7]; + op->scale = UD_NONE; if (mod == 0 && rm == 6) { - op->offset= 16; + offset = 16; op->base = UD_NONE; } else if (mod == 1) { - op->offset = 8; + offset = 8; } else if (mod == 2) { - op->offset = 16; + offset = 16; } } - /* - * extract offset, if any - */ - switch (op->offset) { - case 8 : op->lval.ubyte = ud_inp_uint8(u); break; - case 16: op->lval.uword = ud_inp_uint16(u); break; - case 32: op->lval.udword = ud_inp_uint32(u); break; - case 64: op->lval.uqword = ud_inp_uint64(u); break; - default: break; + if (offset) { + decode_mem_disp(u, offset, op); + } else { + op->offset = 0; } } -/* ----------------------------------------------------------------------------- - * decode_o() - Decodes offset - * ----------------------------------------------------------------------------- + +/* + * decode_moffset + * Decode offset-only memory operand */ -static void -decode_o(struct ud* u, unsigned int s, struct ud_operand *op) +static void +decode_moffset(struct ud *u, unsigned int size, struct ud_operand *opr) { - switch (u->adr_mode) { - case 64: - op->offset = 64; - op->lval.uqword = ud_inp_uint64(u); - break; - case 32: - op->offset = 32; - op->lval.udword = ud_inp_uint32(u); - break; - case 16: - op->offset = 16; - op->lval.uword = ud_inp_uint16(u); - break; - default: - return; - } - op->type = UD_OP_MEM; - op->size = resolve_operand_size(u, s); + opr->type = UD_OP_MEM; + opr->base = UD_NONE; + opr->index = UD_NONE; + opr->scale = UD_NONE; + opr->size = resolve_operand_size(u, size); + decode_mem_disp(u, u->adr_mode, opr); } -/* ----------------------------------------------------------------------------- - * decode_operands() - Disassembles Operands. - * ----------------------------------------------------------------------------- + +static void +decode_vex_vvvv(struct ud *u, struct ud_operand *opr, unsigned size) +{ + uint8_t vvvv; + UD_ASSERT(u->vex_op != 0); + vvvv = ((u->vex_op == 0xc4 ? u->vex_b2 : u->vex_b1) >> 3) & 0xf; + decode_reg(u, opr, REGCLASS_XMM, (0xf & ~vvvv), size); +} + + +/* + * decode_vex_immreg + * Decode source operand encoded in immediate byte [7:4] + */ +static int +decode_vex_immreg(struct ud *u, struct ud_operand *opr, unsigned size) +{ + uint8_t imm = inp_next(u); + uint8_t mask = u->dis_mode == 64 ? 0xf : 0x7; + UD_RETURN_ON_ERROR(u); + UD_ASSERT(u->vex_op != 0); + decode_reg(u, opr, REGCLASS_XMM, mask & (imm >> 4), size); + return 0; +} + + +/* + * decode_operand + * + * Decodes a single operand. + * Returns the type of the operand (UD_NONE if none) */ static int decode_operand(struct ud *u, @@ -626,35 +735,33 @@ decode_operand(struct ud *u, enum ud_operand_code type, unsigned int size) { + operand->type = UD_NONE; + operand->_oprcode = type; + switch (type) { case OP_A : decode_a(u, operand); break; case OP_MR: - if (MODRM_MOD(modrm(u)) == 3) { - decode_modrm_rm(u, operand, T_GPR, - size == SZ_DY ? SZ_MDQ : SZ_V); - } else if (size == SZ_WV) { - decode_modrm_rm( u, operand, T_GPR, SZ_W); - } else if (size == SZ_BV) { - decode_modrm_rm( u, operand, T_GPR, SZ_B); - } else if (size == SZ_DY) { - decode_modrm_rm( u, operand, T_GPR, SZ_D); - } else { - ASSERT(!"unexpected size"); - } + decode_modrm_rm(u, operand, REGCLASS_GPR, + MODRM_MOD(modrm(u)) == 3 ? + Mx_reg_size(size) : Mx_mem_size(size)); break; + case OP_F: + u->br_far = 1; + /* intended fall through */ case OP_M: if (MODRM_MOD(modrm(u)) == 3) { - u->error = 1; + UDERR(u, "expected modrm.mod != 3\n"); } /* intended fall through */ case OP_E: - decode_modrm_rm(u, operand, T_GPR, size); + decode_modrm_rm(u, operand, REGCLASS_GPR, size); break; case OP_G: - decode_modrm_reg(u, operand, T_GPR, size); + decode_modrm_reg(u, operand, REGCLASS_GPR, size); break; + case OP_sI: case OP_I: decode_imm(u, size, operand); break; @@ -662,96 +769,68 @@ decode_operand(struct ud *u, operand->type = UD_OP_CONST; operand->lval.udword = 1; break; - case OP_PR: + case OP_N: if (MODRM_MOD(modrm(u)) != 3) { - u->error = 1; + UDERR(u, "expected modrm.mod == 3\n"); } - decode_modrm_rm(u, operand, T_MMX, size); + /* intended fall through */ + case OP_Q: + decode_modrm_rm(u, operand, REGCLASS_MMX, size); break; case OP_P: - decode_modrm_reg(u, operand, T_MMX, size); + decode_modrm_reg(u, operand, REGCLASS_MMX, size); break; - case OP_VR: + case OP_U: if (MODRM_MOD(modrm(u)) != 3) { - u->error = 1; + UDERR(u, "expected modrm.mod == 3\n"); } /* intended fall through */ case OP_W: - decode_modrm_rm(u, operand, T_XMM, size); + decode_modrm_rm(u, operand, REGCLASS_XMM, size); break; case OP_V: - decode_modrm_reg(u, operand, T_XMM, size); + decode_modrm_reg(u, operand, REGCLASS_XMM, size); break; - case OP_S: - decode_modrm_reg(u, operand, T_SEG, size); + case OP_H: + decode_vex_vvvv(u, operand, size); break; - case OP_AL: - case OP_CL: - case OP_DL: - case OP_BL: - case OP_AH: - case OP_CH: - case OP_DH: - case OP_BH: - operand->type = UD_OP_REG; - operand->base = UD_R_AL + (type - OP_AL); - operand->size = 8; + case OP_MU: + decode_modrm_rm(u, operand, REGCLASS_XMM, + MODRM_MOD(modrm(u)) == 3 ? + Mx_reg_size(size) : Mx_mem_size(size)); break; - case OP_DX: - operand->type = UD_OP_REG; - operand->base = UD_R_DX; - operand->size = 16; + case OP_S: + decode_modrm_reg(u, operand, REGCLASS_SEG, size); break; case OP_O: - decode_o(u, size, operand); + decode_moffset(u, size, operand); break; - case OP_rAXr8: - case OP_rCXr9: - case OP_rDXr10: - case OP_rBXr11: - case OP_rSPr12: - case OP_rBPr13: - case OP_rSIr14: - case OP_rDIr15: - case OP_rAX: - case OP_rCX: - case OP_rDX: - case OP_rBX: - case OP_rSP: - case OP_rBP: - case OP_rSI: - case OP_rDI: - operand->type = UD_OP_REG; - operand->base = resolve_gpr64(u, type, &operand->size); + case OP_R0: + case OP_R1: + case OP_R2: + case OP_R3: + case OP_R4: + case OP_R5: + case OP_R6: + case OP_R7: + decode_reg(u, operand, REGCLASS_GPR, + (REX_B(u->_rex) << 3) | (type - OP_R0), size); break; - case OP_ALr8b: - case OP_CLr9b: - case OP_DLr10b: - case OP_BLr11b: - case OP_AHr12b: - case OP_CHr13b: - case OP_DHr14b: - case OP_BHr15b: { - ud_type_t gpr = (type - OP_ALr8b) + UD_R_AL - + (REX_B(u->pfx_rex) << 3); - if (UD_R_AH <= gpr && u->pfx_rex) { - gpr = gpr + 4; - } - operand->type = UD_OP_REG; - operand->base = gpr; + case OP_AL: + case OP_AX: + case OP_eAX: + case OP_rAX: + decode_reg(u, operand, REGCLASS_GPR, 0, size); break; - } - case OP_eAX: - case OP_eCX: - case OP_eDX: - case OP_eBX: - case OP_eSP: - case OP_eBP: - case OP_eSI: - case OP_eDI: - operand->type = UD_OP_REG; - operand->base = resolve_gpr32(u, type); - operand->size = u->opr_mode == 16 ? 16 : 32; + case OP_CL: + case OP_CX: + case OP_eCX: + decode_reg(u, operand, REGCLASS_GPR, 1, size); + break; + case OP_DL: + case OP_DX: + case OP_eDX: + decode_reg(u, operand, REGCLASS_GPR, 2, size); break; case OP_ES: case OP_CS: @@ -762,7 +841,7 @@ decode_operand(struct ud *u, /* in 64bits mode, only fs and gs are allowed */ if (u->dis_mode == 64) { if (type != OP_FS && type != OP_GS) { - u->error= 1; + UDERR(u, "invalid segment register in 64bits\n"); } } operand->type = UD_OP_REG; @@ -773,17 +852,17 @@ decode_operand(struct ud *u, decode_imm(u, size, operand); operand->type = UD_OP_JIMM; break ; - case OP_Q: - decode_modrm_rm(u, operand, T_MMX, size); - break; case OP_R : - decode_modrm_rm(u, operand, T_GPR, size); + if (MODRM_MOD(modrm(u)) != 3) { + UDERR(u, "expected modrm.mod == 3\n"); + } + decode_modrm_rm(u, operand, REGCLASS_GPR, size); break; case OP_C: - decode_modrm_reg(u, operand, T_CRG, size); + decode_modrm_reg(u, operand, REGCLASS_CR, size); break; case OP_D: - decode_modrm_reg(u, operand, T_DBG, size); + decode_modrm_reg(u, operand, REGCLASS_DB, size); break; case OP_I3 : operand->type = UD_OP_CONST; @@ -799,18 +878,16 @@ decode_operand(struct ud *u, case OP_ST7: operand->type = UD_OP_REG; operand->base = (type - OP_ST0) + UD_R_ST0; - operand->size = 0; + operand->size = 80; break; - case OP_AX: - operand->type = UD_OP_REG; - operand->base = UD_R_AX; - operand->size = 16; + case OP_L: + decode_vex_immreg(u, operand, size); break; default : operand->type = UD_NONE; break; } - return 0; + return operand->type; } @@ -827,12 +904,21 @@ decode_operands(struct ud* u) decode_operand(u, &u->operand[0], u->itab_entry->operand1.type, u->itab_entry->operand1.size); - decode_operand(u, &u->operand[1], - u->itab_entry->operand2.type, - u->itab_entry->operand2.size); - decode_operand(u, &u->operand[2], - u->itab_entry->operand3.type, - u->itab_entry->operand3.size); + if (u->operand[0].type != UD_NONE) { + decode_operand(u, &u->operand[1], + u->itab_entry->operand2.type, + u->itab_entry->operand2.size); + } + if (u->operand[1].type != UD_NONE) { + decode_operand(u, &u->operand[2], + u->itab_entry->operand3.type, + u->itab_entry->operand3.size); + } + if (u->operand[2].type != UD_NONE) { + decode_operand(u, &u->operand[3], + u->itab_entry->operand4.type, + u->itab_entry->operand4.size); + } return 0; } @@ -852,19 +938,40 @@ clear_insn(register struct ud* u) u->pfx_rep = 0; u->pfx_repe = 0; u->pfx_rex = 0; - u->pfx_insn = 0; + u->pfx_str = 0; u->mnemonic = UD_Inone; u->itab_entry = NULL; u->have_modrm = 0; + u->br_far = 0; + u->vex_op = 0; + u->_rex = 0; + u->operand[0].type = UD_NONE; + u->operand[1].type = UD_NONE; + u->operand[2].type = UD_NONE; + u->operand[3].type = UD_NONE; +} - memset( &u->operand[ 0 ], 0, sizeof( struct ud_operand ) ); - memset( &u->operand[ 1 ], 0, sizeof( struct ud_operand ) ); - memset( &u->operand[ 2 ], 0, sizeof( struct ud_operand ) ); + +static UD_INLINE int +resolve_pfx_str(struct ud* u) +{ + if (u->pfx_str == 0xf3) { + if (P_STR(u->itab_entry->prefix)) { + u->pfx_rep = 0xf3; + } else { + u->pfx_repe = 0xf3; + } + } else if (u->pfx_str == 0xf2) { + u->pfx_repne = 0xf3; + } + return 0; } + static int resolve_mode( struct ud* u ) { + int default64; /* if in error state, bail out */ if ( u->error ) return -1; @@ -873,22 +980,34 @@ resolve_mode( struct ud* u ) /* Check validity of instruction m64 */ if ( P_INV64( u->itab_entry->prefix ) ) { - u->error = 1; - return -1; + UDERR(u, "instruction invalid in 64bits\n"); + return -1; } - /* effective rex prefix is the effective mask for the - * instruction hard-coded in the opcode map. + /* compute effective rex based on, + * - vex prefix (if any) + * - rex prefix (if any, and not vex) + * - allowed prefixes specified by the opcode map */ - u->pfx_rex = ( u->pfx_rex & 0x40 ) | - ( u->pfx_rex & REX_PFX_MASK( u->itab_entry->prefix ) ); + if (u->vex_op == 0xc4) { + /* vex has rex.rxb in 1's complement */ + u->_rex = ((~(u->vex_b1 >> 5) & 0x7) /* rex.0rxb */ | + ((u->vex_b2 >> 4) & 0x8) /* rex.w000 */); + } else if (u->vex_op == 0xc5) { + /* vex has rex.r in 1's complement */ + u->_rex = (~(u->vex_b1 >> 5)) & 4; + } else { + UD_ASSERT(u->vex_op == 0); + u->_rex = u->pfx_rex; + } + u->_rex &= REX_PFX_MASK(u->itab_entry->prefix); /* whether this instruction has a default operand size of * 64bit, also hardcoded into the opcode map. */ - u->default64 = P_DEF64( u->itab_entry->prefix ); + default64 = P_DEF64( u->itab_entry->prefix ); /* calculate effective operand size */ - if ( REX_W( u->pfx_rex ) ) { + if (REX_W(u->_rex)) { u->opr_mode = 64; } else if ( u->pfx_opr ) { u->opr_mode = 16; @@ -897,7 +1016,7 @@ resolve_mode( struct ud* u ) * the effective operand size in the absence of rex.w * prefix is 32. */ - u->opr_mode = ( u->default64 ) ? 64 : 32; + u->opr_mode = default64 ? 64 : 32; } /* calculate effective address size */ @@ -910,45 +1029,18 @@ resolve_mode( struct ud* u ) u->adr_mode = ( u->pfx_adr ) ? 32 : 16; } - /* These flags determine which operand to apply the operand size - * cast to. - */ - u->c1 = ( P_C1( u->itab_entry->prefix ) ) ? 1 : 0; - u->c2 = ( P_C2( u->itab_entry->prefix ) ) ? 1 : 0; - u->c3 = ( P_C3( u->itab_entry->prefix ) ) ? 1 : 0; - - /* set flags for implicit addressing */ - u->implicit_addr = P_IMPADDR( u->itab_entry->prefix ); - - return 0; -} - -static int gen_hex( struct ud *u ) -{ - unsigned int i; - unsigned char *src_ptr = ud_inp_sess( u ); - char* src_hex; - - /* bail out if in error stat. */ - if ( u->error ) return -1; - /* output buffer pointe */ - src_hex = ( char* ) u->insn_hexcode; - /* for each byte used to decode instruction */ - for ( i = 0; i < u->inp_ctr; ++i, ++src_ptr) { - sprintf( src_hex, "%02x", *src_ptr & 0xFF ); - src_hex += 2; - } return 0; } -static inline int +static UD_INLINE int decode_insn(struct ud *u, uint16_t ptr) { - ASSERT((ptr & 0x8000) == 0); + UD_ASSERT((ptr & 0x8000) == 0); u->itab_entry = &ud_itab[ ptr ]; u->mnemonic = u->itab_entry->mnemonic; - return (resolve_mode(u) == 0 && + return (resolve_pfx_str(u) == 0 && + resolve_mode(u) == 0 && decode_operands(u) == 0 && resolve_mnemonic(u) == 0) ? 0 : -1; } @@ -965,19 +1057,19 @@ decode_insn(struct ud *u, uint16_t ptr) * valid entry in the table, decode the operands, and read the final * byte to resolve the menmonic. */ -static inline int +static UD_INLINE int decode_3dnow(struct ud* u) { uint16_t ptr; - ASSERT(u->le->type == UD_TAB__OPC_3DNOW); - ASSERT(u->le->table[0xc] != 0); + UD_ASSERT(u->le->type == UD_TAB__OPC_3DNOW); + UD_ASSERT(u->le->table[0xc] != 0); decode_insn(u, u->le->table[0xc]); - ud_inp_next(u); + inp_next(u); if (u->error) { return -1; } - ptr = u->le->table[ud_inp_curr(u)]; - ASSERT((ptr & 0x8000) == 0); + ptr = u->le->table[inp_curr(u)]; + UD_ASSERT((ptr & 0x8000) == 0); u->mnemonic = ud_itab[ptr].mnemonic; return 0; } @@ -986,7 +1078,18 @@ decode_3dnow(struct ud* u) static int decode_ssepfx(struct ud *u) { - uint8_t idx = ((u->pfx_insn & 0xf) + 1) / 2; + uint8_t idx; + uint8_t pfx; + + /* + * String prefixes (f2, f3) take precedence over operand + * size prefix (66). + */ + pfx = u->pfx_str; + if (pfx == 0) { + pfx = u->pfx_opr; + } + idx = ((pfx & 0xf) + 1) / 2; if (u->le->table[idx] == 0) { idx = 0; } @@ -995,23 +1098,50 @@ decode_ssepfx(struct ud *u) * "Consume" the prefix as a part of the opcode, so it is no * longer exported as an instruction prefix. */ - switch (u->pfx_insn) { - case 0xf2: - u->pfx_repne = 0; - break; - case 0xf3: - u->pfx_rep = 0; - u->pfx_repe = 0; - break; - case 0x66: + u->pfx_str = 0; + if (pfx == 0x66) { + /* + * consume "66" only if it was used for decoding, leaving + * it to be used as an operands size override for some + * simd instructions. + */ u->pfx_opr = 0; - break; } } return decode_ext(u, u->le->table[idx]); } +static int +decode_vex(struct ud *u) +{ + uint8_t index; + if (u->dis_mode != 64 && MODRM_MOD(inp_peek(u)) != 0x3) { + index = 0; + } else { + u->vex_op = inp_curr(u); + u->vex_b1 = inp_next(u); + if (u->vex_op == 0xc4) { + uint8_t pp, m; + /* 3-byte vex */ + u->vex_b2 = inp_next(u); + UD_RETURN_ON_ERROR(u); + m = u->vex_b1 & 0x1f; + if (m == 0 || m > 3) { + UD_RETURN_WITH_ERROR(u, "reserved vex.m-mmmm value"); + } + pp = u->vex_b2 & 0x3; + index = (pp << 2) | m; + } else { + /* 2-byte vex */ + UD_ASSERT(u->vex_op == 0xc5); + index = 0x1 | ((u->vex_b1 & 0x3) << 2); + } + } + return decode_ext(u, u->le->table[index]); +} + + /* * decode_ext() * @@ -1038,7 +1168,7 @@ decode_ext(struct ud *u, uint16_t ptr) * 16 = 0,, 32 = 1, 64 = 2 */ case UD_TAB__OPC_MODE: - idx = u->dis_mode / 32; + idx = u->dis_mode != 64 ? 0 : 1; break; case UD_TAB__OPC_OSIZE: idx = eff_opr_mode(u->dis_mode, REX_W(u->pfx_rex), u->pfx_opr) / 32; @@ -1067,8 +1197,19 @@ decode_ext(struct ud *u, uint16_t ptr) break; case UD_TAB__OPC_SSE: return decode_ssepfx(u); + case UD_TAB__OPC_VEX: + return decode_vex(u); + case UD_TAB__OPC_VEX_W: + idx = vex_w(u); + break; + case UD_TAB__OPC_VEX_L: + idx = vex_l(u); + break; + case UD_TAB__OPC_TABLE: + inp_next(u); + return decode_opcode(u); default: - ASSERT(!"not reached"); + UD_ASSERT(!"not reached"); break; } @@ -1076,22 +1217,13 @@ decode_ext(struct ud *u, uint16_t ptr) } -static inline int +static int decode_opcode(struct ud *u) { uint16_t ptr; - ASSERT(u->le->type == UD_TAB__OPC_TABLE); - ud_inp_next(u); - if (u->error) { - return -1; - } - ptr = u->le->table[ud_inp_curr(u)]; - if (ptr & 0x8000) { - u->le = &ud_lookup_table_list[ptr & ~0x8000]; - if (u->le->type == UD_TAB__OPC_TABLE) { - return decode_opcode(u); - } - } + UD_ASSERT(u->le->type == UD_TAB__OPC_TABLE); + UD_RETURN_ON_ERROR(u); + ptr = u->le->table[inp_curr(u)]; return decode_ext(u, ptr); } @@ -1103,7 +1235,7 @@ decode_opcode(struct ud *u) unsigned int ud_decode(struct ud *u) { - ud_inp_start(u); + inp_start(u); clear_insn(u); u->le = &ud_lookup_table_list[0]; u->error = decode_prefixes(u) == -1 || @@ -1114,7 +1246,7 @@ ud_decode(struct ud *u) /* clear out the decode data. */ clear_insn(u); /* mark the sequence of bytes as invalid. */ - u->itab_entry = & s_ie__invalid; + u->itab_entry = &ud_itab[0]; /* entry 0 is invalid */ u->mnemonic = u->itab_entry->mnemonic; } @@ -1127,16 +1259,15 @@ ud_decode(struct ud *u) u->pfx_seg = 0; u->insn_offset = u->pc; /* set offset of instruction */ - u->insn_fill = 0; /* set translation buffer index to 0 */ + u->asm_buf_fill = 0; /* set translation buffer index to 0 */ u->pc += u->inp_ctr; /* move program counter by bytes decoded */ - gen_hex( u ); /* generate hex code */ /* return number of bytes disassembled. */ return u->inp_ctr; } +#endif // USE(UDIS86) + /* vim: set ts=2 sw=2 expandtab */ - -#endif // USE(UDIS86) diff --git a/Source/JavaScriptCore/disassembler/udis86/udis86_decode.h b/Source/JavaScriptCore/disassembler/udis86/udis86_decode.h index 940ed5ad6..411c8830e 100644 --- a/Source/JavaScriptCore/disassembler/udis86/udis86_decode.h +++ b/Source/JavaScriptCore/disassembler/udis86/udis86_decode.h @@ -27,74 +27,45 @@ #define UD_DECODE_H #include "udis86_types.h" +#include "udis86_udint.h" #include "udis86_itab.h" #define MAX_INSN_LENGTH 15 -/* register classes */ -#define T_NONE 0 -#define T_GPR 1 -#define T_MMX 2 -#define T_CRG 3 -#define T_DBG 4 -#define T_SEG 5 -#define T_XMM 6 - /* itab prefix bits */ #define P_none ( 0 ) -#define P_cast ( 1 << 0 ) -#define P_CAST(n) ( ( n >> 0 ) & 1 ) -#define P_c1 ( 1 << 0 ) -#define P_C1(n) ( ( n >> 0 ) & 1 ) -#define P_rexb ( 1 << 1 ) -#define P_REXB(n) ( ( n >> 1 ) & 1 ) -#define P_depM ( 1 << 2 ) -#define P_DEPM(n) ( ( n >> 2 ) & 1 ) -#define P_c3 ( 1 << 3 ) -#define P_C3(n) ( ( n >> 3 ) & 1 ) -#define P_inv64 ( 1 << 4 ) -#define P_INV64(n) ( ( n >> 4 ) & 1 ) + +#define P_inv64 ( 1 << 0 ) +#define P_INV64(n) ( ( n >> 0 ) & 1 ) +#define P_def64 ( 1 << 1 ) +#define P_DEF64(n) ( ( n >> 1 ) & 1 ) + +#define P_oso ( 1 << 2 ) +#define P_OSO(n) ( ( n >> 2 ) & 1 ) +#define P_aso ( 1 << 3 ) +#define P_ASO(n) ( ( n >> 3 ) & 1 ) + +#define P_rexb ( 1 << 4 ) +#define P_REXB(n) ( ( n >> 4 ) & 1 ) #define P_rexw ( 1 << 5 ) #define P_REXW(n) ( ( n >> 5 ) & 1 ) -#define P_c2 ( 1 << 6 ) -#define P_C2(n) ( ( n >> 6 ) & 1 ) -#define P_def64 ( 1 << 7 ) -#define P_DEF64(n) ( ( n >> 7 ) & 1 ) -#define P_rexr ( 1 << 8 ) -#define P_REXR(n) ( ( n >> 8 ) & 1 ) -#define P_oso ( 1 << 9 ) -#define P_OSO(n) ( ( n >> 9 ) & 1 ) -#define P_aso ( 1 << 10 ) -#define P_ASO(n) ( ( n >> 10 ) & 1 ) -#define P_rexx ( 1 << 11 ) -#define P_REXX(n) ( ( n >> 11 ) & 1 ) -#define P_ImpAddr ( 1 << 12 ) -#define P_IMPADDR(n) ( ( n >> 12 ) & 1 ) -#define P_seg ( 1 << 13 ) -#define P_SEG(n) ( ( n >> 13 ) & 1 ) -#define P_sext ( 1 << 14 ) -#define P_SEXT(n) ( ( n >> 14 ) & 1 ) - -/* rex prefix bits */ -#define REX_W(r) ( ( 0xF & ( r ) ) >> 3 ) -#define REX_R(r) ( ( 0x7 & ( r ) ) >> 2 ) -#define REX_X(r) ( ( 0x3 & ( r ) ) >> 1 ) -#define REX_B(r) ( ( 0x1 & ( r ) ) >> 0 ) -#define REX_PFX_MASK(n) ( ( P_REXW(n) << 3 ) | \ - ( P_REXR(n) << 2 ) | \ - ( P_REXX(n) << 1 ) | \ - ( P_REXB(n) << 0 ) ) - -/* scable-index-base bits */ -#define SIB_S(b) ( ( b ) >> 6 ) -#define SIB_I(b) ( ( ( b ) >> 3 ) & 7 ) -#define SIB_B(b) ( ( b ) & 7 ) - -/* modrm bits */ -#define MODRM_REG(b) ( ( ( b ) >> 3 ) & 7 ) -#define MODRM_NNN(b) ( ( ( b ) >> 3 ) & 7 ) -#define MODRM_MOD(b) ( ( ( b ) >> 6 ) & 3 ) -#define MODRM_RM(b) ( ( b ) & 7 ) +#define P_rexr ( 1 << 6 ) +#define P_REXR(n) ( ( n >> 6 ) & 1 ) +#define P_rexx ( 1 << 7 ) +#define P_REXX(n) ( ( n >> 7 ) & 1 ) + +#define P_seg ( 1 << 8 ) +#define P_SEG(n) ( ( n >> 8 ) & 1 ) + +#define P_vexl ( 1 << 9 ) +#define P_VEXL(n) ( ( n >> 9 ) & 1 ) +#define P_vexw ( 1 << 10 ) +#define P_VEXW(n) ( ( n >> 10 ) & 1 ) + +#define P_str ( 1 << 11 ) +#define P_STR(n) ( ( n >> 11 ) & 1 ) +#define P_strz ( 1 << 12 ) +#define P_STR_ZF(n) ( ( n >> 12 ) & 1 ) /* operand type constants -- order is important! */ @@ -102,25 +73,15 @@ enum ud_operand_code { OP_NONE, OP_A, OP_E, OP_M, OP_G, - OP_I, - - OP_AL, OP_CL, OP_DL, OP_BL, - OP_AH, OP_CH, OP_DH, OP_BH, - - OP_ALr8b, OP_CLr9b, OP_DLr10b, OP_BLr11b, - OP_AHr12b, OP_CHr13b, OP_DHr14b, OP_BHr15b, - - OP_AX, OP_CX, OP_DX, OP_BX, - OP_SI, OP_DI, OP_SP, OP_BP, - - OP_rAX, OP_rCX, OP_rDX, OP_rBX, - OP_rSP, OP_rBP, OP_rSI, OP_rDI, + OP_I, OP_F, - OP_rAXr8, OP_rCXr9, OP_rDXr10, OP_rBXr11, - OP_rSPr12, OP_rBPr13, OP_rSIr14, OP_rDIr15, + OP_R0, OP_R1, OP_R2, OP_R3, + OP_R4, OP_R5, OP_R6, OP_R7, - OP_eAX, OP_eCX, OP_eDX, OP_eBX, - OP_eSP, OP_eBP, OP_eSI, OP_eDI, + OP_AL, OP_CL, OP_DL, + OP_AX, OP_CX, OP_DX, + OP_eAX, OP_eCX, OP_eDX, + OP_rAX, OP_rCX, OP_rDX, OP_ES, OP_CS, OP_SS, OP_DS, OP_FS, OP_GS, @@ -129,45 +90,71 @@ enum ud_operand_code { OP_ST4, OP_ST5, OP_ST6, OP_ST7, OP_J, OP_S, OP_O, - OP_I1, OP_I3, + OP_I1, OP_I3, OP_sI, OP_V, OP_W, OP_Q, OP_P, + OP_U, OP_N, OP_MU, OP_H, + OP_L, - OP_R, OP_C, OP_D, OP_VR, OP_PR, + OP_R, OP_C, OP_D, OP_MR } UD_ATTR_PACKED; -/* operand size constants */ - -enum ud_operand_size { - SZ_NA = 0, - SZ_Z = 1, - SZ_V = 2, - SZ_P = 3, - SZ_WP = 4, - SZ_DP = 5, - SZ_MDQ = 6, - SZ_RDQ = 7, - - /* the following values are used as is, - * and thus hard-coded. changing them - * will break internals - */ - SZ_B = 8, - SZ_W = 16, - SZ_D = 32, - SZ_Q = 64, - SZ_T = 80, - SZ_O = 128, - - SZ_WV = 17, - SZ_BV = 18, - SZ_DY = 19 - -} UD_ATTR_PACKED; +/* + * Operand size constants + * + * Symbolic constants for various operand sizes. Some of these constants + * are given a value equal to the width of the data (SZ_B == 8), such + * that they maybe used interchangeably in the internals. Modifying them + * will most certainly break things! + */ +typedef uint16_t ud_operand_size_t; + +#define SZ_NA 0 +#define SZ_Z 1 +#define SZ_V 2 +#define SZ_Y 3 +#define SZ_X 4 +#define SZ_RDQ 7 +#define SZ_B 8 +#define SZ_W 16 +#define SZ_D 32 +#define SZ_Q 64 +#define SZ_T 80 +#define SZ_O 12 +#define SZ_DQ 128 /* double quad */ +#define SZ_QQ 256 /* quad quad */ + +/* + * Complex size types; that encode sizes for operands of type MR (memory or + * register); for internal use only. Id space above 256. + */ +#define SZ_BD ((SZ_B << 8) | SZ_D) +#define SZ_BV ((SZ_B << 8) | SZ_V) +#define SZ_WD ((SZ_W << 8) | SZ_D) +#define SZ_WV ((SZ_W << 8) | SZ_V) +#define SZ_WY ((SZ_W << 8) | SZ_Y) +#define SZ_DY ((SZ_D << 8) | SZ_Y) +#define SZ_WO ((SZ_W << 8) | SZ_O) +#define SZ_DO ((SZ_D << 8) | SZ_O) +#define SZ_QO ((SZ_Q << 8) | SZ_O) + + +/* resolve complex size type. + */ +static UD_INLINE ud_operand_size_t +Mx_mem_size(ud_operand_size_t size) +{ + return (size >> 8) & 0xff; +} +static UD_INLINE ud_operand_size_t +Mx_reg_size(ud_operand_size_t size) +{ + return size & 0xff; +} /* A single operand of an entry in the instruction table. * (internal use only) @@ -175,7 +162,7 @@ enum ud_operand_size { struct ud_itab_entry_operand { enum ud_operand_code type; - enum ud_operand_size size; + ud_operand_size_t size; }; @@ -188,6 +175,7 @@ struct ud_itab_entry struct ud_itab_entry_operand operand1; struct ud_itab_entry_operand operand2; struct ud_itab_entry_operand operand3; + struct ud_itab_entry_operand operand4; uint32_t prefix; }; @@ -197,55 +185,6 @@ struct ud_lookup_table_list_entry { const char *meta; }; - -static inline unsigned int sse_pfx_idx( const unsigned int pfx ) -{ - /* 00 = 0 - * f2 = 1 - * f3 = 2 - * 66 = 3 - */ - return ( ( pfx & 0xf ) + 1 ) / 2; -} - -static inline unsigned int mode_idx( const unsigned int mode ) -{ - /* 16 = 0 - * 32 = 1 - * 64 = 2 - */ - return ( mode / 32 ); -} - -static inline unsigned int modrm_mod_idx( const unsigned int mod ) -{ - /* !11 = 0 - * 11 = 1 - */ - return ( mod + 1 ) / 4; -} - -static inline unsigned int vendor_idx( const unsigned int vendor ) -{ - switch ( vendor ) { - case UD_VENDOR_AMD: return 0; - case UD_VENDOR_INTEL: return 1; - case UD_VENDOR_ANY: return 2; - default: return 2; - } -} - -static inline unsigned int is_group_ptr( uint16_t ptr ) -{ - return ( 0x8000 & ptr ); -} - -static inline unsigned int group_idx( uint16_t ptr ) -{ - return ( ~0x8000 & ptr ); -} - - extern struct ud_itab_entry ud_itab[]; extern struct ud_lookup_table_list_entry ud_lookup_table_list[]; diff --git a/Source/JavaScriptCore/disassembler/udis86/udis86_extern.h b/Source/JavaScriptCore/disassembler/udis86/udis86_extern.h index 8e87721e8..bf3314d09 100644 --- a/Source/JavaScriptCore/disassembler/udis86/udis86_extern.h +++ b/Source/JavaScriptCore/disassembler/udis86/udis86_extern.h @@ -1,6 +1,6 @@ /* udis86 - libudis86/extern.h * - * Copyright (c) 2002-2009 Vivek Thampi + * Copyright (c) 2002-2009, 2013 Vivek Thampi * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, @@ -32,57 +32,82 @@ extern "C" { #include "udis86_types.h" +#if defined(_MSC_VER) && defined(_USRDLL) +# ifdef LIBUDIS86_EXPORTS +# define LIBUDIS86_DLLEXTERN __declspec(dllexport) +# else +# define LIBUDIS86_DLLEXTERN __declspec(dllimport) +# endif +#else +# define LIBUDIS86_DLLEXTERN +#endif + /* ============================= PUBLIC API ================================= */ -extern void ud_init(struct ud*); +extern LIBUDIS86_DLLEXTERN void ud_init(struct ud*); -extern void ud_set_mode(struct ud*, uint8_t); +extern LIBUDIS86_DLLEXTERN void ud_set_mode(struct ud*, uint8_t); -extern void ud_set_pc(struct ud*, uint64_t); +extern LIBUDIS86_DLLEXTERN void ud_set_pc(struct ud*, uint64_t); -extern void ud_set_input_hook(struct ud*, int (*)(struct ud*)); +extern LIBUDIS86_DLLEXTERN void ud_set_input_hook(struct ud*, int (*)(struct ud*)); -extern void ud_set_input_buffer(struct ud*, uint8_t*, size_t); +extern LIBUDIS86_DLLEXTERN void ud_set_input_buffer(struct ud*, const uint8_t*, size_t); #ifndef __UD_STANDALONE__ -extern void ud_set_input_file(struct ud*, FILE*); +extern LIBUDIS86_DLLEXTERN void ud_set_input_file(struct ud*, FILE*); #endif /* __UD_STANDALONE__ */ -extern void ud_set_vendor(struct ud*, unsigned); +extern LIBUDIS86_DLLEXTERN void ud_set_vendor(struct ud*, unsigned); + +extern LIBUDIS86_DLLEXTERN void ud_set_syntax(struct ud*, void (*)(struct ud*)); + +extern LIBUDIS86_DLLEXTERN void ud_input_skip(struct ud*, size_t); + +extern LIBUDIS86_DLLEXTERN int ud_input_end(const struct ud*); -extern void ud_set_syntax(struct ud*, void (*)(struct ud*)); +extern LIBUDIS86_DLLEXTERN unsigned int ud_decode(struct ud*); -extern void ud_input_skip(struct ud*, size_t); +extern LIBUDIS86_DLLEXTERN unsigned int ud_disassemble(struct ud*); -extern int ud_input_end(struct ud*); +extern LIBUDIS86_DLLEXTERN void ud_translate_intel(struct ud*); -extern unsigned int ud_decode(struct ud*); +extern LIBUDIS86_DLLEXTERN void ud_translate_att(struct ud*); -extern unsigned int ud_disassemble(struct ud*); +extern LIBUDIS86_DLLEXTERN const char* ud_insn_asm(const struct ud* u); -extern void ud_translate_intel(struct ud*); +extern LIBUDIS86_DLLEXTERN const uint8_t* ud_insn_ptr(const struct ud* u); -extern void ud_translate_att(struct ud*); +extern LIBUDIS86_DLLEXTERN uint64_t ud_insn_off(const struct ud*); -extern char* ud_insn_asm(struct ud* u); +extern LIBUDIS86_DLLEXTERN const char* ud_insn_hex(struct ud*); -extern uint8_t* ud_insn_ptr(struct ud* u); +extern LIBUDIS86_DLLEXTERN unsigned int ud_insn_len(const struct ud* u); -extern uint64_t ud_insn_off(struct ud*); +extern LIBUDIS86_DLLEXTERN const struct ud_operand* ud_insn_opr(const struct ud *u, unsigned int n); -extern char* ud_insn_hex(struct ud*); +extern LIBUDIS86_DLLEXTERN int ud_opr_is_sreg(const struct ud_operand *opr); -extern unsigned int ud_insn_len(struct ud* u); +extern LIBUDIS86_DLLEXTERN int ud_opr_is_gpr(const struct ud_operand *opr); -extern const char* ud_lookup_mnemonic(enum ud_mnemonic_code c); +extern LIBUDIS86_DLLEXTERN enum ud_mnemonic_code ud_insn_mnemonic(const struct ud *u); -extern void ud_set_user_opaque_data(struct ud*, void*); +extern LIBUDIS86_DLLEXTERN const char* ud_lookup_mnemonic(enum ud_mnemonic_code c); -extern void *ud_get_user_opaque_data(struct ud*); +extern LIBUDIS86_DLLEXTERN void ud_set_user_opaque_data(struct ud*, void*); + +extern LIBUDIS86_DLLEXTERN void* ud_get_user_opaque_data(const struct ud*); + +extern LIBUDIS86_DLLEXTERN void ud_set_asm_buffer(struct ud *u, char *buf, size_t size); + +extern LIBUDIS86_DLLEXTERN void ud_set_sym_resolver(struct ud *u, + const char* (*resolver)(struct ud*, + uint64_t addr, + int64_t *offset)); /* ========================================================================== */ #ifdef __cplusplus } #endif -#endif +#endif /* UD_EXTERN_H */ diff --git a/Source/JavaScriptCore/disassembler/udis86/udis86_input.c b/Source/JavaScriptCore/disassembler/udis86/udis86_input.c deleted file mode 100644 index 4dbe32876..000000000 --- a/Source/JavaScriptCore/disassembler/udis86/udis86_input.c +++ /dev/null @@ -1,262 +0,0 @@ -/* udis86 - libudis86/input.c - * - * Copyright (c) 2002-2009 Vivek Thampi - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include "config.h" - -#if USE(UDIS86) - -#include "udis86_extern.h" -#include "udis86_types.h" -#include "udis86_input.h" - -/* ----------------------------------------------------------------------------- - * inp_buff_hook() - Hook for buffered inputs. - * ----------------------------------------------------------------------------- - */ -static int -inp_buff_hook(struct ud* u) -{ - if (u->inp_buff < u->inp_buff_end) - return *u->inp_buff++; - else return -1; -} - -#ifndef __UD_STANDALONE__ -/* ----------------------------------------------------------------------------- - * inp_file_hook() - Hook for FILE inputs. - * ----------------------------------------------------------------------------- - */ -static int -inp_file_hook(struct ud* u) -{ - return fgetc(u->inp_file); -} -#endif /* __UD_STANDALONE__*/ - -/* ============================================================================= - * ud_inp_set_hook() - Sets input hook. - * ============================================================================= - */ -extern void -ud_set_input_hook(register struct ud* u, int (*hook)(struct ud*)) -{ - u->inp_hook = hook; - ud_inp_init(u); -} - -extern void -ud_set_user_opaque_data( struct ud * u, void * opaque ) -{ - u->user_opaque_data = opaque; -} - -extern void * -ud_get_user_opaque_data( struct ud * u ) -{ - return u->user_opaque_data; -} - -/* ============================================================================= - * ud_inp_set_buffer() - Set buffer as input. - * ============================================================================= - */ -extern void -ud_set_input_buffer(register struct ud* u, uint8_t* buf, size_t len) -{ - u->inp_hook = inp_buff_hook; - u->inp_buff = buf; - u->inp_buff_end = buf + len; - ud_inp_init(u); -} - -#ifndef __UD_STANDALONE__ -/* ============================================================================= - * ud_input_set_file() - Set buffer as input. - * ============================================================================= - */ -extern void -ud_set_input_file(register struct ud* u, FILE* f) -{ - u->inp_hook = inp_file_hook; - u->inp_file = f; - ud_inp_init(u); -} -#endif /* __UD_STANDALONE__ */ - -/* ============================================================================= - * ud_input_skip() - Skip n input bytes. - * ============================================================================= - */ -extern void -ud_input_skip(struct ud* u, size_t n) -{ - while (n--) { - u->inp_hook(u); - } -} - -/* ============================================================================= - * ud_input_end() - Test for end of input. - * ============================================================================= - */ -extern int -ud_input_end(struct ud* u) -{ - return (u->inp_curr == u->inp_fill) && u->inp_end; -} - -/* ----------------------------------------------------------------------------- - * ud_inp_next() - Loads and returns the next byte from input. - * - * inp_curr and inp_fill are pointers to the cache. The program is written based - * on the property that they are 8-bits in size, and will eventually wrap around - * forming a circular buffer. So, the size of the cache is 256 in size, kind of - * unnecessary yet optimized. - * - * A buffer inp_sess stores the bytes disassembled for a single session. - * ----------------------------------------------------------------------------- - */ -extern uint8_t ud_inp_next(struct ud* u) -{ - int c = -1; - /* if current pointer is not upto the fill point in the - * input cache. - */ - if ( u->inp_curr != u->inp_fill ) { - c = u->inp_cache[ ++u->inp_curr ]; - /* if !end-of-input, call the input hook and get a byte */ - } else if ( u->inp_end || ( c = u->inp_hook( u ) ) == -1 ) { - /* end-of-input, mark it as an error, since the decoder, - * expected a byte more. - */ - u->error = 1; - /* flag end of input */ - u->inp_end = 1; - return 0; - } else { - /* increment pointers, we have a new byte. */ - u->inp_curr = ++u->inp_fill; - /* add the byte to the cache */ - u->inp_cache[ u->inp_fill ] = c; - } - /* record bytes input per decode-session. */ - u->inp_sess[ u->inp_ctr++ ] = c; - /* return byte */ - return ( uint8_t ) c; -} - -/* ----------------------------------------------------------------------------- - * ud_inp_back() - Move back a single byte in the stream. - * ----------------------------------------------------------------------------- - */ -extern void -ud_inp_back(struct ud* u) -{ - if ( u->inp_ctr > 0 ) { - --u->inp_curr; - --u->inp_ctr; - } -} - -/* ----------------------------------------------------------------------------- - * ud_inp_peek() - Peek into the next byte in source. - * ----------------------------------------------------------------------------- - */ -extern uint8_t -ud_inp_peek(struct ud* u) -{ - uint8_t r = ud_inp_next(u); - if ( !u->error ) ud_inp_back(u); /* Don't backup if there was an error */ - return r; -} - -/* ----------------------------------------------------------------------------- - * ud_inp_move() - Move ahead n input bytes. - * ----------------------------------------------------------------------------- - */ -extern void -ud_inp_move(struct ud* u, size_t n) -{ - while (n--) - ud_inp_next(u); -} - -/*------------------------------------------------------------------------------ - * ud_inp_uintN() - return uintN from source. - *------------------------------------------------------------------------------ - */ -extern uint8_t -ud_inp_uint8(struct ud* u) -{ - return ud_inp_next(u); -} - -extern uint16_t -ud_inp_uint16(struct ud* u) -{ - uint16_t r, ret; - - ret = ud_inp_next(u); - r = ud_inp_next(u); - return ret | (r << 8); -} - -extern uint32_t -ud_inp_uint32(struct ud* u) -{ - uint32_t r, ret; - - ret = ud_inp_next(u); - r = ud_inp_next(u); - ret = ret | (r << 8); - r = ud_inp_next(u); - ret = ret | (r << 16); - r = ud_inp_next(u); - return ret | (r << 24); -} - -extern uint64_t -ud_inp_uint64(struct ud* u) -{ - uint64_t r, ret; - - ret = ud_inp_next(u); - r = ud_inp_next(u); - ret = ret | (r << 8); - r = ud_inp_next(u); - ret = ret | (r << 16); - r = ud_inp_next(u); - ret = ret | (r << 24); - r = ud_inp_next(u); - ret = ret | (r << 32); - r = ud_inp_next(u); - ret = ret | (r << 40); - r = ud_inp_next(u); - ret = ret | (r << 48); - r = ud_inp_next(u); - return ret | (r << 56); -} - -#endif // USE(UDIS86) diff --git a/Source/JavaScriptCore/disassembler/udis86/udis86_input.h b/Source/JavaScriptCore/disassembler/udis86/udis86_input.h deleted file mode 100644 index 96865a88b..000000000 --- a/Source/JavaScriptCore/disassembler/udis86/udis86_input.h +++ /dev/null @@ -1,67 +0,0 @@ -/* udis86 - libudis86/input.h - * - * Copyright (c) 2002-2009 Vivek Thampi - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef UD_INPUT_H -#define UD_INPUT_H - -#include "udis86_types.h" - -uint8_t ud_inp_next(struct ud*); -uint8_t ud_inp_peek(struct ud*); -uint8_t ud_inp_uint8(struct ud*); -uint16_t ud_inp_uint16(struct ud*); -uint32_t ud_inp_uint32(struct ud*); -uint64_t ud_inp_uint64(struct ud*); -void ud_inp_move(struct ud*, size_t); -void ud_inp_back(struct ud*); - -/* ud_inp_init() - Initializes the input system. */ -#define ud_inp_init(u) \ -do { \ - u->inp_curr = 0; \ - u->inp_fill = 0; \ - u->inp_ctr = 0; \ - u->inp_end = 0; \ -} while (0) - -/* ud_inp_start() - Should be called before each de-code operation. */ -#define ud_inp_start(u) u->inp_ctr = 0 - -/* ud_inp_back() - Resets the current pointer to its position before the current - * instruction disassembly was started. - */ -#define ud_inp_reset(u) \ -do { \ - u->inp_curr -= u->inp_ctr; \ - u->inp_ctr = 0; \ -} while (0) - -/* ud_inp_sess() - Returns the pointer to current session. */ -#define ud_inp_sess(u) (u->inp_sess) - -/* inp_cur() - Returns the current input byte. */ -#define ud_inp_curr(u) ((u)->inp_cache[(u)->inp_curr]) - -#endif diff --git a/Source/JavaScriptCore/disassembler/udis86/udis86_syn-att.c b/Source/JavaScriptCore/disassembler/udis86/udis86_syn-att.c index c9c84880a..7d5646e4a 100644 --- a/Source/JavaScriptCore/disassembler/udis86/udis86_syn-att.c +++ b/Source/JavaScriptCore/disassembler/udis86/udis86_syn-att.c @@ -23,6 +23,7 @@ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ + #include "config.h" #if USE(UDIS86) @@ -32,6 +33,7 @@ #include "udis86_decode.h" #include "udis86_itab.h" #include "udis86_syn.h" +#include "udis86_udint.h" /* ----------------------------------------------------------------------------- * opr_cast() - Prints an operand cast. @@ -41,9 +43,9 @@ static void opr_cast(struct ud* u, struct ud_operand* op) { switch(op->size) { - case 16 : case 32 : - mkasm(u, "*"); break; - default: break; + case 16 : case 32 : + ud_asmprintf(u, "*"); break; + default: break; } } @@ -55,107 +57,66 @@ static void gen_operand(struct ud* u, struct ud_operand* op) { switch(op->type) { - case UD_OP_REG: - mkasm(u, "%%%s", ud_reg_tab[op->base - UD_R_AL]); - break; - - case UD_OP_MEM: - if (u->br_far) opr_cast(u, op); - if (u->pfx_seg) - mkasm(u, "%%%s:", ud_reg_tab[u->pfx_seg - UD_R_AL]); - if (op->offset == 8) { - if (op->lval.sbyte < 0) - mkasm(u, "-0x%x", (-op->lval.sbyte) & 0xff); - else - mkasm(u, "0x%x", op->lval.sbyte); - } - else if (op->offset == 16) { - if (op->lval.sword < 0) - mkasm(u, "-0x%x", (-op->lval.sword) & 0xffff); - else - mkasm(u, "0x%x", op->lval.sword); - } else if (op->offset == 32) { - if (op->lval.sdword < 0) - mkasm(u, "-0x%x", (-op->lval.sdword) & 0xffffffff); - else - mkasm(u, "0x%x", op->lval.sdword); - } else if (op->offset == 64) { - if (op->lval.sdword < 0) - mkasm(u, "-0x" FMT64 "x", (uint64_t)-op->lval.sqword); - else - mkasm(u, "0x" FMT64 "x", (uint64_t)op->lval.sqword); - } + case UD_OP_CONST: + ud_asmprintf(u, "$0x%x", op->lval.udword); + break; - if (op->base) - mkasm(u, "(%%%s", ud_reg_tab[op->base - UD_R_AL]); - if (op->index) { - if (op->base) - mkasm(u, ","); - else mkasm(u, "("); - mkasm(u, "%%%s", ud_reg_tab[op->index - UD_R_AL]); - } - if (op->scale) - mkasm(u, ",%d", op->scale); - if (op->base || op->index) - mkasm(u, ")"); - break; + case UD_OP_REG: + ud_asmprintf(u, "%%%s", ud_reg_tab[op->base - UD_R_AL]); + break; - case UD_OP_IMM: { - int64_t imm = 0; - uint64_t sext_mask = 0xffffffffffffffffull; - unsigned sext_size = op->size; - - switch (op->size) { - case 8: imm = op->lval.sbyte; break; - case 16: imm = op->lval.sword; break; - case 32: imm = op->lval.sdword; break; - case 64: imm = op->lval.sqword; break; - } - if ( P_SEXT( u->itab_entry->prefix ) ) { - sext_size = u->operand[ 0 ].size; - if ( u->mnemonic == UD_Ipush ) - /* push sign-extends to operand size */ - sext_size = u->opr_mode; - } - if ( sext_size < 64 ) - sext_mask = ( 1ull << sext_size ) - 1; - mkasm( u, "$0x" FMT64 "x", (uint64_t)(imm & sext_mask) ); - - break; + case UD_OP_MEM: + if (u->br_far) { + opr_cast(u, op); } - - case UD_OP_JIMM: - switch (op->size) { - case 8: - mkasm(u, "0x" FMT64 "x", (uint64_t)(u->pc + op->lval.sbyte)); - break; - case 16: - mkasm(u, "0x" FMT64 "x", (uint64_t)((u->pc + op->lval.sword) & 0xffff) ); - break; - case 32: - if (u->dis_mode == 32) - mkasm(u, "0x" FMT64 "x", (uint64_t)((u->pc + op->lval.sdword) & 0xffffffff)); - else - mkasm(u, "0x" FMT64 "x", (uint64_t)(u->pc + op->lval.sdword)); - break; - default:break; - } - break; - - case UD_OP_PTR: - switch (op->size) { - case 32: - mkasm(u, "$0x%x, $0x%x", op->lval.ptr.seg, - op->lval.ptr.off & 0xFFFF); - break; - case 48: - mkasm(u, "$0x%x, $0x%lx", op->lval.ptr.seg, - (unsigned long)op->lval.ptr.off); - break; - } - break; - - default: return; + if (u->pfx_seg) { + ud_asmprintf(u, "%%%s:", ud_reg_tab[u->pfx_seg - UD_R_AL]); + } + if (op->offset != 0) { + ud_syn_print_mem_disp(u, op, 0); + } + if (op->base) { + ud_asmprintf(u, "(%%%s", ud_reg_tab[op->base - UD_R_AL]); + } + if (op->index) { + if (op->base) { + ud_asmprintf(u, ","); + } else { + ud_asmprintf(u, "("); + } + ud_asmprintf(u, "%%%s", ud_reg_tab[op->index - UD_R_AL]); + } + if (op->scale) { + ud_asmprintf(u, ",%d", op->scale); + } + if (op->base || op->index) { + ud_asmprintf(u, ")"); + } + break; + + case UD_OP_IMM: + ud_asmprintf(u, "$"); + ud_syn_print_imm(u, op); + break; + + case UD_OP_JIMM: + ud_syn_print_addr(u, ud_syn_rel_target(u, op)); + break; + + case UD_OP_PTR: + switch (op->size) { + case 32: + ud_asmprintf(u, "$0x%x, $0x%x", op->lval.ptr.seg, + op->lval.ptr.off & 0xFFFF); + break; + case 48: + ud_asmprintf(u, "$0x%x, $0x%x", op->lval.ptr.seg, + op->lval.ptr.off); + break; + } + break; + + default: return; } } @@ -167,99 +128,108 @@ extern void ud_translate_att(struct ud *u) { int size = 0; - unsigned i; + int star = 0; /* check if P_OSO prefix is used */ if (! P_OSO(u->itab_entry->prefix) && u->pfx_opr) { - switch (u->dis_mode) { - case 16: - mkasm(u, "o32 "); - break; - case 32: - case 64: - mkasm(u, "o16 "); - break; - } + switch (u->dis_mode) { + case 16: + ud_asmprintf(u, "o32 "); + break; + case 32: + case 64: + ud_asmprintf(u, "o16 "); + break; + } } /* check if P_ASO prefix was used */ if (! P_ASO(u->itab_entry->prefix) && u->pfx_adr) { - switch (u->dis_mode) { - case 16: - mkasm(u, "a32 "); - break; - case 32: - mkasm(u, "a16 "); - break; - case 64: - mkasm(u, "a32 "); - break; - } + switch (u->dis_mode) { + case 16: + ud_asmprintf(u, "a32 "); + break; + case 32: + ud_asmprintf(u, "a16 "); + break; + case 64: + ud_asmprintf(u, "a32 "); + break; + } } if (u->pfx_lock) - mkasm(u, "lock "); - if (u->pfx_rep) - mkasm(u, "rep "); - if (u->pfx_repne) - mkasm(u, "repne "); + ud_asmprintf(u, "lock "); + if (u->pfx_rep) { + ud_asmprintf(u, "rep "); + } else if (u->pfx_repe) { + ud_asmprintf(u, "repe "); + } else if (u->pfx_repne) { + ud_asmprintf(u, "repne "); + } /* special instructions */ switch (u->mnemonic) { - case UD_Iretf: - mkasm(u, "lret "); - break; - case UD_Idb: - mkasm(u, ".byte 0x%x", u->operand[0].lval.ubyte); - return; - case UD_Ijmp: - case UD_Icall: - if (u->br_far) mkasm(u, "l"); - mkasm(u, "%s", ud_lookup_mnemonic(u->mnemonic)); - break; - case UD_Ibound: - case UD_Ienter: - if (u->operand[0].type != UD_NONE) - gen_operand(u, &u->operand[0]); - if (u->operand[1].type != UD_NONE) { - mkasm(u, ","); - gen_operand(u, &u->operand[1]); - } - return; - default: - mkasm(u, "%s", ud_lookup_mnemonic(u->mnemonic)); + case UD_Iretf: + ud_asmprintf(u, "lret "); + break; + case UD_Idb: + ud_asmprintf(u, ".byte 0x%x", u->operand[0].lval.ubyte); + return; + case UD_Ijmp: + case UD_Icall: + if (u->br_far) ud_asmprintf(u, "l"); + if (u->operand[0].type == UD_OP_REG) { + star = 1; + } + ud_asmprintf(u, "%s", ud_lookup_mnemonic(u->mnemonic)); + break; + case UD_Ibound: + case UD_Ienter: + if (u->operand[0].type != UD_NONE) + gen_operand(u, &u->operand[0]); + if (u->operand[1].type != UD_NONE) { + ud_asmprintf(u, ","); + gen_operand(u, &u->operand[1]); + } + return; + default: + ud_asmprintf(u, "%s", ud_lookup_mnemonic(u->mnemonic)); } - for (i = 3; i--;) { - if (u->operand[i].size > size - && u->operand[i].type != UD_OP_JIMM) - size = u->operand[i].size; + if (size == 8) { + ud_asmprintf(u, "b"); + } else if (size == 16) { + ud_asmprintf(u, "w"); + } else if (size == 64) { + ud_asmprintf(u, "q"); } - if (size == 8) - mkasm(u, "b"); - else if (size == 16) - mkasm(u, "w"); - else if (size == 32) - mkasm(u, "l"); - else if (size == 64) - mkasm(u, "q"); - - mkasm(u, " "); + if (star) { + ud_asmprintf(u, " *"); + } else { + ud_asmprintf(u, " "); + } + if (u->operand[3].type != UD_NONE) { + gen_operand(u, &u->operand[3]); + ud_asmprintf(u, ", "); + } if (u->operand[2].type != UD_NONE) { - gen_operand(u, &u->operand[2]); - mkasm(u, ", "); + gen_operand(u, &u->operand[2]); + ud_asmprintf(u, ", "); } - if (u->operand[1].type != UD_NONE) { - gen_operand(u, &u->operand[1]); - mkasm(u, ", "); + gen_operand(u, &u->operand[1]); + ud_asmprintf(u, ", "); + } + if (u->operand[0].type != UD_NONE) { + gen_operand(u, &u->operand[0]); } - - if (u->operand[0].type != UD_NONE) - gen_operand(u, &u->operand[0]); } #endif // USE(UDIS86) +/* +vim: set ts=2 sw=2 expandtab +*/ diff --git a/Source/JavaScriptCore/disassembler/udis86/udis86_syn-intel.c b/Source/JavaScriptCore/disassembler/udis86/udis86_syn-intel.c index 4ad42eb63..769df8901 100644 --- a/Source/JavaScriptCore/disassembler/udis86/udis86_syn-intel.c +++ b/Source/JavaScriptCore/disassembler/udis86/udis86_syn-intel.c @@ -1,6 +1,6 @@ /* udis86 - libudis86/syn-intel.c * - * Copyright (c) 2002-2009 Vivek Thampi + * Copyright (c) 2002-2013 Vivek Thampi * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, @@ -23,6 +23,7 @@ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ + #include "config.h" #if USE(UDIS86) @@ -32,6 +33,7 @@ #include "udis86_decode.h" #include "udis86_itab.h" #include "udis86_syn.h" +#include "udis86_udint.h" /* ----------------------------------------------------------------------------- * opr_cast() - Prints an operand cast. @@ -40,16 +42,19 @@ static void opr_cast(struct ud* u, struct ud_operand* op) { + if (u->br_far) { + ud_asmprintf(u, "far "); + } switch(op->size) { - case 8: mkasm(u, "byte " ); break; - case 16: mkasm(u, "word " ); break; - case 32: mkasm(u, "dword "); break; - case 64: mkasm(u, "qword "); break; - case 80: mkasm(u, "tword "); break; - default: break; + case 8: ud_asmprintf(u, "byte " ); break; + case 16: ud_asmprintf(u, "word " ); break; + case 32: ud_asmprintf(u, "dword "); break; + case 64: ud_asmprintf(u, "qword "); break; + case 80: ud_asmprintf(u, "tword "); break; + case 128: ud_asmprintf(u, "oword "); break; + case 256: ud_asmprintf(u, "yword "); break; + default: break; } - if (u->br_far) - mkasm(u, "far "); } /* ----------------------------------------------------------------------------- @@ -59,121 +64,63 @@ opr_cast(struct ud* u, struct ud_operand* op) static void gen_operand(struct ud* u, struct ud_operand* op, int syn_cast) { switch(op->type) { - case UD_OP_REG: - mkasm(u, "%s", ud_reg_tab[op->base - UD_R_AL]); - break; - - case UD_OP_MEM: { - - int op_f = 0; - - if (syn_cast) - opr_cast(u, op); - - mkasm(u, "["); - - if (u->pfx_seg) - mkasm(u, "%s:", ud_reg_tab[u->pfx_seg - UD_R_AL]); - - if (op->base) { - mkasm(u, "%s", ud_reg_tab[op->base - UD_R_AL]); - op_f = 1; - } - - if (op->index) { - if (op_f) - mkasm(u, "+"); - mkasm(u, "%s", ud_reg_tab[op->index - UD_R_AL]); - op_f = 1; - } + case UD_OP_REG: + ud_asmprintf(u, "%s", ud_reg_tab[op->base - UD_R_AL]); + break; - if (op->scale) - mkasm(u, "*%d", op->scale); - - if (op->offset == 8) { - if (op->lval.sbyte < 0) - mkasm(u, "-0x%x", -op->lval.sbyte); - else mkasm(u, "%s0x%x", (op_f) ? "+" : "", op->lval.sbyte); - } - else if (op->offset == 16) - mkasm(u, "%s0x%x", (op_f) ? "+" : "", op->lval.uword); - else if (op->offset == 32) { - if (u->adr_mode == 64) { - if (op->lval.sdword < 0) - mkasm(u, "-0x%x", -op->lval.sdword); - else mkasm(u, "%s0x%x", (op_f) ? "+" : "", op->lval.sdword); - } - else mkasm(u, "%s0x%lx", (op_f) ? "+" : "", (unsigned long)op->lval.udword); - } - else if (op->offset == 64) - mkasm(u, "%s0x" FMT64 "x", (op_f) ? "+" : "", (uint64_t)op->lval.uqword); - - mkasm(u, "]"); - break; - } - - case UD_OP_IMM: { - int64_t imm = 0; - uint64_t sext_mask = 0xffffffffffffffffull; - unsigned sext_size = op->size; - - if (syn_cast) - opr_cast(u, op); - switch (op->size) { - case 8: imm = op->lval.sbyte; break; - case 16: imm = op->lval.sword; break; - case 32: imm = op->lval.sdword; break; - case 64: imm = op->lval.sqword; break; - } - if ( P_SEXT( u->itab_entry->prefix ) ) { - sext_size = u->operand[ 0 ].size; - if ( u->mnemonic == UD_Ipush ) - /* push sign-extends to operand size */ - sext_size = u->opr_mode; - } - if ( sext_size < 64 ) - sext_mask = ( 1ull << sext_size ) - 1; - mkasm( u, "0x" FMT64 "x", (uint64_t)(imm & sext_mask) ); - - break; + case UD_OP_MEM: + if (syn_cast) { + opr_cast(u, op); } + ud_asmprintf(u, "["); + if (u->pfx_seg) { + ud_asmprintf(u, "%s:", ud_reg_tab[u->pfx_seg - UD_R_AL]); + } + if (op->base) { + ud_asmprintf(u, "%s", ud_reg_tab[op->base - UD_R_AL]); + } + if (op->index) { + ud_asmprintf(u, "%s%s", op->base != UD_NONE? "+" : "", + ud_reg_tab[op->index - UD_R_AL]); + if (op->scale) { + ud_asmprintf(u, "*%d", op->scale); + } + } + if (op->offset != 0) { + ud_syn_print_mem_disp(u, op, (op->base != UD_NONE || + op->index != UD_NONE) ? 1 : 0); + } + ud_asmprintf(u, "]"); + break; + + case UD_OP_IMM: + ud_syn_print_imm(u, op); + break; + + + case UD_OP_JIMM: + ud_syn_print_addr(u, ud_syn_rel_target(u, op)); + break; + + case UD_OP_PTR: + switch (op->size) { + case 32: + ud_asmprintf(u, "word 0x%x:0x%x", op->lval.ptr.seg, + op->lval.ptr.off & 0xFFFF); + break; + case 48: + ud_asmprintf(u, "dword 0x%x:0x%x", op->lval.ptr.seg, + op->lval.ptr.off); + break; + } + break; + case UD_OP_CONST: + if (syn_cast) opr_cast(u, op); + ud_asmprintf(u, "%d", op->lval.udword); + break; - case UD_OP_JIMM: - if (syn_cast) opr_cast(u, op); - switch (op->size) { - case 8: - mkasm(u, "0x" FMT64 "x", (uint64_t)(u->pc + op->lval.sbyte)); - break; - case 16: - mkasm(u, "0x" FMT64 "x", (uint64_t)(( u->pc + op->lval.sword ) & 0xffff) ); - break; - case 32: - mkasm(u, "0x" FMT64 "x", (uint64_t)(( u->pc + op->lval.sdword ) & 0xfffffffful) ); - break; - default:break; - } - break; - - case UD_OP_PTR: - switch (op->size) { - case 32: - mkasm(u, "word 0x%x:0x%x", op->lval.ptr.seg, - op->lval.ptr.off & 0xFFFF); - break; - case 48: - mkasm(u, "dword 0x%x:0x%lx", op->lval.ptr.seg, - (unsigned long)op->lval.ptr.off); - break; - } - break; - - case UD_OP_CONST: - if (syn_cast) opr_cast(u, op); - mkasm(u, "%d", op->lval.udword); - break; - - default: return; + default: return; } } @@ -181,98 +128,104 @@ static void gen_operand(struct ud* u, struct ud_operand* op, int syn_cast) * translates to intel syntax * ============================================================================= */ -extern void ud_translate_intel(struct ud* u) +extern void +ud_translate_intel(struct ud* u) { - /* -- prefixes -- */ - /* check if P_OSO prefix is used */ - if (! P_OSO(u->itab_entry->prefix) && u->pfx_opr) { - switch (u->dis_mode) { - case 16: - mkasm(u, "o32 "); - break; - case 32: - case 64: - mkasm(u, "o16 "); - break; - } + if (!P_OSO(u->itab_entry->prefix) && u->pfx_opr) { + switch (u->dis_mode) { + case 16: ud_asmprintf(u, "o32 "); break; + case 32: + case 64: ud_asmprintf(u, "o16 "); break; + } } /* check if P_ASO prefix was used */ - if (! P_ASO(u->itab_entry->prefix) && u->pfx_adr) { - switch (u->dis_mode) { - case 16: - mkasm(u, "a32 "); - break; - case 32: - mkasm(u, "a16 "); - break; - case 64: - mkasm(u, "a32 "); - break; - } + if (!P_ASO(u->itab_entry->prefix) && u->pfx_adr) { + switch (u->dis_mode) { + case 16: ud_asmprintf(u, "a32 "); break; + case 32: ud_asmprintf(u, "a16 "); break; + case 64: ud_asmprintf(u, "a32 "); break; + } } - if ( u->pfx_seg && - u->operand[0].type != UD_OP_MEM && - u->operand[1].type != UD_OP_MEM ) { - mkasm(u, "%s ", ud_reg_tab[u->pfx_seg - UD_R_AL]); - } - if (u->pfx_lock) - mkasm(u, "lock "); - if (u->pfx_rep) - mkasm(u, "rep "); - if (u->pfx_repne) - mkasm(u, "repne "); + if (u->pfx_seg && + u->operand[0].type != UD_OP_MEM && + u->operand[1].type != UD_OP_MEM ) { + ud_asmprintf(u, "%s ", ud_reg_tab[u->pfx_seg - UD_R_AL]); + } + + if (u->pfx_lock) { + ud_asmprintf(u, "lock "); + } + if (u->pfx_rep) { + ud_asmprintf(u, "rep "); + } else if (u->pfx_repe) { + ud_asmprintf(u, "repe "); + } else if (u->pfx_repne) { + ud_asmprintf(u, "repne "); + } /* print the instruction mnemonic */ - mkasm(u, "%s ", ud_lookup_mnemonic(u->mnemonic)); + ud_asmprintf(u, "%s", ud_lookup_mnemonic(u->mnemonic)); - /* operand 1 */ if (u->operand[0].type != UD_NONE) { int cast = 0; - if ( u->operand[0].type == UD_OP_IMM && - u->operand[1].type == UD_NONE ) - cast = u->c1; - if ( u->operand[0].type == UD_OP_MEM ) { - cast = u->c1; - if ( u->operand[1].type == UD_OP_IMM || - u->operand[1].type == UD_OP_CONST ) - cast = 1; - if ( u->operand[1].type == UD_NONE ) - cast = 1; - if ( ( u->operand[0].size != u->operand[1].size ) && u->operand[1].size ) - cast = 1; - } else if ( u->operand[ 0 ].type == UD_OP_JIMM ) { - if ( u->operand[ 0 ].size > 8 ) cast = 1; + ud_asmprintf(u, " "); + if (u->operand[0].type == UD_OP_MEM) { + if (u->operand[1].type == UD_OP_IMM || + u->operand[1].type == UD_OP_CONST || + u->operand[1].type == UD_NONE || + (u->operand[0].size != u->operand[1].size)) { + cast = 1; + } else if (u->operand[1].type == UD_OP_REG && + u->operand[1].base == UD_R_CL) { + switch (u->mnemonic) { + case UD_Ircl: + case UD_Irol: + case UD_Iror: + case UD_Ircr: + case UD_Ishl: + case UD_Ishr: + case UD_Isar: + cast = 1; + break; + default: break; + } + } } - gen_operand(u, &u->operand[0], cast); + gen_operand(u, &u->operand[0], cast); } - /* operand 2 */ + if (u->operand[1].type != UD_NONE) { int cast = 0; - mkasm(u, ", "); - if ( u->operand[1].type == UD_OP_MEM ) { - cast = u->c1; - - if ( u->operand[0].type != UD_OP_REG ) - cast = 1; - if ( u->operand[0].size != u->operand[1].size && u->operand[1].size ) - cast = 1; - if ( u->operand[0].type == UD_OP_REG && - u->operand[0].base >= UD_R_ES && - u->operand[0].base <= UD_R_GS ) - cast = 0; + ud_asmprintf(u, ", "); + if (u->operand[1].type == UD_OP_MEM && + u->operand[0].size != u->operand[1].size && + !ud_opr_is_sreg(&u->operand[0])) { + cast = 1; } - gen_operand(u, &u->operand[1], cast ); + gen_operand(u, &u->operand[1], cast); } - /* operand 3 */ if (u->operand[2].type != UD_NONE) { - mkasm(u, ", "); - gen_operand(u, &u->operand[2], u->c3); + int cast = 0; + ud_asmprintf(u, ", "); + if (u->operand[2].type == UD_OP_MEM && + u->operand[2].size != u->operand[1].size) { + cast = 1; + } + gen_operand(u, &u->operand[2], cast); + } + + if (u->operand[3].type != UD_NONE) { + ud_asmprintf(u, ", "); + gen_operand(u, &u->operand[3], 0); } } #endif // USE(UDIS86) +/* +vim: set ts=2 sw=2 expandtab +*/ diff --git a/Source/JavaScriptCore/disassembler/udis86/udis86_syn.c b/Source/JavaScriptCore/disassembler/udis86/udis86_syn.c index 31a45ea5c..4417d9997 100644 --- a/Source/JavaScriptCore/disassembler/udis86/udis86_syn.c +++ b/Source/JavaScriptCore/disassembler/udis86/udis86_syn.c @@ -1,6 +1,6 @@ /* udis86 - libudis86/syn.c * - * Copyright (c) 2002-2009 Vivek Thampi + * Copyright (c) 2002-2013 Vivek Thampi * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, @@ -28,59 +28,192 @@ #if USE(UDIS86) -/* ----------------------------------------------------------------------------- - * Intel Register Table - Order Matters (types.h)! - * ----------------------------------------------------------------------------- +#include "udis86_types.h" +#include "udis86_decode.h" +#include "udis86_syn.h" +#include "udis86_udint.h" + +/* + * Register Table - Order Matters (types.h)! + * */ const char* ud_reg_tab[] = { - "al", "cl", "dl", "bl", - "ah", "ch", "dh", "bh", - "spl", "bpl", "sil", "dil", - "r8b", "r9b", "r10b", "r11b", - "r12b", "r13b", "r14b", "r15b", - - "ax", "cx", "dx", "bx", - "sp", "bp", "si", "di", - "r8w", "r9w", "r10w", "r11w", - "r12w", "r13W" , "r14w", "r15w", - - "eax", "ecx", "edx", "ebx", - "esp", "ebp", "esi", "edi", - "r8d", "r9d", "r10d", "r11d", - "r12d", "r13d", "r14d", "r15d", - - "rax", "rcx", "rdx", "rbx", - "rsp", "rbp", "rsi", "rdi", - "r8", "r9", "r10", "r11", - "r12", "r13", "r14", "r15", - - "es", "cs", "ss", "ds", - "fs", "gs", - - "cr0", "cr1", "cr2", "cr3", - "cr4", "cr5", "cr6", "cr7", - "cr8", "cr9", "cr10", "cr11", - "cr12", "cr13", "cr14", "cr15", - - "dr0", "dr1", "dr2", "dr3", - "dr4", "dr5", "dr6", "dr7", - "dr8", "dr9", "dr10", "dr11", - "dr12", "dr13", "dr14", "dr15", - - "mm0", "mm1", "mm2", "mm3", - "mm4", "mm5", "mm6", "mm7", - - "st0", "st1", "st2", "st3", - "st4", "st5", "st6", "st7", - - "xmm0", "xmm1", "xmm2", "xmm3", - "xmm4", "xmm5", "xmm6", "xmm7", - "xmm8", "xmm9", "xmm10", "xmm11", - "xmm12", "xmm13", "xmm14", "xmm15", + "al", "cl", "dl", "bl", + "ah", "ch", "dh", "bh", + "spl", "bpl", "sil", "dil", + "r8b", "r9b", "r10b", "r11b", + "r12b", "r13b", "r14b", "r15b", + + "ax", "cx", "dx", "bx", + "sp", "bp", "si", "di", + "r8w", "r9w", "r10w", "r11w", + "r12w", "r13w", "r14w", "r15w", + + "eax", "ecx", "edx", "ebx", + "esp", "ebp", "esi", "edi", + "r8d", "r9d", "r10d", "r11d", + "r12d", "r13d", "r14d", "r15d", + + "rax", "rcx", "rdx", "rbx", + "rsp", "rbp", "rsi", "rdi", + "r8", "r9", "r10", "r11", + "r12", "r13", "r14", "r15", + + "es", "cs", "ss", "ds", + "fs", "gs", + + "cr0", "cr1", "cr2", "cr3", + "cr4", "cr5", "cr6", "cr7", + "cr8", "cr9", "cr10", "cr11", + "cr12", "cr13", "cr14", "cr15", + + "dr0", "dr1", "dr2", "dr3", + "dr4", "dr5", "dr6", "dr7", + "dr8", "dr9", "dr10", "dr11", + "dr12", "dr13", "dr14", "dr15", + + "mm0", "mm1", "mm2", "mm3", + "mm4", "mm5", "mm6", "mm7", + + "st0", "st1", "st2", "st3", + "st4", "st5", "st6", "st7", + + "xmm0", "xmm1", "xmm2", "xmm3", + "xmm4", "xmm5", "xmm6", "xmm7", + "xmm8", "xmm9", "xmm10", "xmm11", + "xmm12", "xmm13", "xmm14", "xmm15", + + "ymm0", "ymm1", "ymm2", "ymm3", + "ymm4", "ymm5", "ymm6", "ymm7", + "ymm8", "ymm9", "ymm10", "ymm11", + "ymm12", "ymm13", "ymm14", "ymm15", "rip" }; + +uint64_t +ud_syn_rel_target(struct ud *u, struct ud_operand *opr) +{ + const uint64_t trunc_mask = 0xffffffffffffffffull >> (64 - u->opr_mode); + switch (opr->size) { + case 8 : return (u->pc + opr->lval.sbyte) & trunc_mask; + case 16: return (u->pc + opr->lval.sword) & trunc_mask; + case 32: return (u->pc + opr->lval.sdword) & trunc_mask; + default: UD_ASSERT(!"invalid relative offset size."); + return 0ull; + } +} + + +/* + * asmprintf + * Printf style function for printing translated assembly + * output. Returns the number of characters written and + * moves the buffer pointer forward. On an overflow, + * returns a negative number and truncates the output. + */ +int +ud_asmprintf(struct ud *u, const char *fmt, ...) +{ + int ret; + int avail; + va_list ap; + va_start(ap, fmt); + avail = u->asm_buf_size - u->asm_buf_fill - 1 /* nullchar */; + ret = vsnprintf((char*) u->asm_buf + u->asm_buf_fill, avail, fmt, ap); + if (ret < 0 || ret > avail) { + u->asm_buf_fill = u->asm_buf_size - 1; + } else { + u->asm_buf_fill += ret; + } + va_end(ap); + return ret; +} + + +void +ud_syn_print_addr(struct ud *u, uint64_t addr) +{ + const char *name = NULL; + if (u->sym_resolver) { + int64_t offset = 0; + name = u->sym_resolver(u, addr, &offset); + if (name) { + if (offset) { + ud_asmprintf(u, "%s%+" FMT64 "d", name, offset); + } else { + ud_asmprintf(u, "%s", name); + } + return; + } + } + ud_asmprintf(u, "0x%" FMT64 "x", addr); +} + + +void +ud_syn_print_imm(struct ud* u, const struct ud_operand *op) +{ + uint64_t v; + if (op->_oprcode == OP_sI && op->size != u->opr_mode) { + if (op->size == 8) { + v = (int64_t)op->lval.sbyte; + } else { + UD_ASSERT(op->size == 32); + v = (int64_t)op->lval.sdword; + } + if (u->opr_mode < 64) { + v = v & ((1ull << u->opr_mode) - 1ull); + } + } else { + switch (op->size) { + case 8 : v = op->lval.ubyte; break; + case 16: v = op->lval.uword; break; + case 32: v = op->lval.udword; break; + case 64: v = op->lval.uqword; break; + default: UD_ASSERT(!"invalid offset"); v = 0; /* keep cc happy */ + } + } + ud_asmprintf(u, "0x%" FMT64 "x", v); +} + + +void +ud_syn_print_mem_disp(struct ud* u, const struct ud_operand *op, int sign) +{ + UD_ASSERT(op->offset != 0); + if (op->base == UD_NONE && op->index == UD_NONE) { + uint64_t v; + UD_ASSERT(op->scale == UD_NONE && op->offset != 8); + /* unsigned mem-offset */ + switch (op->offset) { + case 16: v = op->lval.uword; break; + case 32: v = op->lval.udword; break; + case 64: v = op->lval.uqword; break; + default: UD_ASSERT(!"invalid offset"); v = 0; /* keep cc happy */ + } + ud_asmprintf(u, "0x%" FMT64 "x", v); + } else { + int64_t v; + UD_ASSERT(op->offset != 64); + switch (op->offset) { + case 8 : v = op->lval.sbyte; break; + case 16: v = op->lval.sword; break; + case 32: v = op->lval.sdword; break; + default: UD_ASSERT(!"invalid offset"); v = 0; /* keep cc happy */ + } + if (v < 0) { + ud_asmprintf(u, "-0x%" FMT64 "x", -v); + } else if (v > 0) { + ud_asmprintf(u, "%s0x%" FMT64 "x", sign? "+" : "", v); + } + } +} + #endif // USE(UDIS86) +/* +vim: set ts=2 sw=2 expandtab +*/ diff --git a/Source/JavaScriptCore/disassembler/udis86/udis86_syn.h b/Source/JavaScriptCore/disassembler/udis86/udis86_syn.h index e8636163e..712ec37ae 100644 --- a/Source/JavaScriptCore/disassembler/udis86/udis86_syn.h +++ b/Source/JavaScriptCore/disassembler/udis86/udis86_syn.h @@ -27,21 +27,27 @@ #define UD_SYN_H #include "udis86_types.h" -#include <wtf/Assertions.h> - #ifndef __UD_STANDALONE__ # include <stdarg.h> #endif /* __UD_STANDALONE__ */ extern const char* ud_reg_tab[]; -static void mkasm(struct ud* u, const char* fmt, ...) WTF_ATTRIBUTE_PRINTF(2, 3); -static void mkasm(struct ud* u, const char* fmt, ...) -{ - va_list ap; - va_start(ap, fmt); - u->insn_fill += vsnprintf((char*) u->insn_buffer + u->insn_fill, UD_STRING_BUFFER_SIZE - u->insn_fill, fmt, ap); - va_end(ap); -} +uint64_t ud_syn_rel_target(struct ud*, struct ud_operand*); +#ifdef __GNUC__ +int ud_asmprintf(struct ud *u, const char *fmt, ...) + __attribute__ ((format (printf, 2, 3))); +#else +int ud_asmprintf(struct ud *u, const char *fmt, ...); #endif + +void ud_syn_print_addr(struct ud *u, uint64_t addr); +void ud_syn_print_imm(struct ud* u, const struct ud_operand *op); +void ud_syn_print_mem_disp(struct ud* u, const struct ud_operand *, int sign); + +#endif /* UD_SYN_H */ + +/* +vim: set ts=2 sw=2 expandtab +*/ diff --git a/Source/JavaScriptCore/disassembler/udis86/udis86_types.h b/Source/JavaScriptCore/disassembler/udis86/udis86_types.h index 176bf6d73..604f08e51 100644 --- a/Source/JavaScriptCore/disassembler/udis86/udis86_types.h +++ b/Source/JavaScriptCore/disassembler/udis86/udis86_types.h @@ -1,6 +1,6 @@ /* udis86 - libudis86/types.h * - * Copyright (c) 2002-2009 Vivek Thampi + * Copyright (c) 2002-2013 Vivek Thampi * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, @@ -26,9 +26,23 @@ #ifndef UD_TYPES_H #define UD_TYPES_H -#ifndef __UD_STANDALONE__ +#ifdef __KERNEL__ + /* + * -D__KERNEL__ is automatically passed on the command line when + * building something as part of the Linux kernel. Assume standalone + * mode. + */ +# include <linux/kernel.h> +# include <linux/string.h> +# ifndef __UD_STANDALONE__ +# define __UD_STANDALONE__ 1 +# endif +#endif /* __KERNEL__ */ + +#if !defined(__UD_STANDALONE__) +# include <stdint.h> # include <stdio.h> -#endif /* __UD_STANDALONE__ */ +#endif /* gcc specific extensions */ #ifdef __GNUC__ @@ -37,26 +51,6 @@ # define UD_ATTR_PACKED #endif /* UD_ATTR_PACKED */ -#ifdef _MSC_VER -# define FMT64 "%I64" - typedef unsigned __int8 uint8_t; - typedef unsigned __int16 uint16_t; - typedef unsigned __int32 uint32_t; - typedef unsigned __int64 uint64_t; - typedef __int8 int8_t; - typedef __int16 int16_t; - typedef __int32 int32_t; - typedef __int64 int64_t; -#else -# if defined(__GNU_LIBRARY__) && defined(__WORDSIZE) && (__WORDSIZE == 64) -# define FMT64 "%l" -# else -# define FMT64 "%ll" -# endif -# ifndef __UD_STANDALONE__ -# include <inttypes.h> -# endif /* __UD_STANDALONE__ */ -#endif /* ----------------------------------------------------------------------------- * All possible "types" of objects in udis86. Order is Important! @@ -67,152 +61,176 @@ enum ud_type UD_NONE, /* 8 bit GPRs */ - UD_R_AL, UD_R_CL, UD_R_DL, UD_R_BL, - UD_R_AH, UD_R_CH, UD_R_DH, UD_R_BH, - UD_R_SPL, UD_R_BPL, UD_R_SIL, UD_R_DIL, - UD_R_R8B, UD_R_R9B, UD_R_R10B, UD_R_R11B, - UD_R_R12B, UD_R_R13B, UD_R_R14B, UD_R_R15B, + UD_R_AL, UD_R_CL, UD_R_DL, UD_R_BL, + UD_R_AH, UD_R_CH, UD_R_DH, UD_R_BH, + UD_R_SPL, UD_R_BPL, UD_R_SIL, UD_R_DIL, + UD_R_R8B, UD_R_R9B, UD_R_R10B, UD_R_R11B, + UD_R_R12B, UD_R_R13B, UD_R_R14B, UD_R_R15B, /* 16 bit GPRs */ - UD_R_AX, UD_R_CX, UD_R_DX, UD_R_BX, - UD_R_SP, UD_R_BP, UD_R_SI, UD_R_DI, - UD_R_R8W, UD_R_R9W, UD_R_R10W, UD_R_R11W, - UD_R_R12W, UD_R_R13W, UD_R_R14W, UD_R_R15W, - + UD_R_AX, UD_R_CX, UD_R_DX, UD_R_BX, + UD_R_SP, UD_R_BP, UD_R_SI, UD_R_DI, + UD_R_R8W, UD_R_R9W, UD_R_R10W, UD_R_R11W, + UD_R_R12W, UD_R_R13W, UD_R_R14W, UD_R_R15W, + /* 32 bit GPRs */ - UD_R_EAX, UD_R_ECX, UD_R_EDX, UD_R_EBX, - UD_R_ESP, UD_R_EBP, UD_R_ESI, UD_R_EDI, - UD_R_R8D, UD_R_R9D, UD_R_R10D, UD_R_R11D, - UD_R_R12D, UD_R_R13D, UD_R_R14D, UD_R_R15D, - + UD_R_EAX, UD_R_ECX, UD_R_EDX, UD_R_EBX, + UD_R_ESP, UD_R_EBP, UD_R_ESI, UD_R_EDI, + UD_R_R8D, UD_R_R9D, UD_R_R10D, UD_R_R11D, + UD_R_R12D, UD_R_R13D, UD_R_R14D, UD_R_R15D, + /* 64 bit GPRs */ - UD_R_RAX, UD_R_RCX, UD_R_RDX, UD_R_RBX, - UD_R_RSP, UD_R_RBP, UD_R_RSI, UD_R_RDI, - UD_R_R8, UD_R_R9, UD_R_R10, UD_R_R11, - UD_R_R12, UD_R_R13, UD_R_R14, UD_R_R15, + UD_R_RAX, UD_R_RCX, UD_R_RDX, UD_R_RBX, + UD_R_RSP, UD_R_RBP, UD_R_RSI, UD_R_RDI, + UD_R_R8, UD_R_R9, UD_R_R10, UD_R_R11, + UD_R_R12, UD_R_R13, UD_R_R14, UD_R_R15, /* segment registers */ - UD_R_ES, UD_R_CS, UD_R_SS, UD_R_DS, - UD_R_FS, UD_R_GS, + UD_R_ES, UD_R_CS, UD_R_SS, UD_R_DS, + UD_R_FS, UD_R_GS, /* control registers*/ - UD_R_CR0, UD_R_CR1, UD_R_CR2, UD_R_CR3, - UD_R_CR4, UD_R_CR5, UD_R_CR6, UD_R_CR7, - UD_R_CR8, UD_R_CR9, UD_R_CR10, UD_R_CR11, - UD_R_CR12, UD_R_CR13, UD_R_CR14, UD_R_CR15, - + UD_R_CR0, UD_R_CR1, UD_R_CR2, UD_R_CR3, + UD_R_CR4, UD_R_CR5, UD_R_CR6, UD_R_CR7, + UD_R_CR8, UD_R_CR9, UD_R_CR10, UD_R_CR11, + UD_R_CR12, UD_R_CR13, UD_R_CR14, UD_R_CR15, + /* debug registers */ - UD_R_DR0, UD_R_DR1, UD_R_DR2, UD_R_DR3, - UD_R_DR4, UD_R_DR5, UD_R_DR6, UD_R_DR7, - UD_R_DR8, UD_R_DR9, UD_R_DR10, UD_R_DR11, - UD_R_DR12, UD_R_DR13, UD_R_DR14, UD_R_DR15, + UD_R_DR0, UD_R_DR1, UD_R_DR2, UD_R_DR3, + UD_R_DR4, UD_R_DR5, UD_R_DR6, UD_R_DR7, + UD_R_DR8, UD_R_DR9, UD_R_DR10, UD_R_DR11, + UD_R_DR12, UD_R_DR13, UD_R_DR14, UD_R_DR15, /* mmx registers */ - UD_R_MM0, UD_R_MM1, UD_R_MM2, UD_R_MM3, - UD_R_MM4, UD_R_MM5, UD_R_MM6, UD_R_MM7, + UD_R_MM0, UD_R_MM1, UD_R_MM2, UD_R_MM3, + UD_R_MM4, UD_R_MM5, UD_R_MM6, UD_R_MM7, /* x87 registers */ - UD_R_ST0, UD_R_ST1, UD_R_ST2, UD_R_ST3, - UD_R_ST4, UD_R_ST5, UD_R_ST6, UD_R_ST7, + UD_R_ST0, UD_R_ST1, UD_R_ST2, UD_R_ST3, + UD_R_ST4, UD_R_ST5, UD_R_ST6, UD_R_ST7, /* extended multimedia registers */ - UD_R_XMM0, UD_R_XMM1, UD_R_XMM2, UD_R_XMM3, - UD_R_XMM4, UD_R_XMM5, UD_R_XMM6, UD_R_XMM7, - UD_R_XMM8, UD_R_XMM9, UD_R_XMM10, UD_R_XMM11, - UD_R_XMM12, UD_R_XMM13, UD_R_XMM14, UD_R_XMM15, + UD_R_XMM0, UD_R_XMM1, UD_R_XMM2, UD_R_XMM3, + UD_R_XMM4, UD_R_XMM5, UD_R_XMM6, UD_R_XMM7, + UD_R_XMM8, UD_R_XMM9, UD_R_XMM10, UD_R_XMM11, + UD_R_XMM12, UD_R_XMM13, UD_R_XMM14, UD_R_XMM15, + + /* 256B multimedia registers */ + UD_R_YMM0, UD_R_YMM1, UD_R_YMM2, UD_R_YMM3, + UD_R_YMM4, UD_R_YMM5, UD_R_YMM6, UD_R_YMM7, + UD_R_YMM8, UD_R_YMM9, UD_R_YMM10, UD_R_YMM11, + UD_R_YMM12, UD_R_YMM13, UD_R_YMM14, UD_R_YMM15, UD_R_RIP, /* Operand Types */ - UD_OP_REG, UD_OP_MEM, UD_OP_PTR, UD_OP_IMM, - UD_OP_JIMM, UD_OP_CONST + UD_OP_REG, UD_OP_MEM, UD_OP_PTR, UD_OP_IMM, + UD_OP_JIMM, UD_OP_CONST }; #include "udis86_itab.h" +union ud_lval { + int8_t sbyte; + uint8_t ubyte; + int16_t sword; + uint16_t uword; + int32_t sdword; + uint32_t udword; + int64_t sqword; + uint64_t uqword; + struct { + uint16_t seg; + uint32_t off; + } ptr; +}; + /* ----------------------------------------------------------------------------- * struct ud_operand - Disassembled instruction Operand. * ----------------------------------------------------------------------------- */ -struct ud_operand -{ - enum ud_type type; - uint8_t size; - union { - int8_t sbyte; - uint8_t ubyte; - int16_t sword; - uint16_t uword; - int32_t sdword; - uint32_t udword; - int64_t sqword; - uint64_t uqword; - - struct { - uint16_t seg; - uint32_t off; - } ptr; - } lval; - - enum ud_type base; - enum ud_type index; - uint8_t offset; - uint8_t scale; +struct ud_operand { + enum ud_type type; + uint16_t size; + enum ud_type base; + enum ud_type index; + uint8_t scale; + uint8_t offset; + union ud_lval lval; + /* + * internal use only + */ + uint64_t _legacy; /* this will be removed in 1.8 */ + uint8_t _oprcode; }; -#define UD_STRING_BUFFER_SIZE 64 - /* ----------------------------------------------------------------------------- * struct ud - The udis86 object. * ----------------------------------------------------------------------------- */ struct ud { - int (*inp_hook) (struct ud*); - uint8_t inp_curr; - uint8_t inp_fill; + /* + * input buffering + */ + int (*inp_hook) (struct ud*); #ifndef __UD_STANDALONE__ - FILE* inp_file; + FILE* inp_file; #endif - uint8_t inp_ctr; - uint8_t* inp_buff; - uint8_t* inp_buff_end; - uint8_t inp_end; - void (*translator)(struct ud*); - uint64_t insn_offset; - char insn_hexcode[32]; - char insn_buffer[UD_STRING_BUFFER_SIZE]; - unsigned int insn_fill; - uint8_t dis_mode; - uint64_t pc; - uint8_t vendor; - struct map_entry* mapen; - enum ud_mnemonic_code mnemonic; - struct ud_operand operand[3]; - uint8_t error; - uint8_t pfx_rex; - uint8_t pfx_seg; - uint8_t pfx_opr; - uint8_t pfx_adr; - uint8_t pfx_lock; - uint8_t pfx_rep; - uint8_t pfx_repe; - uint8_t pfx_repne; - uint8_t pfx_insn; - uint8_t default64; - uint8_t opr_mode; - uint8_t adr_mode; - uint8_t br_far; - uint8_t br_near; - uint8_t implicit_addr; - uint8_t c1; - uint8_t c2; - uint8_t c3; - uint8_t inp_cache[256]; - uint8_t inp_sess[64]; - uint8_t have_modrm; - uint8_t modrm; - void * user_opaque_data; + const uint8_t* inp_buf; + size_t inp_buf_size; + size_t inp_buf_index; + uint8_t inp_curr; + size_t inp_ctr; + uint8_t inp_sess[64]; + int inp_end; + int inp_peek; + + void (*translator)(struct ud*); + uint64_t insn_offset; + char insn_hexcode[64]; + + /* + * Assembly output buffer + */ + char *asm_buf; + size_t asm_buf_size; + size_t asm_buf_fill; + char asm_buf_int[128]; + + /* + * Symbol resolver for use in the translation phase. + */ + const char* (*sym_resolver)(struct ud*, uint64_t addr, int64_t *offset); + + uint8_t dis_mode; + uint64_t pc; + uint8_t vendor; + enum ud_mnemonic_code mnemonic; + struct ud_operand operand[4]; + uint8_t error; + uint8_t _rex; + uint8_t pfx_rex; + uint8_t pfx_seg; + uint8_t pfx_opr; + uint8_t pfx_adr; + uint8_t pfx_lock; + uint8_t pfx_str; + uint8_t pfx_rep; + uint8_t pfx_repe; + uint8_t pfx_repne; + uint8_t opr_mode; + uint8_t adr_mode; + uint8_t br_far; + uint8_t br_near; + uint8_t have_modrm; + uint8_t modrm; + uint8_t modrm_offset; + uint8_t vex_op; + uint8_t vex_b1; + uint8_t vex_b2; + uint8_t primary_opcode; + void * user_opaque_data; struct ud_itab_entry * itab_entry; struct ud_lookup_table_list_entry *le; }; @@ -221,22 +239,22 @@ struct ud * Type-definitions * ----------------------------------------------------------------------------- */ -typedef enum ud_type ud_type_t; -typedef enum ud_mnemonic_code ud_mnemonic_code_t; +typedef enum ud_type ud_type_t; +typedef enum ud_mnemonic_code ud_mnemonic_code_t; -typedef struct ud ud_t; -typedef struct ud_operand ud_operand_t; +typedef struct ud ud_t; +typedef struct ud_operand ud_operand_t; -#define UD_SYN_INTEL ud_translate_intel -#define UD_SYN_ATT ud_translate_att -#define UD_EOI -1 -#define UD_INP_CACHE_SZ 32 -#define UD_VENDOR_AMD 0 -#define UD_VENDOR_INTEL 1 -#define UD_VENDOR_ANY 2 - -#define bail_out(ud,error_code) longjmp( (ud)->bailout, error_code ) -#define try_decode(ud) if ( setjmp( (ud)->bailout ) == 0 ) -#define catch_error() else +#define UD_SYN_INTEL ud_translate_intel +#define UD_SYN_ATT ud_translate_att +#define UD_EOI (-1) +#define UD_INP_CACHE_SZ 32 +#define UD_VENDOR_AMD 0 +#define UD_VENDOR_INTEL 1 +#define UD_VENDOR_ANY 2 #endif + +/* +vim: set ts=2 sw=2 expandtab +*/ diff --git a/Source/JavaScriptCore/disassembler/udis86/udis86_udint.h b/Source/JavaScriptCore/disassembler/udis86/udis86_udint.h new file mode 100644 index 000000000..d166b9173 --- /dev/null +++ b/Source/JavaScriptCore/disassembler/udis86/udis86_udint.h @@ -0,0 +1,98 @@ +/* udis86 - libudis86/udint.h -- definitions for internal use only + * + * Copyright (c) 2002-2009 Vivek Thampi + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _UDINT_H_ +#define _UDINT_H_ + +#include "udis86_types.h" + +#ifdef HAVE_CONFIG_H +# include <config.h> +#endif /* HAVE_CONFIG_H */ + +#if defined(UD_DEBUG) && HAVE_ASSERT_H +# define UD_ASSERT(_x) ASSERT(_x) +#else +# define UD_ASSERT(_x) +#endif /* !HAVE_ASSERT_H */ + +#if defined(UD_DEBUG) + #define UDERR(u, msg) \ + do { \ + (u)->error = 1; \ + fprintf(stderr, "decode-error: %s:%d: %s", \ + __FILE__, __LINE__, (msg)); \ + } while (0) +#else + #define UDERR(u, m) \ + do { \ + (u)->error = 1; \ + } while (0) +#endif /* !LOGERR */ + +#define UD_RETURN_ON_ERROR(u) \ + do { \ + if ((u)->error != 0) { \ + return (u)->error; \ + } \ + } while (0) + +#define UD_RETURN_WITH_ERROR(u, m) \ + do { \ + UDERR(u, m); \ + return (u)->error; \ + } while (0) + +#ifndef __UD_STANDALONE__ +# define UD_NON_STANDALONE(x) x +#else +# define UD_NON_STANDALONE(x) +#endif + +/* printf formatting int64 specifier */ +#ifdef FMT64 +# undef FMT64 +#endif +#if defined(_MSC_VER) || defined(__BORLANDC__) +# define FMT64 "I64" +#else +# if defined(__APPLE__) +# define FMT64 "ll" +# elif defined(__amd64__) || defined(__x86_64__) +# define FMT64 "l" +# else +# define FMT64 "ll" +# endif /* !x64 */ +#endif + +/* define an inline macro */ +#if defined(_MSC_VER) || defined(__BORLANDC__) +# define UD_INLINE __inline /* MS Visual Studio requires __inline + instead of inline for C code */ +#else +# define UD_INLINE inline +#endif + +#endif /* _UDINT_H_ */ |