diff options
Diffstat (limited to 'Source/JavaScriptCore/assembler')
| -rw-r--r-- | Source/JavaScriptCore/assembler/ARMAssembler.cpp | 80 | ||||
| -rw-r--r-- | Source/JavaScriptCore/assembler/ARMAssembler.h | 154 | ||||
| -rw-r--r-- | Source/JavaScriptCore/assembler/MacroAssemblerARM.cpp | 22 | ||||
| -rw-r--r-- | Source/JavaScriptCore/assembler/MacroAssemblerARM.h | 246 |
4 files changed, 251 insertions, 251 deletions
diff --git a/Source/JavaScriptCore/assembler/ARMAssembler.cpp b/Source/JavaScriptCore/assembler/ARMAssembler.cpp index 533640ea8..9655557a5 100644 --- a/Source/JavaScriptCore/assembler/ARMAssembler.cpp +++ b/Source/JavaScriptCore/assembler/ARMAssembler.cpp @@ -187,11 +187,11 @@ int ARMAssembler::genInt(int reg, ARMWord imm, bool positive) } if (positive) { - mov_r(reg, imm1); - orr_r(reg, reg, imm2); + mov(reg, imm1); + orr(reg, reg, imm2); } else { - mvn_r(reg, imm1); - bic_r(reg, reg, imm2); + mvn(reg, imm1); + bic(reg, reg, imm2); } return 1; @@ -210,7 +210,7 @@ ARMWord ARMAssembler::getImm(ARMWord imm, int tmpReg, bool invert) if (tmp != InvalidImmediate) { if (invert) return tmp | Op2InvertedImmediate; - mvn_r(tmpReg, tmp); + mvn(tmpReg, tmp); return tmpReg; } @@ -224,13 +224,13 @@ void ARMAssembler::moveImm(ARMWord imm, int dest) // Do it by 1 instruction tmp = getOp2(imm); if (tmp != InvalidImmediate) { - mov_r(dest, tmp); + mov(dest, tmp); return; } tmp = getOp2(~imm); if (tmp != InvalidImmediate) { - mvn_r(dest, tmp); + mvn(dest, tmp); return; } @@ -242,11 +242,11 @@ ARMWord ARMAssembler::encodeComplexImm(ARMWord imm, int dest) #if WTF_ARM_ARCH_AT_LEAST(7) ARMWord tmp = getImm16Op2(imm); if (tmp != InvalidImmediate) { - movw_r(dest, tmp); + movw(dest, tmp); return dest; } - movw_r(dest, getImm16Op2(imm & 0xffff)); - movt_r(dest, getImm16Op2(imm >> 16)); + movw(dest, getImm16Op2(imm & 0xffff)); + movt(dest, getImm16Op2(imm >> 16)); return dest; #else // Do it by 2 instruction @@ -255,7 +255,7 @@ ARMWord ARMAssembler::encodeComplexImm(ARMWord imm, int dest) if (genInt(dest, ~imm, false)) return dest; - ldr_imm(dest, imm); + ldrImmediate(dest, imm); return dest; #endif } @@ -266,23 +266,23 @@ void ARMAssembler::dataTransfer32(DataTransferTypeA transferType, RegisterID src { if (offset >= 0) { if (offset <= 0xfff) - dtr_u(transferType, srcDst, base, offset); + dtrUp(transferType, srcDst, base, offset); else if (offset <= 0xfffff) { - add_r(ARMRegisters::S0, base, Op2Immediate | (offset >> 12) | (10 << 8)); - dtr_u(transferType, srcDst, ARMRegisters::S0, (offset & 0xfff)); + add(ARMRegisters::S0, base, Op2Immediate | (offset >> 12) | (10 << 8)); + dtrUp(transferType, srcDst, ARMRegisters::S0, (offset & 0xfff)); } else { moveImm(offset, ARMRegisters::S0); - dtr_ur(transferType, srcDst, base, ARMRegisters::S0); + dtrUpRegister(transferType, srcDst, base, ARMRegisters::S0); } } else { if (offset >= -0xfff) - dtr_d(transferType, srcDst, base, -offset); + dtrDown(transferType, srcDst, base, -offset); else if (offset >= -0xfffff) { - sub_r(ARMRegisters::S0, base, Op2Immediate | (-offset >> 12) | (10 << 8)); - dtr_d(transferType, srcDst, ARMRegisters::S0, (-offset & 0xfff)); + sub(ARMRegisters::S0, base, Op2Immediate | (-offset >> 12) | (10 << 8)); + dtrDown(transferType, srcDst, ARMRegisters::S0, (-offset & 0xfff)); } else { moveImm(offset, ARMRegisters::S0); - dtr_ur(transferType, srcDst, base, ARMRegisters::S0); + dtrUpRegister(transferType, srcDst, base, ARMRegisters::S0); } } } @@ -293,11 +293,11 @@ void ARMAssembler::baseIndexTransfer32(DataTransferTypeA transferType, RegisterI ARMWord op2 = lsl(index, scale); if (!offset) { - dtr_ur(transferType, srcDst, base, op2); + dtrUpRegister(transferType, srcDst, base, op2); return; } - add_r(ARMRegisters::S1, base, op2); + add(ARMRegisters::S1, base, op2); dataTransfer32(transferType, srcDst, ARMRegisters::S1, offset); } @@ -305,23 +305,23 @@ void ARMAssembler::dataTransfer16(DataTransferTypeB transferType, RegisterID src { if (offset >= 0) { if (offset <= 0xff) - dtrh_u(transferType, srcDst, base, getOp2Half(offset)); + halfDtrUp(transferType, srcDst, base, getOp2Half(offset)); else if (offset <= 0xffff) { - add_r(ARMRegisters::S0, base, Op2Immediate | (offset >> 8) | (12 << 8)); - dtrh_u(transferType, srcDst, ARMRegisters::S0, getOp2Half(offset & 0xff)); + add(ARMRegisters::S0, base, Op2Immediate | (offset >> 8) | (12 << 8)); + halfDtrUp(transferType, srcDst, ARMRegisters::S0, getOp2Half(offset & 0xff)); } else { moveImm(offset, ARMRegisters::S0); - dtrh_ur(transferType, srcDst, base, ARMRegisters::S0); + halfDtrUpRegister(transferType, srcDst, base, ARMRegisters::S0); } } else { if (offset >= -0xff) - dtrh_d(transferType, srcDst, base, getOp2Half(-offset)); + halfDtrDown(transferType, srcDst, base, getOp2Half(-offset)); else if (offset >= -0xffff) { - sub_r(ARMRegisters::S0, base, Op2Immediate | (-offset >> 8) | (12 << 8)); - dtrh_d(transferType, srcDst, ARMRegisters::S0, getOp2Half(-offset & 0xff)); + sub(ARMRegisters::S0, base, Op2Immediate | (-offset >> 8) | (12 << 8)); + halfDtrDown(transferType, srcDst, ARMRegisters::S0, getOp2Half(-offset & 0xff)); } else { moveImm(offset, ARMRegisters::S0); - dtrh_ur(transferType, srcDst, base, ARMRegisters::S0); + halfDtrUpRegister(transferType, srcDst, base, ARMRegisters::S0); } } } @@ -329,11 +329,11 @@ void ARMAssembler::dataTransfer16(DataTransferTypeB transferType, RegisterID src void ARMAssembler::baseIndexTransfer16(DataTransferTypeB transferType, RegisterID srcDst, RegisterID base, RegisterID index, int scale, int32_t offset) { if (!scale && !offset) { - dtrh_ur(transferType, srcDst, base, index); + halfDtrUpRegister(transferType, srcDst, base, index); return; } - add_r(ARMRegisters::S1, base, lsl(index, scale)); + add(ARMRegisters::S1, base, lsl(index, scale)); dataTransfer16(transferType, srcDst, ARMRegisters::S1, offset); } @@ -342,36 +342,36 @@ void ARMAssembler::dataTransferFloat(DataTransferTypeFloat transferType, FPRegis // VFP cannot directly access memory that is not four-byte-aligned if (!(offset & 0x3)) { if (offset <= 0x3ff && offset >= 0) { - fdtr_u(transferType, srcDst, base, offset >> 2); + doubleDtrUp(transferType, srcDst, base, offset >> 2); return; } if (offset <= 0x3ffff && offset >= 0) { - add_r(ARMRegisters::S0, base, Op2Immediate | (offset >> 10) | (11 << 8)); - fdtr_u(transferType, srcDst, ARMRegisters::S0, (offset >> 2) & 0xff); + add(ARMRegisters::S0, base, Op2Immediate | (offset >> 10) | (11 << 8)); + doubleDtrUp(transferType, srcDst, ARMRegisters::S0, (offset >> 2) & 0xff); return; } offset = -offset; if (offset <= 0x3ff && offset >= 0) { - fdtr_d(transferType, srcDst, base, offset >> 2); + doubleDtrDown(transferType, srcDst, base, offset >> 2); return; } if (offset <= 0x3ffff && offset >= 0) { - sub_r(ARMRegisters::S0, base, Op2Immediate | (offset >> 10) | (11 << 8)); - fdtr_d(transferType, srcDst, ARMRegisters::S0, (offset >> 2) & 0xff); + sub(ARMRegisters::S0, base, Op2Immediate | (offset >> 10) | (11 << 8)); + doubleDtrDown(transferType, srcDst, ARMRegisters::S0, (offset >> 2) & 0xff); return; } offset = -offset; } moveImm(offset, ARMRegisters::S0); - add_r(ARMRegisters::S0, ARMRegisters::S0, base); - fdtr_u(transferType, srcDst, ARMRegisters::S0, 0); + add(ARMRegisters::S0, ARMRegisters::S0, base); + doubleDtrUp(transferType, srcDst, ARMRegisters::S0, 0); } void ARMAssembler::baseIndexTransferFloat(DataTransferTypeFloat transferType, FPRegisterID srcDst, RegisterID base, RegisterID index, int scale, int32_t offset) { - add_r(ARMRegisters::S1, base, lsl(index, scale)); + add(ARMRegisters::S1, base, lsl(index, scale)); dataTransferFloat(transferType, srcDst, ARMRegisters::S1, offset); } diff --git a/Source/JavaScriptCore/assembler/ARMAssembler.h b/Source/JavaScriptCore/assembler/ARMAssembler.h index ac918f31e..38d0c5e6d 100644 --- a/Source/JavaScriptCore/assembler/ARMAssembler.h +++ b/Source/JavaScriptCore/assembler/ARMAssembler.h @@ -268,355 +268,355 @@ namespace JSC { | (sm >> 1) | ((sm & 0x1) << 5)); } - void and_r(int rd, int rn, ARMWord op2, Condition cc = AL) + void bitAnd(int rd, int rn, ARMWord op2, Condition cc = AL) { emitInstruction(toARMWord(cc) | AND, rd, rn, op2); } - void ands_r(int rd, int rn, ARMWord op2, Condition cc = AL) + void bitAnds(int rd, int rn, ARMWord op2, Condition cc = AL) { emitInstruction(toARMWord(cc) | AND | SetConditionalCodes, rd, rn, op2); } - void eor_r(int rd, int rn, ARMWord op2, Condition cc = AL) + void eor(int rd, int rn, ARMWord op2, Condition cc = AL) { emitInstruction(toARMWord(cc) | EOR, rd, rn, op2); } - void eors_r(int rd, int rn, ARMWord op2, Condition cc = AL) + void eors(int rd, int rn, ARMWord op2, Condition cc = AL) { emitInstruction(toARMWord(cc) | EOR | SetConditionalCodes, rd, rn, op2); } - void sub_r(int rd, int rn, ARMWord op2, Condition cc = AL) + void sub(int rd, int rn, ARMWord op2, Condition cc = AL) { emitInstruction(toARMWord(cc) | SUB, rd, rn, op2); } - void subs_r(int rd, int rn, ARMWord op2, Condition cc = AL) + void subs(int rd, int rn, ARMWord op2, Condition cc = AL) { emitInstruction(toARMWord(cc) | SUB | SetConditionalCodes, rd, rn, op2); } - void rsb_r(int rd, int rn, ARMWord op2, Condition cc = AL) + void rsb(int rd, int rn, ARMWord op2, Condition cc = AL) { emitInstruction(toARMWord(cc) | RSB, rd, rn, op2); } - void rsbs_r(int rd, int rn, ARMWord op2, Condition cc = AL) + void rsbs(int rd, int rn, ARMWord op2, Condition cc = AL) { emitInstruction(toARMWord(cc) | RSB | SetConditionalCodes, rd, rn, op2); } - void add_r(int rd, int rn, ARMWord op2, Condition cc = AL) + void add(int rd, int rn, ARMWord op2, Condition cc = AL) { emitInstruction(toARMWord(cc) | ADD, rd, rn, op2); } - void adds_r(int rd, int rn, ARMWord op2, Condition cc = AL) + void adds(int rd, int rn, ARMWord op2, Condition cc = AL) { emitInstruction(toARMWord(cc) | ADD | SetConditionalCodes, rd, rn, op2); } - void adc_r(int rd, int rn, ARMWord op2, Condition cc = AL) + void adc(int rd, int rn, ARMWord op2, Condition cc = AL) { emitInstruction(toARMWord(cc) | ADC, rd, rn, op2); } - void adcs_r(int rd, int rn, ARMWord op2, Condition cc = AL) + void adcs(int rd, int rn, ARMWord op2, Condition cc = AL) { emitInstruction(toARMWord(cc) | ADC | SetConditionalCodes, rd, rn, op2); } - void sbc_r(int rd, int rn, ARMWord op2, Condition cc = AL) + void sbc(int rd, int rn, ARMWord op2, Condition cc = AL) { emitInstruction(toARMWord(cc) | SBC, rd, rn, op2); } - void sbcs_r(int rd, int rn, ARMWord op2, Condition cc = AL) + void sbcs(int rd, int rn, ARMWord op2, Condition cc = AL) { emitInstruction(toARMWord(cc) | SBC | SetConditionalCodes, rd, rn, op2); } - void rsc_r(int rd, int rn, ARMWord op2, Condition cc = AL) + void rsc(int rd, int rn, ARMWord op2, Condition cc = AL) { emitInstruction(toARMWord(cc) | RSC, rd, rn, op2); } - void rscs_r(int rd, int rn, ARMWord op2, Condition cc = AL) + void rscs(int rd, int rn, ARMWord op2, Condition cc = AL) { emitInstruction(toARMWord(cc) | RSC | SetConditionalCodes, rd, rn, op2); } - void tst_r(int rn, ARMWord op2, Condition cc = AL) + void tst(int rn, ARMWord op2, Condition cc = AL) { emitInstruction(toARMWord(cc) | TST | SetConditionalCodes, 0, rn, op2); } - void teq_r(int rn, ARMWord op2, Condition cc = AL) + void teq(int rn, ARMWord op2, Condition cc = AL) { emitInstruction(toARMWord(cc) | TEQ | SetConditionalCodes, 0, rn, op2); } - void cmp_r(int rn, ARMWord op2, Condition cc = AL) + void cmp(int rn, ARMWord op2, Condition cc = AL) { emitInstruction(toARMWord(cc) | CMP | SetConditionalCodes, 0, rn, op2); } - void cmn_r(int rn, ARMWord op2, Condition cc = AL) + void cmn(int rn, ARMWord op2, Condition cc = AL) { emitInstruction(toARMWord(cc) | CMN | SetConditionalCodes, 0, rn, op2); } - void orr_r(int rd, int rn, ARMWord op2, Condition cc = AL) + void orr(int rd, int rn, ARMWord op2, Condition cc = AL) { emitInstruction(toARMWord(cc) | ORR, rd, rn, op2); } - void orrs_r(int rd, int rn, ARMWord op2, Condition cc = AL) + void orrs(int rd, int rn, ARMWord op2, Condition cc = AL) { emitInstruction(toARMWord(cc) | ORR | SetConditionalCodes, rd, rn, op2); } - void mov_r(int rd, ARMWord op2, Condition cc = AL) + void mov(int rd, ARMWord op2, Condition cc = AL) { emitInstruction(toARMWord(cc) | MOV, rd, ARMRegisters::r0, op2); } #if WTF_ARM_ARCH_AT_LEAST(7) - void movw_r(int rd, ARMWord op2, Condition cc = AL) + void movw(int rd, ARMWord op2, Condition cc = AL) { ASSERT((op2 | 0xf0fff) == 0xf0fff); m_buffer.putInt(toARMWord(cc) | MOVW | RD(rd) | op2); } - void movt_r(int rd, ARMWord op2, Condition cc = AL) + void movt(int rd, ARMWord op2, Condition cc = AL) { ASSERT((op2 | 0xf0fff) == 0xf0fff); m_buffer.putInt(toARMWord(cc) | MOVT | RD(rd) | op2); } #endif - void movs_r(int rd, ARMWord op2, Condition cc = AL) + void movs(int rd, ARMWord op2, Condition cc = AL) { emitInstruction(toARMWord(cc) | MOV | SetConditionalCodes, rd, ARMRegisters::r0, op2); } - void bic_r(int rd, int rn, ARMWord op2, Condition cc = AL) + void bic(int rd, int rn, ARMWord op2, Condition cc = AL) { emitInstruction(toARMWord(cc) | BIC, rd, rn, op2); } - void bics_r(int rd, int rn, ARMWord op2, Condition cc = AL) + void bics(int rd, int rn, ARMWord op2, Condition cc = AL) { emitInstruction(toARMWord(cc) | BIC | SetConditionalCodes, rd, rn, op2); } - void mvn_r(int rd, ARMWord op2, Condition cc = AL) + void mvn(int rd, ARMWord op2, Condition cc = AL) { emitInstruction(toARMWord(cc) | MVN, rd, ARMRegisters::r0, op2); } - void mvns_r(int rd, ARMWord op2, Condition cc = AL) + void mvns(int rd, ARMWord op2, Condition cc = AL) { emitInstruction(toARMWord(cc) | MVN | SetConditionalCodes, rd, ARMRegisters::r0, op2); } - void mul_r(int rd, int rn, int rm, Condition cc = AL) + void mul(int rd, int rn, int rm, Condition cc = AL) { m_buffer.putInt(toARMWord(cc) | MUL | RN(rd) | RS(rn) | RM(rm)); } - void muls_r(int rd, int rn, int rm, Condition cc = AL) + void muls(int rd, int rn, int rm, Condition cc = AL) { m_buffer.putInt(toARMWord(cc) | MUL | SetConditionalCodes | RN(rd) | RS(rn) | RM(rm)); } - void mull_r(int rdhi, int rdlo, int rn, int rm, Condition cc = AL) + void mull(int rdhi, int rdlo, int rn, int rm, Condition cc = AL) { m_buffer.putInt(toARMWord(cc) | MULL | RN(rdhi) | RD(rdlo) | RS(rn) | RM(rm)); } - void vmov_f64_r(int dd, int dm, Condition cc = AL) + void vmov_f64(int dd, int dm, Condition cc = AL) { emitDoublePrecisionInstruction(toARMWord(cc) | VMOV_F64, dd, 0, dm); } - void vadd_f64_r(int dd, int dn, int dm, Condition cc = AL) + void vadd_f64(int dd, int dn, int dm, Condition cc = AL) { emitDoublePrecisionInstruction(toARMWord(cc) | VADD_F64, dd, dn, dm); } - void vdiv_f64_r(int dd, int dn, int dm, Condition cc = AL) + void vdiv_f64(int dd, int dn, int dm, Condition cc = AL) { emitDoublePrecisionInstruction(toARMWord(cc) | VDIV_F64, dd, dn, dm); } - void vsub_f64_r(int dd, int dn, int dm, Condition cc = AL) + void vsub_f64(int dd, int dn, int dm, Condition cc = AL) { emitDoublePrecisionInstruction(toARMWord(cc) | VSUB_F64, dd, dn, dm); } - void vmul_f64_r(int dd, int dn, int dm, Condition cc = AL) + void vmul_f64(int dd, int dn, int dm, Condition cc = AL) { emitDoublePrecisionInstruction(toARMWord(cc) | VMUL_F64, dd, dn, dm); } - void vcmp_f64_r(int dd, int dm, Condition cc = AL) + void vcmp_f64(int dd, int dm, Condition cc = AL) { emitDoublePrecisionInstruction(toARMWord(cc) | VCMP_F64, dd, 0, dm); } - void vsqrt_f64_r(int dd, int dm, Condition cc = AL) + void vsqrt_f64(int dd, int dm, Condition cc = AL) { emitDoublePrecisionInstruction(toARMWord(cc) | VSQRT_F64, dd, 0, dm); } - void vabs_f64_r(int dd, int dm, Condition cc = AL) + void vabs_f64(int dd, int dm, Condition cc = AL) { emitDoublePrecisionInstruction(toARMWord(cc) | VABS_F64, dd, 0, dm); } - void vneg_f64_r(int dd, int dm, Condition cc = AL) + void vneg_f64(int dd, int dm, Condition cc = AL) { emitDoublePrecisionInstruction(toARMWord(cc) | VNEG_F64, dd, 0, dm); } - void ldr_imm(int rd, ARMWord imm, Condition cc = AL) + void ldrImmediate(int rd, ARMWord imm, Condition cc = AL) { m_buffer.putIntWithConstantInt(toARMWord(cc) | LoadUint32 | DataTransferUp | RN(ARMRegisters::pc) | RD(rd), imm, true); } - void ldr_un_imm(int rd, ARMWord imm, Condition cc = AL) + void ldrUniqueImmediate(int rd, ARMWord imm, Condition cc = AL) { m_buffer.putIntWithConstantInt(toARMWord(cc) | LoadUint32 | DataTransferUp | RN(ARMRegisters::pc) | RD(rd), imm); } - void dtr_u(DataTransferTypeA transferType, int rd, int rb, ARMWord op2, Condition cc = AL) + void dtrUp(DataTransferTypeA transferType, int rd, int rb, ARMWord op2, Condition cc = AL) { emitInstruction(toARMWord(cc) | transferType | DataTransferUp, rd, rb, op2); } - void dtr_ur(DataTransferTypeA transferType, int rd, int rb, int rm, Condition cc = AL) + void dtrUpRegister(DataTransferTypeA transferType, int rd, int rb, int rm, Condition cc = AL) { emitInstruction(toARMWord(cc) | transferType | DataTransferUp | Op2IsRegisterArgument, rd, rb, rm); } - void dtr_d(DataTransferTypeA transferType, int rd, int rb, ARMWord op2, Condition cc = AL) + void dtrDown(DataTransferTypeA transferType, int rd, int rb, ARMWord op2, Condition cc = AL) { emitInstruction(toARMWord(cc) | transferType, rd, rb, op2); } - void dtr_dr(DataTransferTypeA transferType, int rd, int rb, int rm, Condition cc = AL) + void dtrDownRegister(DataTransferTypeA transferType, int rd, int rb, int rm, Condition cc = AL) { emitInstruction(toARMWord(cc) | transferType | Op2IsRegisterArgument, rd, rb, rm); } - void dtrh_u(DataTransferTypeB transferType, int rd, int rb, ARMWord op2, Condition cc = AL) + void halfDtrUp(DataTransferTypeB transferType, int rd, int rb, ARMWord op2, Condition cc = AL) { emitInstruction(toARMWord(cc) | transferType | DataTransferUp, rd, rb, op2); } - void dtrh_ur(DataTransferTypeB transferType, int rd, int rn, int rm, Condition cc = AL) + void halfDtrUpRegister(DataTransferTypeB transferType, int rd, int rn, int rm, Condition cc = AL) { emitInstruction(toARMWord(cc) | transferType | DataTransferUp, rd, rn, rm); } - void dtrh_d(DataTransferTypeB transferType, int rd, int rb, ARMWord op2, Condition cc = AL) + void halfDtrDown(DataTransferTypeB transferType, int rd, int rb, ARMWord op2, Condition cc = AL) { emitInstruction(toARMWord(cc) | transferType, rd, rb, op2); } - void dtrh_dr(DataTransferTypeB transferType, int rd, int rn, int rm, Condition cc = AL) + void halfDtrDownRegister(DataTransferTypeB transferType, int rd, int rn, int rm, Condition cc = AL) { emitInstruction(toARMWord(cc) | transferType, rd, rn, rm); } - void fdtr_u(DataTransferTypeFloat type, int rd, int rb, ARMWord op2, Condition cc = AL) + void doubleDtrUp(DataTransferTypeFloat type, int rd, int rb, ARMWord op2, Condition cc = AL) { ASSERT(op2 <= 0xff && rd <= 15); /* Only d0-d15 and s0, s2, s4 ... s30 are supported. */ m_buffer.putInt(toARMWord(cc) | DataTransferUp | type | (rd << 12) | RN(rb) | op2); } - void fdtr_d(DataTransferTypeFloat type, int rd, int rb, ARMWord op2, Condition cc = AL) + void doubleDtrDown(DataTransferTypeFloat type, int rd, int rb, ARMWord op2, Condition cc = AL) { ASSERT(op2 <= 0xff && rd <= 15); /* Only d0-d15 and s0, s2, s4 ... s30 are supported. */ m_buffer.putInt(toARMWord(cc) | type | (rd << 12) | RN(rb) | op2); } - void push_r(int reg, Condition cc = AL) + void push(int reg, Condition cc = AL) { ASSERT(ARMWord(reg) <= 0xf); m_buffer.putInt(toARMWord(cc) | StoreUint32 | DataTransferWriteBack | RN(ARMRegisters::sp) | RD(reg) | 0x4); } - void pop_r(int reg, Condition cc = AL) + void pop(int reg, Condition cc = AL) { ASSERT(ARMWord(reg) <= 0xf); m_buffer.putInt(toARMWord(cc) | (LoadUint32 ^ DataTransferPostUpdate) | DataTransferUp | RN(ARMRegisters::sp) | RD(reg) | 0x4); } - inline void poke_r(int reg, Condition cc = AL) + inline void poke(int reg, Condition cc = AL) { - dtr_d(StoreUint32, ARMRegisters::sp, 0, reg, cc); + dtrDown(StoreUint32, ARMRegisters::sp, 0, reg, cc); } - inline void peek_r(int reg, Condition cc = AL) + inline void peek(int reg, Condition cc = AL) { - dtr_u(LoadUint32, reg, ARMRegisters::sp, 0, cc); + dtrUp(LoadUint32, reg, ARMRegisters::sp, 0, cc); } - void vmov_vfp64_r(int sm, int rt, int rt2, Condition cc = AL) + void vmov_vfp64(int sm, int rt, int rt2, Condition cc = AL) { ASSERT(rt != rt2); m_buffer.putInt(toARMWord(cc) | VMOV_VFP64 | RN(rt2) | RD(rt) | (sm & 0xf) | ((sm & 0x10) << (5 - 4))); } - void vmov_arm64_r(int rt, int rt2, int sm, Condition cc = AL) + void vmov_arm64(int rt, int rt2, int sm, Condition cc = AL) { ASSERT(rt != rt2); m_buffer.putInt(toARMWord(cc) | VMOV_ARM64 | RN(rt2) | RD(rt) | (sm & 0xf) | ((sm & 0x10) << (5 - 4))); } - void vmov_vfp32_r(int sn, int rt, Condition cc = AL) + void vmov_vfp32(int sn, int rt, Condition cc = AL) { ASSERT(rt <= 15); emitSinglePrecisionInstruction(toARMWord(cc) | VMOV_VFP32, rt << 1, sn, 0); } - void vmov_arm32_r(int rt, int sn, Condition cc = AL) + void vmov_arm32(int rt, int sn, Condition cc = AL) { ASSERT(rt <= 15); emitSinglePrecisionInstruction(toARMWord(cc) | VMOV_ARM32, rt << 1, sn, 0); } - void vcvt_f64_s32_r(int dd, int sm, Condition cc = AL) + void vcvt_f64_s32(int dd, int sm, Condition cc = AL) { ASSERT(!(sm & 0x1)); // sm must be divisible by 2 emitDoublePrecisionInstruction(toARMWord(cc) | VCVT_F64_S32, dd, 0, (sm >> 1)); } - void vcvt_s32_f64_r(int sd, int dm, Condition cc = AL) + void vcvt_s32_f64(int sd, int dm, Condition cc = AL) { ASSERT(!(sd & 0x1)); // sd must be divisible by 2 emitDoublePrecisionInstruction(toARMWord(cc) | VCVT_S32_F64, (sd >> 1), 0, dm); } - void vcvt_u32_f64_r(int sd, int dm, Condition cc = AL) + void vcvt_u32_f64(int sd, int dm, Condition cc = AL) { ASSERT(!(sd & 0x1)); // sd must be divisible by 2 emitDoublePrecisionInstruction(toARMWord(cc) | VCVT_U32_F64, (sd >> 1), 0, dm); } - void vcvt_f64_f32_r(int dd, int sm, Condition cc = AL) + void vcvt_f64_f32(int dd, int sm, Condition cc = AL) { ASSERT(dd <= 15 && sm <= 15); emitDoublePrecisionInstruction(toARMWord(cc) | VCVT_F64_F32, dd, 0, sm); } - void vcvt_f32_f64_r(int dd, int sm, Condition cc = AL) + void vcvt_f32_f64(int dd, int sm, Condition cc = AL) { ASSERT(dd <= 15 && sm <= 15); emitDoublePrecisionInstruction(toARMWord(cc) | VCVT_F32_F64, dd, 0, sm); @@ -627,7 +627,7 @@ namespace JSC { m_buffer.putInt(toARMWord(cc) | VMRS_APSR); } - void clz_r(int rd, int rm, Condition cc = AL) + void clz(int rd, int rm, Condition cc = AL) { m_buffer.putInt(toARMWord(cc) | CLZ | RD(rd) | RM(rm)); } @@ -674,21 +674,21 @@ namespace JSC { return reg | (value << 7) | 0x40; } - static ARMWord lsl_r(int reg, int shiftReg) + static ARMWord lslRegister(int reg, int shiftReg) { ASSERT(reg <= ARMRegisters::pc); ASSERT(shiftReg <= ARMRegisters::pc); return reg | (shiftReg << 8) | 0x10; } - static ARMWord lsr_r(int reg, int shiftReg) + static ARMWord lsrRegister(int reg, int shiftReg) { ASSERT(reg <= ARMRegisters::pc); ASSERT(shiftReg <= ARMRegisters::pc); return reg | (shiftReg << 8) | 0x30; } - static ARMWord asr_r(int reg, int shiftReg) + static ARMWord asrRegister(int reg, int shiftReg) { ASSERT(reg <= ARMRegisters::pc); ASSERT(shiftReg <= ARMRegisters::pc); @@ -742,7 +742,7 @@ namespace JSC { AssemblerLabel align(int alignment) { while (!m_buffer.isAligned(alignment)) - mov_r(ARMRegisters::r0, ARMRegisters::r0); + mov(ARMRegisters::r0, ARMRegisters::r0); return label(); } @@ -751,7 +751,7 @@ namespace JSC { { ensureSpace(sizeof(ARMWord), sizeof(ARMWord)); m_jumps.append(m_buffer.codeSize() | (useConstantPool & 0x1)); - ldr_un_imm(rd, InvalidBranchTarget, cc); + ldrUniqueImmediate(rd, InvalidBranchTarget, cc); return m_buffer.label(); } @@ -767,12 +767,12 @@ namespace JSC { // DFG assembly helpers for moving data between fp and registers. void vmov(RegisterID rd1, RegisterID rd2, FPRegisterID rn) { - vmov_arm64_r(rd1, rd2, rn); + vmov_arm64(rd1, rd2, rn); } void vmov(FPRegisterID rd, RegisterID rn1, RegisterID rn2) { - vmov_vfp64_r(rd, rn1, rn2); + vmov_vfp64(rd, rn1, rn2); } // Patching helpers diff --git a/Source/JavaScriptCore/assembler/MacroAssemblerARM.cpp b/Source/JavaScriptCore/assembler/MacroAssemblerARM.cpp index a251a4376..98dc3e987 100644 --- a/Source/JavaScriptCore/assembler/MacroAssemblerARM.cpp +++ b/Source/JavaScriptCore/assembler/MacroAssemblerARM.cpp @@ -76,21 +76,21 @@ void MacroAssemblerARM::load32WithUnalignedHalfWords(BaseIndex address, Register op2 = m_assembler.lsl(address.index, static_cast<int>(address.scale)); if (address.offset >= 0 && address.offset + 0x2 <= 0xff) { - m_assembler.add_r(ARMRegisters::S0, address.base, op2); - m_assembler.dtrh_u(ARMAssembler::LoadUint16, dest, ARMRegisters::S0, ARMAssembler::getOp2Half(address.offset)); - m_assembler.dtrh_u(ARMAssembler::LoadUint16, ARMRegisters::S0, ARMRegisters::S0, ARMAssembler::getOp2Half(address.offset + 0x2)); + m_assembler.add(ARMRegisters::S0, address.base, op2); + m_assembler.halfDtrUp(ARMAssembler::LoadUint16, dest, ARMRegisters::S0, ARMAssembler::getOp2Half(address.offset)); + m_assembler.halfDtrUp(ARMAssembler::LoadUint16, ARMRegisters::S0, ARMRegisters::S0, ARMAssembler::getOp2Half(address.offset + 0x2)); } else if (address.offset < 0 && address.offset >= -0xff) { - m_assembler.add_r(ARMRegisters::S0, address.base, op2); - m_assembler.dtrh_d(ARMAssembler::LoadUint16, dest, ARMRegisters::S0, ARMAssembler::getOp2Half(-address.offset)); - m_assembler.dtrh_d(ARMAssembler::LoadUint16, ARMRegisters::S0, ARMRegisters::S0, ARMAssembler::getOp2Half(-address.offset - 0x2)); + m_assembler.add(ARMRegisters::S0, address.base, op2); + m_assembler.halfDtrDown(ARMAssembler::LoadUint16, dest, ARMRegisters::S0, ARMAssembler::getOp2Half(-address.offset)); + m_assembler.halfDtrDown(ARMAssembler::LoadUint16, ARMRegisters::S0, ARMRegisters::S0, ARMAssembler::getOp2Half(-address.offset - 0x2)); } else { m_assembler.moveImm(address.offset, ARMRegisters::S0); - m_assembler.add_r(ARMRegisters::S0, ARMRegisters::S0, op2); - m_assembler.dtrh_ur(ARMAssembler::LoadUint16, dest, address.base, ARMRegisters::S0); - m_assembler.add_r(ARMRegisters::S0, ARMRegisters::S0, ARMAssembler::Op2Immediate | 0x2); - m_assembler.dtrh_ur(ARMAssembler::LoadUint16, ARMRegisters::S0, address.base, ARMRegisters::S0); + m_assembler.add(ARMRegisters::S0, ARMRegisters::S0, op2); + m_assembler.halfDtrUpRegister(ARMAssembler::LoadUint16, dest, address.base, ARMRegisters::S0); + m_assembler.add(ARMRegisters::S0, ARMRegisters::S0, ARMAssembler::Op2Immediate | 0x2); + m_assembler.halfDtrUpRegister(ARMAssembler::LoadUint16, ARMRegisters::S0, address.base, ARMRegisters::S0); } - m_assembler.orr_r(dest, dest, m_assembler.lsl(ARMRegisters::S0, 16)); + m_assembler.orr(dest, dest, m_assembler.lsl(ARMRegisters::S0, 16)); } #endif diff --git a/Source/JavaScriptCore/assembler/MacroAssemblerARM.h b/Source/JavaScriptCore/assembler/MacroAssemblerARM.h index 85d0ffbcc..295354119 100644 --- a/Source/JavaScriptCore/assembler/MacroAssemblerARM.h +++ b/Source/JavaScriptCore/assembler/MacroAssemblerARM.h @@ -86,12 +86,12 @@ public: void add32(RegisterID src, RegisterID dest) { - m_assembler.adds_r(dest, dest, src); + m_assembler.adds(dest, dest, src); } void add32(RegisterID op1, RegisterID op2, RegisterID dest) { - m_assembler.adds_r(dest, op1, op2); + m_assembler.adds(dest, op1, op2); } void add32(TrustedImm32 imm, Address address) @@ -103,13 +103,13 @@ public: void add32(TrustedImm32 imm, RegisterID dest) { - m_assembler.adds_r(dest, dest, m_assembler.getImm(imm.m_value, ARMRegisters::S0)); + m_assembler.adds(dest, dest, m_assembler.getImm(imm.m_value, ARMRegisters::S0)); } void add32(AbsoluteAddress src, RegisterID dest) { move(TrustedImmPtr(src.m_ptr), ARMRegisters::S1); - m_assembler.dtr_u(ARMAssembler::LoadUint32, ARMRegisters::S1, ARMRegisters::S1, 0); + m_assembler.dtrUp(ARMAssembler::LoadUint32, ARMRegisters::S1, ARMRegisters::S1, 0); add32(ARMRegisters::S1, dest); } @@ -121,35 +121,35 @@ public: void add32(RegisterID src, TrustedImm32 imm, RegisterID dest) { - m_assembler.adds_r(dest, src, m_assembler.getImm(imm.m_value, ARMRegisters::S0)); + m_assembler.adds(dest, src, m_assembler.getImm(imm.m_value, ARMRegisters::S0)); } void and32(RegisterID src, RegisterID dest) { - m_assembler.ands_r(dest, dest, src); + m_assembler.bitAnds(dest, dest, src); } void and32(RegisterID op1, RegisterID op2, RegisterID dest) { - m_assembler.ands_r(dest, op1, op2); + m_assembler.bitAnds(dest, op1, op2); } void and32(TrustedImm32 imm, RegisterID dest) { ARMWord w = m_assembler.getImm(imm.m_value, ARMRegisters::S0, true); if (w & ARMAssembler::Op2InvertedImmediate) - m_assembler.bics_r(dest, dest, w & ~ARMAssembler::Op2InvertedImmediate); + m_assembler.bics(dest, dest, w & ~ARMAssembler::Op2InvertedImmediate); else - m_assembler.ands_r(dest, dest, w); + m_assembler.bitAnds(dest, dest, w); } void and32(TrustedImm32 imm, RegisterID src, RegisterID dest) { ARMWord w = m_assembler.getImm(imm.m_value, ARMRegisters::S0, true); if (w & ARMAssembler::Op2InvertedImmediate) - m_assembler.bics_r(dest, src, w & ~ARMAssembler::Op2InvertedImmediate); + m_assembler.bics(dest, src, w & ~ARMAssembler::Op2InvertedImmediate); else - m_assembler.ands_r(dest, src, w); + m_assembler.bitAnds(dest, src, w); } void lshift32(RegisterID shiftAmount, RegisterID dest) @@ -160,19 +160,19 @@ public: void lshift32(RegisterID src, RegisterID shiftAmount, RegisterID dest) { ARMWord w = ARMAssembler::getOp2Byte(0x1f); - m_assembler.and_r(ARMRegisters::S0, shiftAmount, w); + m_assembler.bitAnd(ARMRegisters::S0, shiftAmount, w); - m_assembler.movs_r(dest, m_assembler.lsl_r(src, ARMRegisters::S0)); + m_assembler.movs(dest, m_assembler.lslRegister(src, ARMRegisters::S0)); } void lshift32(TrustedImm32 imm, RegisterID dest) { - m_assembler.movs_r(dest, m_assembler.lsl(dest, imm.m_value & 0x1f)); + m_assembler.movs(dest, m_assembler.lsl(dest, imm.m_value & 0x1f)); } void lshift32(RegisterID src, TrustedImm32 imm, RegisterID dest) { - m_assembler.movs_r(dest, m_assembler.lsl(src, imm.m_value & 0x1f)); + m_assembler.movs(dest, m_assembler.lsl(src, imm.m_value & 0x1f)); } void mul32(RegisterID op1, RegisterID op2, RegisterID dest) @@ -188,7 +188,7 @@ public: op2 = tmp; } } - m_assembler.muls_r(dest, op1, op2); + m_assembler.muls(dest, op1, op2); } void mul32(RegisterID src, RegisterID dest) @@ -199,32 +199,32 @@ public: void mul32(TrustedImm32 imm, RegisterID src, RegisterID dest) { move(imm, ARMRegisters::S0); - m_assembler.muls_r(dest, src, ARMRegisters::S0); + m_assembler.muls(dest, src, ARMRegisters::S0); } void neg32(RegisterID srcDest) { - m_assembler.rsbs_r(srcDest, srcDest, ARMAssembler::getOp2Byte(0)); + m_assembler.rsbs(srcDest, srcDest, ARMAssembler::getOp2Byte(0)); } void or32(RegisterID src, RegisterID dest) { - m_assembler.orrs_r(dest, dest, src); + m_assembler.orrs(dest, dest, src); } void or32(TrustedImm32 imm, RegisterID dest) { - m_assembler.orrs_r(dest, dest, m_assembler.getImm(imm.m_value, ARMRegisters::S0)); + m_assembler.orrs(dest, dest, m_assembler.getImm(imm.m_value, ARMRegisters::S0)); } void or32(TrustedImm32 imm, RegisterID src, RegisterID dest) { - m_assembler.orrs_r(dest, src, m_assembler.getImm(imm.m_value, ARMRegisters::S0)); + m_assembler.orrs(dest, src, m_assembler.getImm(imm.m_value, ARMRegisters::S0)); } void or32(RegisterID op1, RegisterID op2, RegisterID dest) { - m_assembler.orrs_r(dest, op1, op2); + m_assembler.orrs(dest, op1, op2); } void rshift32(RegisterID shiftAmount, RegisterID dest) @@ -235,9 +235,9 @@ public: void rshift32(RegisterID src, RegisterID shiftAmount, RegisterID dest) { ARMWord w = ARMAssembler::getOp2Byte(0x1f); - m_assembler.and_r(ARMRegisters::S0, shiftAmount, w); + m_assembler.bitAnd(ARMRegisters::S0, shiftAmount, w); - m_assembler.movs_r(dest, m_assembler.asr_r(src, ARMRegisters::S0)); + m_assembler.movs(dest, m_assembler.asrRegister(src, ARMRegisters::S0)); } void rshift32(TrustedImm32 imm, RegisterID dest) @@ -247,7 +247,7 @@ public: void rshift32(RegisterID src, TrustedImm32 imm, RegisterID dest) { - m_assembler.movs_r(dest, m_assembler.asr(src, imm.m_value & 0x1f)); + m_assembler.movs(dest, m_assembler.asr(src, imm.m_value & 0x1f)); } void urshift32(RegisterID shiftAmount, RegisterID dest) @@ -258,29 +258,29 @@ public: void urshift32(RegisterID src, RegisterID shiftAmount, RegisterID dest) { ARMWord w = ARMAssembler::getOp2Byte(0x1f); - m_assembler.and_r(ARMRegisters::S0, shiftAmount, w); + m_assembler.bitAnd(ARMRegisters::S0, shiftAmount, w); - m_assembler.movs_r(dest, m_assembler.lsr_r(src, ARMRegisters::S0)); + m_assembler.movs(dest, m_assembler.lsrRegister(src, ARMRegisters::S0)); } void urshift32(TrustedImm32 imm, RegisterID dest) { - m_assembler.movs_r(dest, m_assembler.lsr(dest, imm.m_value & 0x1f)); + m_assembler.movs(dest, m_assembler.lsr(dest, imm.m_value & 0x1f)); } void urshift32(RegisterID src, TrustedImm32 imm, RegisterID dest) { - m_assembler.movs_r(dest, m_assembler.lsr(src, imm.m_value & 0x1f)); + m_assembler.movs(dest, m_assembler.lsr(src, imm.m_value & 0x1f)); } void sub32(RegisterID src, RegisterID dest) { - m_assembler.subs_r(dest, dest, src); + m_assembler.subs(dest, dest, src); } void sub32(TrustedImm32 imm, RegisterID dest) { - m_assembler.subs_r(dest, dest, m_assembler.getImm(imm.m_value, ARMRegisters::S0)); + m_assembler.subs(dest, dest, m_assembler.getImm(imm.m_value, ARMRegisters::S0)); } void sub32(TrustedImm32 imm, Address address) @@ -298,39 +298,39 @@ public: void sub32(RegisterID src, TrustedImm32 imm, RegisterID dest) { - m_assembler.subs_r(dest, src, m_assembler.getImm(imm.m_value, ARMRegisters::S0)); + m_assembler.subs(dest, src, m_assembler.getImm(imm.m_value, ARMRegisters::S0)); } void xor32(RegisterID src, RegisterID dest) { - m_assembler.eors_r(dest, dest, src); + m_assembler.eors(dest, dest, src); } void xor32(RegisterID op1, RegisterID op2, RegisterID dest) { - m_assembler.eors_r(dest, op1, op2); + m_assembler.eors(dest, op1, op2); } void xor32(TrustedImm32 imm, RegisterID dest) { if (imm.m_value == -1) - m_assembler.mvns_r(dest, dest); + m_assembler.mvns(dest, dest); else - m_assembler.eors_r(dest, dest, m_assembler.getImm(imm.m_value, ARMRegisters::S0)); + m_assembler.eors(dest, dest, m_assembler.getImm(imm.m_value, ARMRegisters::S0)); } void xor32(TrustedImm32 imm, RegisterID src, RegisterID dest) { if (imm.m_value == -1) - m_assembler.mvns_r(dest, src); + m_assembler.mvns(dest, src); else - m_assembler.eors_r(dest, src, m_assembler.getImm(imm.m_value, ARMRegisters::S0)); + m_assembler.eors(dest, src, m_assembler.getImm(imm.m_value, ARMRegisters::S0)); } void countLeadingZeros32(RegisterID src, RegisterID dest) { #if WTF_ARM_ARCH_AT_LEAST(5) - m_assembler.clz_r(dest, src); + m_assembler.clz(dest, src); #else UNUSED_PARAM(src); UNUSED_PARAM(dest); @@ -396,15 +396,15 @@ public: { ConvertibleLoadLabel result(this); ASSERT(address.offset >= 0 && address.offset <= 255); - m_assembler.dtr_u(ARMAssembler::LoadUint32, dest, address.base, address.offset); + m_assembler.dtrUp(ARMAssembler::LoadUint32, dest, address.base, address.offset); return result; } DataLabel32 load32WithAddressOffsetPatch(Address address, RegisterID dest) { DataLabel32 dataLabel(this); - m_assembler.ldr_un_imm(ARMRegisters::S0, 0); - m_assembler.dtr_ur(ARMAssembler::LoadUint32, dest, address.base, ARMRegisters::S0); + m_assembler.ldrUniqueImmediate(ARMRegisters::S0, 0); + m_assembler.dtrUpRegister(ARMAssembler::LoadUint32, dest, address.base, ARMRegisters::S0); return dataLabel; } @@ -418,17 +418,17 @@ public: DataLabelCompact dataLabel(this); ASSERT(isCompactPtrAlignedAddressOffset(address.offset)); if (address.offset >= 0) - m_assembler.dtr_u(ARMAssembler::LoadUint32, dest, address.base, address.offset); + m_assembler.dtrUp(ARMAssembler::LoadUint32, dest, address.base, address.offset); else - m_assembler.dtr_d(ARMAssembler::LoadUint32, dest, address.base, address.offset); + m_assembler.dtrDown(ARMAssembler::LoadUint32, dest, address.base, address.offset); return dataLabel; } DataLabel32 store32WithAddressOffsetPatch(RegisterID src, Address address) { DataLabel32 dataLabel(this); - m_assembler.ldr_un_imm(ARMRegisters::S0, 0); - m_assembler.dtr_ur(ARMAssembler::StoreUint32, src, address.base, ARMRegisters::S0); + m_assembler.ldrUniqueImmediate(ARMRegisters::S0, 0); + m_assembler.dtrUpRegister(ARMAssembler::StoreUint32, src, address.base, ARMRegisters::S0); return dataLabel; } @@ -466,25 +466,25 @@ public: void store32(RegisterID src, void* address) { - m_assembler.ldr_un_imm(ARMRegisters::S0, reinterpret_cast<ARMWord>(address)); - m_assembler.dtr_u(ARMAssembler::StoreUint32, src, ARMRegisters::S0, 0); + m_assembler.ldrUniqueImmediate(ARMRegisters::S0, reinterpret_cast<ARMWord>(address)); + m_assembler.dtrUp(ARMAssembler::StoreUint32, src, ARMRegisters::S0, 0); } void store32(TrustedImm32 imm, void* address) { - m_assembler.ldr_un_imm(ARMRegisters::S0, reinterpret_cast<ARMWord>(address)); + m_assembler.ldrUniqueImmediate(ARMRegisters::S0, reinterpret_cast<ARMWord>(address)); m_assembler.moveImm(imm.m_value, ARMRegisters::S1); - m_assembler.dtr_u(ARMAssembler::StoreUint32, ARMRegisters::S1, ARMRegisters::S0, 0); + m_assembler.dtrUp(ARMAssembler::StoreUint32, ARMRegisters::S1, ARMRegisters::S0, 0); } void pop(RegisterID dest) { - m_assembler.pop_r(dest); + m_assembler.pop(dest); } void push(RegisterID src) { - m_assembler.push_r(src); + m_assembler.push(src); } void push(Address address) @@ -507,7 +507,7 @@ public: void move(RegisterID src, RegisterID dest) { if (src != dest) - m_assembler.mov_r(dest, src); + m_assembler.mov(dest, src); } void move(TrustedImmPtr imm, RegisterID dest) @@ -517,9 +517,9 @@ public: void swap(RegisterID reg1, RegisterID reg2) { - m_assembler.mov_r(ARMRegisters::S0, reg1); - m_assembler.mov_r(reg1, reg2); - m_assembler.mov_r(reg2, ARMRegisters::S0); + m_assembler.mov(ARMRegisters::S0, reg1); + m_assembler.mov(reg1, reg2); + m_assembler.mov(reg2, ARMRegisters::S0); } void signExtend32ToPtr(RegisterID src, RegisterID dest) @@ -549,7 +549,7 @@ public: Jump branch32(RelationalCondition cond, RegisterID left, RegisterID right, int useConstantPool = 0) { - m_assembler.cmp_r(left, right); + m_assembler.cmp(left, right); return Jump(m_assembler.jmp(ARMCondition(cond), useConstantPool)); } @@ -557,9 +557,9 @@ public: { ARMWord tmp = (right.m_value == 0x80000000) ? ARMAssembler::InvalidImmediate : m_assembler.getOp2(-right.m_value); if (tmp != ARMAssembler::InvalidImmediate) - m_assembler.cmn_r(left, tmp); + m_assembler.cmn(left, tmp); else - m_assembler.cmp_r(left, m_assembler.getImm(right.m_value, ARMRegisters::S0)); + m_assembler.cmp(left, m_assembler.getImm(right.m_value, ARMRegisters::S0)); return Jump(m_assembler.jmp(ARMCondition(cond), useConstantPool)); } @@ -609,7 +609,7 @@ public: Jump branchTest32(ResultCondition cond, RegisterID reg, RegisterID mask) { ASSERT((cond == Zero) || (cond == NonZero)); - m_assembler.tst_r(reg, mask); + m_assembler.tst(reg, mask); return Jump(m_assembler.jmp(ARMCondition(cond))); } @@ -618,9 +618,9 @@ public: ASSERT((cond == Zero) || (cond == NonZero)); ARMWord w = m_assembler.getImm(mask.m_value, ARMRegisters::S0, true); if (w & ARMAssembler::Op2InvertedImmediate) - m_assembler.bics_r(ARMRegisters::S0, reg, w & ~ARMAssembler::Op2InvertedImmediate); + m_assembler.bics(ARMRegisters::S0, reg, w & ~ARMAssembler::Op2InvertedImmediate); else - m_assembler.tst_r(reg, w); + m_assembler.tst(reg, w); return Jump(m_assembler.jmp(ARMCondition(cond))); } @@ -705,8 +705,8 @@ public: op2 = tmp; } } - m_assembler.mull_r(ARMRegisters::S1, dest, op1, op2); - m_assembler.cmp_r(ARMRegisters::S1, m_assembler.asr(dest, 31)); + m_assembler.mull(ARMRegisters::S1, dest, op1, op2); + m_assembler.cmp(ARMRegisters::S1, m_assembler.asr(dest, 31)); } Jump branchMul32(ResultCondition cond, RegisterID src1, RegisterID src2, RegisterID dest) @@ -763,7 +763,7 @@ public: Jump branchSub32(ResultCondition cond, RegisterID op1, RegisterID op2, RegisterID dest) { ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero)); - m_assembler.subs_r(dest, op1, op2); + m_assembler.subs(dest, op1, op2); return Jump(m_assembler.jmp(ARMCondition(cond))); } @@ -809,16 +809,16 @@ public: void compare32(RelationalCondition cond, RegisterID left, RegisterID right, RegisterID dest) { - m_assembler.cmp_r(left, right); - m_assembler.mov_r(dest, ARMAssembler::getOp2Byte(0)); - m_assembler.mov_r(dest, ARMAssembler::getOp2Byte(1), ARMCondition(cond)); + m_assembler.cmp(left, right); + m_assembler.mov(dest, ARMAssembler::getOp2Byte(0)); + m_assembler.mov(dest, ARMAssembler::getOp2Byte(1), ARMCondition(cond)); } void compare32(RelationalCondition cond, RegisterID left, TrustedImm32 right, RegisterID dest) { - m_assembler.cmp_r(left, m_assembler.getImm(right.m_value, ARMRegisters::S0)); - m_assembler.mov_r(dest, ARMAssembler::getOp2Byte(0)); - m_assembler.mov_r(dest, ARMAssembler::getOp2Byte(1), ARMCondition(cond)); + m_assembler.cmp(left, m_assembler.getImm(right.m_value, ARMRegisters::S0)); + m_assembler.mov(dest, ARMAssembler::getOp2Byte(0)); + m_assembler.mov(dest, ARMAssembler::getOp2Byte(1), ARMCondition(cond)); } void compare8(RelationalCondition cond, Address left, TrustedImm32 right, RegisterID dest) @@ -830,11 +830,11 @@ public: void test32(ResultCondition cond, RegisterID reg, TrustedImm32 mask, RegisterID dest) { if (mask.m_value == -1) - m_assembler.cmp_r(0, reg); + m_assembler.cmp(0, reg); else - m_assembler.tst_r(reg, m_assembler.getImm(mask.m_value, ARMRegisters::S0)); - m_assembler.mov_r(dest, ARMAssembler::getOp2Byte(0)); - m_assembler.mov_r(dest, ARMAssembler::getOp2Byte(1), ARMCondition(cond)); + m_assembler.tst(reg, m_assembler.getImm(mask.m_value, ARMRegisters::S0)); + m_assembler.mov(dest, ARMAssembler::getOp2Byte(0)); + m_assembler.mov(dest, ARMAssembler::getOp2Byte(1), ARMCondition(cond)); } void test32(ResultCondition cond, Address address, TrustedImm32 mask, RegisterID dest) @@ -851,31 +851,31 @@ public: void add32(TrustedImm32 imm, RegisterID src, RegisterID dest) { - m_assembler.add_r(dest, src, m_assembler.getImm(imm.m_value, ARMRegisters::S0)); + m_assembler.add(dest, src, m_assembler.getImm(imm.m_value, ARMRegisters::S0)); } void add32(TrustedImm32 imm, AbsoluteAddress address) { - m_assembler.ldr_un_imm(ARMRegisters::S1, reinterpret_cast<ARMWord>(address.m_ptr)); - m_assembler.dtr_u(ARMAssembler::LoadUint32, ARMRegisters::S1, ARMRegisters::S1, 0); + m_assembler.ldrUniqueImmediate(ARMRegisters::S1, reinterpret_cast<ARMWord>(address.m_ptr)); + m_assembler.dtrUp(ARMAssembler::LoadUint32, ARMRegisters::S1, ARMRegisters::S1, 0); add32(imm, ARMRegisters::S1); - m_assembler.ldr_un_imm(ARMRegisters::S0, reinterpret_cast<ARMWord>(address.m_ptr)); - m_assembler.dtr_u(ARMAssembler::StoreUint32, ARMRegisters::S1, ARMRegisters::S0, 0); + m_assembler.ldrUniqueImmediate(ARMRegisters::S0, reinterpret_cast<ARMWord>(address.m_ptr)); + m_assembler.dtrUp(ARMAssembler::StoreUint32, ARMRegisters::S1, ARMRegisters::S0, 0); } void sub32(TrustedImm32 imm, AbsoluteAddress address) { - m_assembler.ldr_un_imm(ARMRegisters::S1, reinterpret_cast<ARMWord>(address.m_ptr)); - m_assembler.dtr_u(ARMAssembler::LoadUint32, ARMRegisters::S1, ARMRegisters::S1, 0); + m_assembler.ldrUniqueImmediate(ARMRegisters::S1, reinterpret_cast<ARMWord>(address.m_ptr)); + m_assembler.dtrUp(ARMAssembler::LoadUint32, ARMRegisters::S1, ARMRegisters::S1, 0); sub32(imm, ARMRegisters::S1); - m_assembler.ldr_un_imm(ARMRegisters::S0, reinterpret_cast<ARMWord>(address.m_ptr)); - m_assembler.dtr_u(ARMAssembler::StoreUint32, ARMRegisters::S1, ARMRegisters::S0, 0); + m_assembler.ldrUniqueImmediate(ARMRegisters::S0, reinterpret_cast<ARMWord>(address.m_ptr)); + m_assembler.dtrUp(ARMAssembler::StoreUint32, ARMRegisters::S1, ARMRegisters::S0, 0); } void load32(const void* address, RegisterID dest) { - m_assembler.ldr_un_imm(ARMRegisters::S0, reinterpret_cast<ARMWord>(address)); - m_assembler.dtr_u(ARMAssembler::LoadUint32, dest, ARMRegisters::S0, 0); + m_assembler.ldrUniqueImmediate(ARMRegisters::S0, reinterpret_cast<ARMWord>(address)); + m_assembler.dtrUp(ARMAssembler::LoadUint32, dest, ARMRegisters::S0, 0); } Jump branch32(RelationalCondition cond, AbsoluteAddress left, RegisterID right) @@ -893,10 +893,10 @@ public: void relativeTableJump(RegisterID index, int scale) { ASSERT(scale >= 0 && scale <= 31); - m_assembler.add_r(ARMRegisters::pc, ARMRegisters::pc, m_assembler.lsl(index, scale)); + m_assembler.add(ARMRegisters::pc, ARMRegisters::pc, m_assembler.lsl(index, scale)); // NOP the default prefetching - m_assembler.mov_r(ARMRegisters::r0, ARMRegisters::r0); + m_assembler.mov(ARMRegisters::r0, ARMRegisters::r0); } Call call() @@ -919,7 +919,7 @@ public: DataLabelPtr moveWithPatch(TrustedImmPtr initialValue, RegisterID dest) { DataLabelPtr dataLabel(this); - m_assembler.ldr_un_imm(dest, reinterpret_cast<ARMWord>(initialValue.m_value)); + m_assembler.ldrUniqueImmediate(dest, reinterpret_cast<ARMWord>(initialValue.m_value)); return dataLabel; } @@ -985,7 +985,7 @@ public: void loadDouble(const void* address, FPRegisterID dest) { move(TrustedImm32(reinterpret_cast<ARMWord>(address)), ARMRegisters::S0); - m_assembler.fdtr_u(ARMAssembler::LoadDouble, dest, ARMRegisters::S0, 0); + m_assembler.doubleDtrUp(ARMAssembler::LoadDouble, dest, ARMRegisters::S0, 0); } void storeFloat(FPRegisterID src, BaseIndex address) @@ -1012,17 +1012,17 @@ public: void moveDouble(FPRegisterID src, FPRegisterID dest) { if (src != dest) - m_assembler.vmov_f64_r(dest, src); + m_assembler.vmov_f64(dest, src); } void addDouble(FPRegisterID src, FPRegisterID dest) { - m_assembler.vadd_f64_r(dest, dest, src); + m_assembler.vadd_f64(dest, dest, src); } void addDouble(FPRegisterID op1, FPRegisterID op2, FPRegisterID dest) { - m_assembler.vadd_f64_r(dest, op1, op2); + m_assembler.vadd_f64(dest, op1, op2); } void addDouble(Address src, FPRegisterID dest) @@ -1039,12 +1039,12 @@ public: void divDouble(FPRegisterID src, FPRegisterID dest) { - m_assembler.vdiv_f64_r(dest, dest, src); + m_assembler.vdiv_f64(dest, dest, src); } void divDouble(FPRegisterID op1, FPRegisterID op2, FPRegisterID dest) { - m_assembler.vdiv_f64_r(dest, op1, op2); + m_assembler.vdiv_f64(dest, op1, op2); } void divDouble(Address src, FPRegisterID dest) @@ -1056,12 +1056,12 @@ public: void subDouble(FPRegisterID src, FPRegisterID dest) { - m_assembler.vsub_f64_r(dest, dest, src); + m_assembler.vsub_f64(dest, dest, src); } void subDouble(FPRegisterID op1, FPRegisterID op2, FPRegisterID dest) { - m_assembler.vsub_f64_r(dest, op1, op2); + m_assembler.vsub_f64(dest, op1, op2); } void subDouble(Address src, FPRegisterID dest) @@ -1072,7 +1072,7 @@ public: void mulDouble(FPRegisterID src, FPRegisterID dest) { - m_assembler.vmul_f64_r(dest, dest, src); + m_assembler.vmul_f64(dest, dest, src); } void mulDouble(Address src, FPRegisterID dest) @@ -1083,28 +1083,28 @@ public: void mulDouble(FPRegisterID op1, FPRegisterID op2, FPRegisterID dest) { - m_assembler.vmul_f64_r(dest, op1, op2); + m_assembler.vmul_f64(dest, op1, op2); } void sqrtDouble(FPRegisterID src, FPRegisterID dest) { - m_assembler.vsqrt_f64_r(dest, src); + m_assembler.vsqrt_f64(dest, src); } void absDouble(FPRegisterID src, FPRegisterID dest) { - m_assembler.vabs_f64_r(dest, src); + m_assembler.vabs_f64(dest, src); } void negateDouble(FPRegisterID src, FPRegisterID dest) { - m_assembler.vneg_f64_r(dest, src); + m_assembler.vneg_f64(dest, src); } void convertInt32ToDouble(RegisterID src, FPRegisterID dest) { - m_assembler.vmov_vfp32_r(dest << 1, src); - m_assembler.vcvt_f64_s32_r(dest, dest << 1); + m_assembler.vmov_vfp32(dest << 1, src); + m_assembler.vcvt_f64_s32(dest, dest << 1); } void convertInt32ToDouble(Address src, FPRegisterID dest) @@ -1122,20 +1122,20 @@ public: void convertFloatToDouble(FPRegisterID src, FPRegisterID dst) { - m_assembler.vcvt_f64_f32_r(dst, src); + m_assembler.vcvt_f64_f32(dst, src); } void convertDoubleToFloat(FPRegisterID src, FPRegisterID dst) { - m_assembler.vcvt_f32_f64_r(dst, src); + m_assembler.vcvt_f32_f64(dst, src); } Jump branchDouble(DoubleCondition cond, FPRegisterID left, FPRegisterID right) { - m_assembler.vcmp_f64_r(left, right); + m_assembler.vcmp_f64(left, right); m_assembler.vmrs_apsr(); if (cond & DoubleConditionBitSpecial) - m_assembler.cmp_r(ARMRegisters::S0, ARMRegisters::S0, ARMAssembler::VS); + m_assembler.cmp(ARMRegisters::S0, ARMRegisters::S0, ARMAssembler::VS); return Jump(m_assembler.jmp(static_cast<ARMAssembler::Condition>(cond & ~DoubleConditionMask))); } @@ -1148,12 +1148,12 @@ public: { truncateDoubleToInt32(src, dest); - m_assembler.add_r(ARMRegisters::S0, dest, ARMAssembler::getOp2Byte(1)); - m_assembler.bic_r(ARMRegisters::S0, ARMRegisters::S0, ARMAssembler::getOp2Byte(1)); + m_assembler.add(ARMRegisters::S0, dest, ARMAssembler::getOp2Byte(1)); + m_assembler.bic(ARMRegisters::S0, ARMRegisters::S0, ARMAssembler::getOp2Byte(1)); ARMWord w = ARMAssembler::getOp2(0x80000000); ASSERT(w != ARMAssembler::InvalidImmediate); - m_assembler.cmp_r(ARMRegisters::S0, w); + m_assembler.cmp(ARMRegisters::S0, w); return Jump(m_assembler.jmp(branchType == BranchIfTruncateFailed ? ARMAssembler::EQ : ARMAssembler::NE)); } @@ -1161,24 +1161,24 @@ public: { truncateDoubleToUint32(src, dest); - m_assembler.add_r(ARMRegisters::S0, dest, ARMAssembler::getOp2Byte(1)); - m_assembler.bic_r(ARMRegisters::S0, ARMRegisters::S0, ARMAssembler::getOp2Byte(1)); + m_assembler.add(ARMRegisters::S0, dest, ARMAssembler::getOp2Byte(1)); + m_assembler.bic(ARMRegisters::S0, ARMRegisters::S0, ARMAssembler::getOp2Byte(1)); - m_assembler.cmp_r(ARMRegisters::S0, ARMAssembler::getOp2Byte(0)); + m_assembler.cmp(ARMRegisters::S0, ARMAssembler::getOp2Byte(0)); return Jump(m_assembler.jmp(branchType == BranchIfTruncateFailed ? ARMAssembler::EQ : ARMAssembler::NE)); } // Result is undefined if the value is outside of the integer range. void truncateDoubleToInt32(FPRegisterID src, RegisterID dest) { - m_assembler.vcvt_s32_f64_r(ARMRegisters::SD0 << 1, src); - m_assembler.vmov_arm32_r(dest, ARMRegisters::SD0 << 1); + m_assembler.vcvt_s32_f64(ARMRegisters::SD0 << 1, src); + m_assembler.vmov_arm32(dest, ARMRegisters::SD0 << 1); } void truncateDoubleToUint32(FPRegisterID src, RegisterID dest) { - m_assembler.vcvt_u32_f64_r(ARMRegisters::SD0 << 1, src); - m_assembler.vmov_arm32_r(dest, ARMRegisters::SD0 << 1); + m_assembler.vcvt_u32_f64(ARMRegisters::SD0 << 1, src); + m_assembler.vmov_arm32(dest, ARMRegisters::SD0 << 1); } // Convert 'src' to an integer, and places the resulting 'dest'. @@ -1187,11 +1187,11 @@ public: // (specifically, in this case, 0). void branchConvertDoubleToInt32(FPRegisterID src, RegisterID dest, JumpList& failureCases, FPRegisterID fpTemp) { - m_assembler.vcvt_s32_f64_r(ARMRegisters::SD0 << 1, src); - m_assembler.vmov_arm32_r(dest, ARMRegisters::SD0 << 1); + m_assembler.vcvt_s32_f64(ARMRegisters::SD0 << 1, src); + m_assembler.vmov_arm32(dest, ARMRegisters::SD0 << 1); // Convert the integer result back to float & compare to the original value - if not equal or unordered (NaN) then jump. - m_assembler.vcvt_f64_s32_r(ARMRegisters::SD0, ARMRegisters::SD0 << 1); + m_assembler.vcvt_f64_s32(ARMRegisters::SD0, ARMRegisters::SD0 << 1); failureCases.append(branchDouble(DoubleNotEqualOrUnordered, src, ARMRegisters::SD0)); // If the result is zero, it might have been -0.0, and 0.0 equals to -0.0 @@ -1200,14 +1200,14 @@ public: Jump branchDoubleNonZero(FPRegisterID reg, FPRegisterID scratch) { - m_assembler.mov_r(ARMRegisters::S0, ARMAssembler::getOp2Byte(0)); + m_assembler.mov(ARMRegisters::S0, ARMAssembler::getOp2Byte(0)); convertInt32ToDouble(ARMRegisters::S0, scratch); return branchDouble(DoubleNotEqual, reg, scratch); } Jump branchDoubleZeroOrNaN(FPRegisterID reg, FPRegisterID scratch) { - m_assembler.mov_r(ARMRegisters::S0, ARMAssembler::getOp2Byte(0)); + m_assembler.mov(ARMRegisters::S0, ARMAssembler::getOp2Byte(0)); convertInt32ToDouble(ARMRegisters::S0, scratch); return branchDouble(DoubleEqualOrUnordered, reg, scratch); } |