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| author | Liang Qi <liang.qi@qt.io> | 2017-07-04 15:29:25 +0200 |
|---|---|---|
| committer | Liang Qi <liang.qi@qt.io> | 2017-07-04 15:30:15 +0200 |
| commit | db2ecc45564609f940ff564e777f76a1a4b734d4 (patch) | |
| tree | d4756dffb486a2a1c64f13402bafd0327b7ddbb3 /Source/JavaScriptCore/assembler/MacroAssemblerMIPS.h | |
| parent | 8231f9776c2e4028937411bd2a0886aa72c97831 (diff) | |
| parent | d10511e0a3f655ab2b1dfebfd9c17ade151a7cfe (diff) | |
| download | qtwebkit-db2ecc45564609f940ff564e777f76a1a4b734d4.tar.gz | |
Merge remote-tracking branch 'origin/5.212' into dev
Change-Id: I006cd9023fadc5407bbaa2ddfda45cb8e88b548b
Diffstat (limited to 'Source/JavaScriptCore/assembler/MacroAssemblerMIPS.h')
| -rw-r--r-- | Source/JavaScriptCore/assembler/MacroAssemblerMIPS.h | 52 |
1 files changed, 47 insertions, 5 deletions
diff --git a/Source/JavaScriptCore/assembler/MacroAssemblerMIPS.h b/Source/JavaScriptCore/assembler/MacroAssemblerMIPS.h index a1e67e262..d43ffd22a 100644 --- a/Source/JavaScriptCore/assembler/MacroAssemblerMIPS.h +++ b/Source/JavaScriptCore/assembler/MacroAssemblerMIPS.h @@ -816,7 +816,53 @@ public: void load16Unaligned(BaseIndex address, RegisterID dest) { - load16(address, dest); + if (address.offset >= -32768 && address.offset <= 32767 && !m_fixedWidth) { + /* + sll addrtemp, address.index, address.scale + addu addrtemp, addrtemp, address.base + lbu immTemp, address.offset+x(addrtemp) (x=0 for LE, x=1 for BE) + lbu dest, address.offset+x(addrtemp) (x=1 for LE, x=0 for BE) + sll dest, dest, 8 + or dest, dest, immTemp + */ + m_assembler.sll(addrTempRegister, address.index, address.scale); + m_assembler.addu(addrTempRegister, addrTempRegister, address.base); +#if CPU(BIG_ENDIAN) + m_assembler.lbu(immTempRegister, addrTempRegister, address.offset + 1); + m_assembler.lbu(dest, addrTempRegister, address.offset); +#else + m_assembler.lbu(immTempRegister, addrTempRegister, address.offset); + m_assembler.lbu(dest, addrTempRegister, address.offset + 1); +#endif + m_assembler.sll(dest, dest, 8); + m_assembler.orInsn(dest, dest, immTempRegister); + } else { + /* + sll addrTemp, address.index, address.scale + addu addrTemp, addrTemp, address.base + lui immTemp, address.offset >> 16 + ori immTemp, immTemp, address.offset & 0xffff + addu addrTemp, addrTemp, immTemp + lbu immTemp, x(addrtemp) (x=0 for LE, x=1 for BE) + lbu dest, x(addrtemp) (x=1 for LE, x=0 for BE) + sll dest, dest, 8 + or dest, dest, immTemp + */ + m_assembler.sll(addrTempRegister, address.index, address.scale); + m_assembler.addu(addrTempRegister, addrTempRegister, address.base); + m_assembler.lui(immTempRegister, address.offset >> 16); + m_assembler.ori(immTempRegister, immTempRegister, address.offset); + m_assembler.addu(addrTempRegister, addrTempRegister, immTempRegister); +#if CPU(BIG_ENDIAN) + m_assembler.lbu(immTempRegister, addrTempRegister, 1); + m_assembler.lbu(dest, addrTempRegister, 0); +#else + m_assembler.lbu(immTempRegister, addrTempRegister, 0); + m_assembler.lbu(dest, addrTempRegister, 1); +#endif + m_assembler.sll(dest, dest, 8); + m_assembler.orInsn(dest, dest, immTempRegister); + } } void load32WithUnalignedHalfWords(BaseIndex address, RegisterID dest) @@ -2645,8 +2691,6 @@ public: Jump branchEqual(RegisterID rs, RegisterID rt) { - m_assembler.nop(); - m_assembler.nop(); m_assembler.appendJump(); m_assembler.beq(rs, rt, 0); m_assembler.nop(); @@ -2656,8 +2700,6 @@ public: Jump branchNotEqual(RegisterID rs, RegisterID rt) { - m_assembler.nop(); - m_assembler.nop(); m_assembler.appendJump(); m_assembler.bne(rs, rt, 0); m_assembler.nop(); |